GB1096019A - Electrically isolated semiconductor devices and method of producing electrically isolated semiconductor devices on common crystalline substrate - Google Patents

Electrically isolated semiconductor devices and method of producing electrically isolated semiconductor devices on common crystalline substrate

Info

Publication number
GB1096019A
GB1096019A GB4925664A GB4925664A GB1096019A GB 1096019 A GB1096019 A GB 1096019A GB 4925664 A GB4925664 A GB 4925664A GB 4925664 A GB4925664 A GB 4925664A GB 1096019 A GB1096019 A GB 1096019A
Authority
GB
United Kingdom
Prior art keywords
silicon
layer
substrate
slots
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB4925664A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
North American Aviation Corp
Original Assignee
North American Aviation Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by North American Aviation Corp filed Critical North American Aviation Corp
Publication of GB1096019A publication Critical patent/GB1096019A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291Oxides or nitrides or carbides, e.g. ceramics, glass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

<PICT:1096019/C6-C7/1> <PICT:1096019/C6-C7/2> A plurality of electrically isolated semi-conductor regions are carried by a common crystalline substrate and are spaced apart by a grid of crystalline material which may be integral with the substrate. The isolation between the regions and the substrate and the region and the grid is provided by one or more films of insulating material. To produce the arrangement of Fig. 9 a semi-conductor body containing N and N+ layers 10, 11 is provided with a patterned masking layer 20 on the N+ layer. Deep slots are then etched into the body while retaining a unitary structure. The body is then cleaned and an insulating layer 201 formed on the N+ layer and on the walls of the slots. The substrate material is now deposited to fill the slots and form the layer 30 the surface of which is lapped parallel to the surface of the insulation 201. The surface of the N type layer 10 is now lapped parallel to the surface of the substrate and to sufficient depth to separate the original semi-conductor body into isolated regions 35 in which circuit elements are to be produced. The masking layer 20 may be an oxide or nitride layer patterned by photo-resist techniques or the layer may be simply photo-resist material. The embodiment of Fig. 16 may have silicon N and N+ layers 10, 11, a silicon substrate, and silicon dioxide insulating layers. The N+ layer of the starting body 10, 11 is coated with silicon dioxide 201, and a substantially intrinsic silicon substrate layer 30 is deposited on this. An upper silicon masking layer (36) is produced on the N type layer 10 and slots etched through the semi-conductor body to the oxide layer 201. Further silicon dioxide 37 is deposited to coat the walls of the slots and silicon carbide particles are formed on this material to act as nucleating centres when the slots are filled with polycrystalline silicon 40. The upper insulating layer (36) is then lapped off to ready the assembly for further processing. In general suitable substrate materials are silicon, germanium, alumina, and beryllia; suitable materials for the insulating films are silicon dioxide, a silicon nitride (e.g. Si3N4, Si3N2, or SiN), germanium, cadmium sulphide, and intermetallic compounds such as gallium arsenide, gallium phosphide, and indium antimonide. Specific etchants are described which attack some of the semi-conductors listed rather than a silicon oxide or nitride masking layer. Methods of forming silicon dioxide and nitride coatings on silicon and other semi-conductors are described. Polycrystalline silicon may be grown readily on a silicon dioxide film by first depositing carbon on the latter from a colloidal graphite suspension or by the decomposition of a hydrocarbon, by heating the oxide to form particles of silicon carbide on its surface, and by passing over the heated layer hydrogen to which a large quantity of silicon tetrachloride is added - the silicon carbide particles act as nucleating points for the deposited silicon.ALSO:Crystalline silicon is grown on a silicon dioxide film by first depositing carbon on the latter from a colloidal graphite suspension or by the decomposition of a hydrocarbon, then heating the oxide to form particles of silicon carbide on its surface, and passing over the heated layer hydrogen to which a large quantity of silicon tetrachloride is added-the silicon carbon particles act as nucleating points for the deposited silicon.
GB4925664A 1963-12-04 1964-12-03 Electrically isolated semiconductor devices and method of producing electrically isolated semiconductor devices on common crystalline substrate Expired GB1096019A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US32799063A 1963-12-04 1963-12-04
US33971764A 1964-01-23 1964-01-23

Publications (1)

Publication Number Publication Date
GB1096019A true GB1096019A (en) 1967-12-20

Family

ID=26986163

Family Applications (1)

Application Number Title Priority Date Filing Date
GB4925664A Expired GB1096019A (en) 1963-12-04 1964-12-03 Electrically isolated semiconductor devices and method of producing electrically isolated semiconductor devices on common crystalline substrate

Country Status (3)

Country Link
CA (1) CA942893A (en)
DK (1) DK116524B (en)
GB (1) GB1096019A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182032A2 (en) * 1984-09-19 1986-05-28 Kabushiki Kaisha Toshiba SoI semiconductor device and method for producing it

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182032A2 (en) * 1984-09-19 1986-05-28 Kabushiki Kaisha Toshiba SoI semiconductor device and method for producing it
EP0182032A3 (en) * 1984-09-19 1988-03-23 Kabushiki Kaisha Toshiba Soi semiconductor device and method for producing it

Also Published As

Publication number Publication date
CA942893A (en) 1974-02-26
DK116524B (en) 1970-01-19

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