GB1089541A - Logical electric circuits - Google Patents

Logical electric circuits

Info

Publication number
GB1089541A
GB1089541A GB14518/63A GB1451863A GB1089541A GB 1089541 A GB1089541 A GB 1089541A GB 14518/63 A GB14518/63 A GB 14518/63A GB 1451863 A GB1451863 A GB 1451863A GB 1089541 A GB1089541 A GB 1089541A
Authority
GB
United Kingdom
Prior art keywords
winding
cores
inhibit
output
windings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB14518/63A
Inventor
Reginald Hugh Allmark
James Raymond Ellison
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
English Electric Co Ltd
Original Assignee
English Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by English Electric Co Ltd filed Critical English Electric Co Ltd
Priority to GB14518/63A priority Critical patent/GB1089541A/en
Priority to US357594A priority patent/US3353105A/en
Priority to FR970160A priority patent/FR1393736A/en
Priority to NL6403816A priority patent/NL6403816A/xx
Publication of GB1089541A publication Critical patent/GB1089541A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/098—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using thyristors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices

Abstract

1,089,541. Logical circuits using magnetic cores. ENGLISH ELECTRIC CO, Ltd. April 9, 1964 [April 11, 1963] No. 14518/63. Heading H3B. A logical circuit includes a magnetic core HO having a primary winding PO energized by current pulses, an inhibit winding IO controllable by logical operands to have either a high or a low impedance, and a secondary winding SO for producing output e.m.f's representative of the negation of the operand or operands. Fig. 1 shows a three input AND circuit in which the inhibit circuit has two yarallel portions each including a diode and a gate, the gates being controlled in response to inputs A and B respectively. A third input C is applied to the secondary winding. The output will exceed a predetermined value only when A, B and C are all present, since a voltage is induced in SO only when IO has a high impedance. To maintain the impedance of the primary circuit constant a second magnetic core may be provided with its primary winding in series with the first primary winding, the second core having an inhibit winding but no secondary winding. In this arrangement one of the parallel portions of the first inhibit circuit is omitted, and the gate in the second inhibit circuit is controlled in response to input A. The output from the secondary winding is A.C. In Fig. 3 equivalence and non-equivalence functions are produced using four cores. Cores H3, H4 have their secondary windings connected in series to form a single winding S2, and cores H5, H6 have a secondary winding S3. The inhibit windings are controlled as shown so that either winding I3 or I4 has a high impedance when A is equivalent to B, giving an output from S2, and so that either I5 or I6 has a high impedance when A is not equivalent to B, giving an output from S3. Fig. 4 shows a stage of a parallel binary multiplier in which two cases H7, H8 each have two secondary windings S4, S6, S7 and S5, while two further cores H9, H10 each have one secondary winding S8 and S9. With the gates and windings S6, S7, S8, S9 energized as shown by the carry C and sum S from a previous stage, and a new multiplicand M, and the negations of each, outputs are derived representing the new sum and carry and their negation. Devices using more than one core may be modified by the use of one or more pieces of magnetic material having a number of apertures equal to the number of cores originally used. Several stages of a binary multiplier may be formed on a single sheet of magnetic material. The drive current pulses in the primary windings are preferably insufficient to saturate the cores.
GB14518/63A 1963-04-11 1963-04-11 Logical electric circuits Expired GB1089541A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB14518/63A GB1089541A (en) 1963-04-11 1963-04-11 Logical electric circuits
US357594A US3353105A (en) 1963-04-11 1964-04-06 Logical electric circuits
FR970160A FR1393736A (en) 1963-04-11 1964-04-08 Logic electric circuit, in particular for parallel binary multiplier
NL6403816A NL6403816A (en) 1963-04-11 1964-04-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB14518/63A GB1089541A (en) 1963-04-11 1963-04-11 Logical electric circuits

Publications (1)

Publication Number Publication Date
GB1089541A true GB1089541A (en) 1967-11-01

Family

ID=10042656

Family Applications (1)

Application Number Title Priority Date Filing Date
GB14518/63A Expired GB1089541A (en) 1963-04-11 1963-04-11 Logical electric circuits

Country Status (3)

Country Link
US (1) US3353105A (en)
GB (1) GB1089541A (en)
NL (1) NL6403816A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0411341A3 (en) * 1989-07-10 1992-05-13 Yozan Inc. Neural network

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2846667A (en) * 1954-05-17 1958-08-05 Librascope Inc Magnetic pulse controlling device
US3091961A (en) * 1960-05-11 1963-06-04 Piell Reinhart Load-cell mounting for mill-roll chock
NL125083C (en) * 1960-11-03
US3182249A (en) * 1961-12-01 1965-05-04 Aerospace Products Res Corp Impedance controlled reactor device

Also Published As

Publication number Publication date
NL6403816A (en) 1964-10-12
US3353105A (en) 1967-11-14

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