GB1065436A - Apparatus for determining peak values in digital form of an analog signal - Google Patents

Abstract

1,065,436. Analogue-to-digital converters. ADAGE Inc. July 16, 1965 [July 17, 1964], No. 30237/65. Heading G4H. In an analogue-to-digital-converter of the feedback balancing type for digitizing amplitude peaks in the analogue input signal, the latter is applied to a summing junction together with the analogue feedback signal, and pulses are provided in one of two states, dependent on the polarity of the summing junction output, to control the operation of peak determining means to apply an analogue bias signal to the summing junction. The summing junction output is inverted or not depending on the state (plus or minus respectively) of an associated sign flip-flop, and then routes clock pulses to a SHIFT or STEP line when positive or negative respectively. Initially a start pulse sets the sign flip-flop to plus and places a programmer in a " sign test " state in which the sign flip-flop is set to minus if the summing junction output is negative. An " overload test " state now occurs in which operation ends if the required digital output would exceed the capacity of the counter used in the converter. If it wouldn't, a " count " state follows in which the most significant order of the counter is incremented by pulses on the STEP line (all lower orders holding their maximum values) until the summing junction output changes polarity when a pulse on the SHIFT lines advances the programmer to route succeeding STEP pulses to the next most significant counter order (which starts at zero), and so on until the analogue feedback voltage (obtained from a digital-to-analogue-converter controlled by the counter and the sign flip-flop) balances the analogue input voltage. A SHIFT pulse then advances the programmer to a " recycle test " state in which the bias voltage is applied to the summing junction. The bias voltage is determined in magnitude by a digital number set in a register and in sign by a second sign flip-flop initially set to plus. The next clock pulse is routed to the STEP or SHIFT line depending on whether or not respectively, the analogue input signal has increased in magnitude by more than the bias value in the interval between successive clock pulses. If it has, a peak in the input has not yet occurred, and the programmer is advanced to the " count" state to perform another conversion. On the other hand, if it has not, a peak may be occurring, so the bias sign flip-flop is switched to minus. If, in the interval to the next clock pulse, the analogue input decreases in value more than the magnitude of the bias, a peak is taken to have occurred, and said next clock pulse is routed to the SHIFT line to cause print-out of the counter reading and (after a delay) a new start pulse. Otherwise, a STEP pulse is produced to advance the programmer to its " recycle test " state (see above) and switch the sign flip-flop to plus again. The use of the bias in this way discriminates against spurious peaks. Until the bias voltage is wanted, an offset voltage may take its place, the digital equivalent being passed to the register (see above) by the start pulse.