GB1023688A - Interpolative analog-to-digital converter - Google Patents

Abstract

1023688 Electric selective signalling LUFKIN RESEARCH LABORATORIES Inc 1 Sept 1964 [21 Oct 1963] 35805/64 Headings G4D and D6Y In a read-out system for plurality of analogueto-digital converter units intercoupled as a decade register and respectively representing digits of a decade progression, each unit has a coded pattern of segments and means for detecting them, first logic circuitry being coupled to one of the converter units to provide an indication of the detected digit, and second logic circuitry being responsive to the detecting means of a second converter unit and to detection of further segments of said one unit to correct reading ambiguities of said one unit. In the particular embodiment, the angular positions of four shafts of a public utility meter representing successive decimal orders of the meter reading are each digitized by a corresponding Graycoded pattern of brush-sensed segments (blocks 200, 202, 204, 206), Fig. 5, (not shown). The signals from each pattern are converted to pure binary (blocks 208, 210, 212, 214, not shown) which, possibly after incrementing or decrementing by one in the case of each decimal order except the least significant (blocks 222, 224, 226, not shown), is converted to 1-out-of-10 code (blocks 220, 228, 230, 232, not shown). The incrementing or decrementing is to correct error arising when one decimal order does not change from 9 to 0 at the same time as the next higher order increases by one. Each pattern except that for the least significant decimal order has an extra track of segments to supply an "interpolation" bit I (not shown) which is ONE when the sensed value of the pattern is either an odd decimal digit with the brushes in the upper half of the segments for that digit or an even digit with the brushes in the lower half. I (not shown) is ZERO for the other two cases (even upper or odd lower). To achieve this, each segment in the extra track has an angular width equal to that for one digit and the segments are centred on alternate inter-digit boundaries. The bit I (not shown) is combined (blocks 240, 242, 244, not shown) with the least significant pure binary bit of the pattern value to produce a bit S (not shown) indicating whether the brushes are in the upper or lower halves (see above). Logic (blocks 222, 224, 226, 246, 250, 252, not shown) is provided for each decimal order except the least significant, to be responsive to some bits of the pure binary value of the next lower decimal order, and to the bit S (not shown), to increment by one as mentioned above if the brushes are in the upper halves and the value of the next lower decimal order is 0, 1 or 2, and to decrement by one if the brushes are in the lower halves and the value of the next lower decimal order is 8 or 9. While this correction is taking place, output flip-flops in the converters 210, 212, 214 (not shown) and in the blocks 222, 224, 226 (not shown) are prevented from responding to changes in brush readings by the inhibition of a clockpulse (CL 2, not shown) necessary thereto. This inhibition is removed and increment/decrement command signals from blocks 246, 250, 252 (not shown) to blocks 222, 224, 226 (not shown) removed, by resetting of flip-flops in blocks 246, 250, 252 (not shown) which occurs when the lowest decimal order reaches 3. Provision is also made to reset the latter flip-flops when the lowest decimal order reaches 4 after an incrementing operation to prevent faulty operation due to too slow signal response (AND gate 520), Fig. 8, (not shown). The incrementing/decrementing logic may be located at a central station and used for a plurality of meters called in turn over telephone lines.