GB0304899D0 - Upgradable memory system with reconfigurable interconnect - Google Patents

Upgradable memory system with reconfigurable interconnect

Info

Publication number
GB0304899D0
GB0304899D0 GBGB0304899.8A GB0304899A GB0304899D0 GB 0304899 D0 GB0304899 D0 GB 0304899D0 GB 0304899 A GB0304899 A GB 0304899A GB 0304899 D0 GB0304899 D0 GB 0304899D0
Authority
GB
United Kingdom
Prior art keywords
memory system
reconfigurable interconnect
upgradable
upgradable memory
reconfigurable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GBGB0304899.8A
Other versions
GB2383656A (en
GB2383656B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rambus Inc
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/797,099 external-priority patent/US7610447B2/en
Application filed by Rambus Inc filed Critical Rambus Inc
Publication of GB0304899D0 publication Critical patent/GB0304899D0/en
Publication of GB2383656A publication Critical patent/GB2383656A/en
Application granted granted Critical
Publication of GB2383656B publication Critical patent/GB2383656B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10189—Non-printed connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
GB0304899A 2001-02-28 2002-02-05 Upgradable memory system with reconfigurable interconnect Expired - Lifetime GB2383656B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/797,099 US7610447B2 (en) 2001-02-28 2001-02-28 Upgradable memory system with reconfigurable interconnect
GB0202644A GB2374693B (en) 2001-02-28 2002-02-05 Upgradable memory system with reconfigurable interconnect

Publications (3)

Publication Number Publication Date
GB0304899D0 true GB0304899D0 (en) 2003-04-09
GB2383656A GB2383656A (en) 2003-07-02
GB2383656B GB2383656B (en) 2003-12-03

Family

ID=26246963

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0304899A Expired - Lifetime GB2383656B (en) 2001-02-28 2002-02-05 Upgradable memory system with reconfigurable interconnect

Country Status (1)

Country Link
GB (1) GB2383656B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7464225B2 (en) 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5852725A (en) * 1996-05-10 1998-12-22 Yen; Juei-Hsiang PCI/ISA bus single board computer card/CPU card and backplane using eisa bus connectors and eisa bus slots
US5958033A (en) * 1997-08-13 1999-09-28 Hewlett Packard Company On- the-fly partitionable computer bus for enhanced operation with varying bus clock frequencies

Also Published As

Publication number Publication date
GB2383656A (en) 2003-07-02
GB2383656B (en) 2003-12-03

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20220204