FR3107051A1 - Manufacturing process of aluminum gallium nitride (AlGaN) nanostructures - Google Patents

Abstract

The invention relates to a method for manufacturing AlGaN nanostructures (BQ) comprising the following steps: at least one step of alternating epitaxial growth (AC), said step of alternating epitaxial growth being carried out at a defined epitaxial temperature and comprising: an epitaxial growth substep (CA1) of GaN; andan AlyGa1-yN epitaxial growth substep (CA2) performed after the GaN epitaxial growth substep, y being a number greater than 0 and less than or equal to 1; said at least one alternating epitaxial growth step leading to the formation of intermediate nanostructures (BQI) in a pseudo-alloy of AlzGa1-zN resulting from the combination of the epitaxial layers, z being a number less than y; - an annealing step at an annealing temperature greater than or equal to 820 ± 20 ° C or greater by at least 100 ° C compared to the epitaxy temperature and leading to the formation of nanostructures (BQ) in AlzGa1-zN. Figure for the abstract: figure 2

Description

Process for manufacturing aluminum gallium nitride (AlGaN) nanostructures

Technical field of the invention

The present invention relates to a process for making three-dimensional (3D) islands of aluminum gallium nitride (AlGaN) of nanometric dimensions, called nanostructures. These nanostructures have two or three directions whose dimensions are less than 50 nm, and are typically between 0.1 and 20 nm. They can be quantum dots which have three directions whose dimensions are less than 50 nm, and typically between 0.1 and 20 nm.

Such nanostructures can be integrated into heterostructures of semiconductors based on aluminum and gallium nitride (AlGaN), used in various components such as light-emitting diodes (LEDs) and laser diodes (LDs) emitting in the ultra -purple (UV). The applications are very numerous, ranging from water and air purification (UVC: λ between 200-280 nm), medicine, dermatology or agriculture (UVB: λ between 280-320 nm ), photo-polymerization, micro-electronics and white light emission (UVA: λ between 320-400 nm).

State of the art

The present invention lies in the field of the fabrication of semiconductor heterostructures based on aluminum gallium nitride (AlGaN).

Currently, it is known to produce UV emitters (in particular LEDs, and in a much smaller proportion LDs) in particular using alloys (Al, Ga) N in the form of quantum wells, whose performance remains weak. Thus, if we consider LEDs, the external quantum efficiencies (η _ext ) are typically less than 4% for wavelengths less than 350 nm. This efficiency η _ext is the ratio between the number of photons emitted by the LED and the number of electrons injected into the LED. This efficiency can be determined using the following relationship:

P _opt is the power measured at the output of the LED, λ the wavelength emitted, h the constant of Planck, c the speed of light, e the charge of the electron and I the electric current injected into the LED.

This external quantum efficiency (η _ext ) is also defined as the product of the injection efficiency (η _inj ) by the internal quantum efficiency (η _int ) and the extraction efficiency (η _extract ). η _inj represents the proportion of electrons traversing the device which are effectively injected into the active region of the LED (generally made up of quantum wells), η _int defines the ratio between the number of photons emitted from the active region over the number d 'electrons injected into it and η _extract defines the ratio between the number of photons extracted from the LED on the number of photons created. Consequently, the drop in η _ext of UV LEDs may be the consequence of a decrease in η _inj , and/or η _int and/or η _extract . The internal quantum efficiency can also be referred to as IQE (Internal Quantum Efficiency). It is generally determined via the photoluminescence yield (PL), which is more easily measured.

However, the structural properties of (Al,Ga)N alloys are one of the main factors leading to low η _int (and consequently to low values of η _ext ): the manufacture of (Al,Ga)N alloys presents difficulties (very high growth temperatures (1100-1400°C), low surface mobility of aluminium) and their crystalline quality is generally very poor. In particular, the crossing dislocation densities (DDs) (i.e. which propagate along the direction of growth) are generally between a few 10 ⁹ and 10 ¹¹ cm ^-2 , typically for AlGaN heterostructures with thicknesses of order of 1 µm carried out in sapphire epitaxy by molecular beams (EJM) or sapphire epitaxy in organo-metallic vapor phase (EPVOM)). These dislocations are non-radiative recombination centers for carriers injected into the active zone and strongly degrade the optical properties of (Al,Ga)N-based heterostructures.

In particular, the yields η _int of quantum wells are at best a few percent for dislocation densities of some 10 ⁹ cm ^-2 . Indeed, the very high dislocation densities lead to a drop in the photoluminescence intensity (PL) of the quantum wells by several orders of magnitude (by a factor of 100 to 1000) between low temperatures and room temperature. The carriers (or "excitons") not being confined in the plane of the well, they can diffuse in the plane of growth due to the spatial confinement along the only direction of growth, and are likely to recombine non-radiatively on the dislocations which are non-radiative recombination centers.

In order to obtain heterostructures with low DDs, it is possible to use bulk substrates of GaN or AlN. However, in the case of AlGaN heterostructures, it is almost necessary to use exclusively AlN substrates. This necessity comes from the constraint between the different materials, which originates from the parametric mismatch between the substrate and the epitaxial layer, which is negative in the case of the growth of (Al,Ga)N layers on an AlN substrate. but which is positive in the case of the growth of layers of (Al,Ga)N on a substrate of GaN so that a layer of (Al,Ga)N is epitaxial under extensive stress on a substrate of GaN. This generates cracks, which appear for thicknesses of only a few hundred nanometers and whose density increases according to the thickness deposited. The consequence in the case of (Al,Ga)N LED structures on bulk GaN substrate, whose thickness is typically between 2 and 5 µm, is a very high density of cracks. These cracks in particular make planar technology impossible (the most commonly used LED technology) because they prevent the lateral passage of the electric current. Also, if the metal used for the electrical contacts is deposited in the cracks, the active area of the diodes can be short-circuited. Thus, cracks can render the LEDs unusable.

However, AlN substrates are extremely expensive, of very uneven quality and very low availability. With regard to heteroepitaxied AlN layers, the dislocation densities are at best some 10 ⁹ cm ^-2 for thicknesses of several µm, unless resorting to complex and therefore costly growth processes which then allow to achieve dislocation densities of between 5.10 ⁸ cm ^-2 and 2.10 ⁹ cm ^-2 , and to obtain η _int efficiencies of the order of 10 to 40% necessary for the production of LED components.

The general problem of the invention is to lead to high internal quantum efficiencies (η _int or IQE), typically greater than 10% regardless of the structural properties of the (Al, Ga) N alloys used in the active part of the LED or of the LD (or more generally of the component).

The inventors sought to implement nanostructures, and more particularly quantum boxes (QDs), instead of quantum wells generally used, which make it possible to obtain internal quantum yields η _int greater than 10%, even on layers of low crystalline qualities (typically density of DDs greater than 10 ¹⁰ cm ^-2 ) and consequently to overcome the need to use thick AlN layers (greater than 1 µm) and/or obtained with complex technological processes or alternatively to use very expensive and small-sized AlN substrates.

Indeed, one of the main interests of nanostructures, and in particular quantum dots, for (Al,Ga)N alloys is that the internal quantum yields are significantly higher than what can be obtained with quantum wells due to the strong localization of carriers (or “excitons”). Indeed, in the case of a quantum dot, the confinement at the nanometric scale along the three directions (3D) favors the radiative recombination of excitons by emission of photons. Thus, with quantum dots, the photoluminescence yields drop only very slightly (generally less than a factor of 5 depending on the temperature between 8K and 300K).

The inventors have shown that it is possible to grow GaN nanostructures on a layer of Al _x Ga _1-x N for aluminum (Al) concentrations x of between 0.20 and 1, all on a substrate of sapphire, for the production of LED devices emitting in the UVA range between 320 and 400 nm. Beyond a critical thickness, the epitaxial layer of GaN spontaneously changes from a two-dimensional (2D) morphology, i.e. a smooth layer at the atomic scale, to a three-dimensional (3D) morphology and to the formation islands of GaN of nanometric size (BQ), and this, during a growth interruption without ammonia (NH ₃ ) which is used as a source of nitrogen during the growth of the layer of Al _x Ga _{1- x} N. The epitaxial nanostructures are free of cracks and dislocations, even after the LED manufacturing steps, which is essential since, as mentioned before, the cracks can lead to short circuits and render the LEDs unusable, and the dislocations are non-radiative recombination centers. However, these epitaxial nanostructures make it possible to obtain emissions in the blue and in the UVA, but not at wavelengths less than or equal to 320 nm.

In order to make full use of the potential of (Al,Ga)N alloys for the production of devices operating in a wide UV spectral range, the inventors sought to epitaxy Al _y Ga _1-y N nanostructures on a layer of Al _x Ga _1-x N (with y less than x), which have smaller dimensions and higher densities than in the case of GaN nanostructures, in order to obtain an emission in the UVB and UVC, c that is to say at wavelengths lower than those obtained in the case of GaN nanostructures on a layer of Al _x Ga _{1 -x} N as presented previously. The problem is that the shape of Al _y Ga _1-y N nanostructures is not as homogeneous as that of GaN nanostructures: they have elongated quantum dots and symmetric quantum dots. A consequence is that the confinement of the carriers is not as efficient as for GaN, with the corollary of a reduction in the yields of photoluminescence.

To address this problem, the inventors have developed a process for manufacturing Al _y Ga _1-y N nanostructures on a layer of Al _x Ga _1-x N (with y less than x), comprising at least three steps , which makes it possible to find a more homogeneous form of quantum dots, essentially symmetrical quantum dots, and thus to find better photoluminescence yields (therefore better internal quantum yields). The three steps are:
- a vacuum step (vacuum growth interruption), to remove the NH ₃ , prior to the growth of the quantum dots;
- an Al _y Ga _1-y N epitaxy step at a temperature of between 700 and 750° C.;
- a vacuum annealing step of the epitaxial layer of Al _y Ga _1-y N at a temperature greater than or equal to 800°C.

This improvement in photoluminescence yields is attributed to the reduced lateral dimensions of the quantum dots which are here essentially symmetrical (obtained thanks to annealing at a higher temperature than for epitaxy). These small dimensions in the three directions of space limit the probability of carrier recombinations with non-radiative defects located in the vicinity of the quantum dots.

It is therefore necessary to control the formation of Al _y Ga _1-y N nanostructures and for this, it is necessary to use a high temperature annealing process. This ultimately makes it possible to achieve high internal quantum efficiencies (η _int or IQE typically greater than 10%). Without such annealing, the yields are at best of the order of one percent, or even similar to those obtained in the case of quantum wells. It appeared that, despite this optimization of the process for forming Al _y Ga _1-y N nanostructures, the optical properties of these are still degraded compared to GaN nanostructures, with an internal quantum yield of symmetrical quantum dots weaker. This drop in the internal quantum yield of the Al _y Ga _1-y N nanostructures seems to be linked to the presence of point defects within the nanostructures or to the interface between the Al _x Ga _1-x N layer and the nanostructures of 'Al _y Ga _1-y N.

The invention aims to overcome the aforementioned drawbacks.

More specifically, it aims to have a process for manufacturing AlGaN nanostructures that makes it possible to obtain emissions in a wide UV spectral range, and this, without degrading the internal quantum yields or even improving them, whatever the properties. structural properties of the (Al,Ga)N alloys used. The invention aims to lead to a strong improvement in the performance of components, and in particular of LEDs comprising these nanostructures. The invention aims in particular to control the formation of AlGaN nanostructures, in particular their homogeneity in shape.

The invention aims in particular to have a process for manufacturing nanostructures integrated in the active part of heterostructures of semiconductors based on nitrides (Al, Ga) N, emitting in the ultraviolet (λ less than or equal to 320 nm), having relatively high external quantum yields, even using substrates with dislocation densities of up to 10 ¹¹ cm ^-2 .

In order to minimize the influence of the dislocations present in the substrate, and therefore reduce the probability that a nanostructure is crossed by a dislocation, it is also desirable to form nanostructures whose lateral dimensions are less than the average distance between two dislocations.

In addition, advantageously, the invention aims to have a process for manufacturing AlGaN nanostructures that is simple to implement, in particular on an industrial scale, in particular a manufacturing process that can be implemented in conventional methods for manufacturing heterostructures of semiconductors.

The invention aims in particular to propose a process for the manufacture of UV LEDs which will make it possible to reduce the cost of manufacture and thus envisage industrial development on a larger scale.

An object of the invention making it possible to remedy these drawbacks is a process for manufacturing Al _z Ga _1-z N nanostructures on a layer of Al _x Ga _1-x N comprising the following steps:
- at least one alternate epitaxial growth step, said alternate epitaxial growth step being carried out at a defined epitaxy temperature and comprising:
a GaN epitaxial growth sub-step; And
an Al _y Ga _1-y N epitaxial growth sub-step performed after the GaN epitaxial growth sub-step, where y is a number greater than 0 and less than or equal to 1;
leading to the formation of a nanostructured Al _z Ga _1-z N pseudo-alloy resulting from the combination of the epitaxial layers, where z is a number less than y and less than x;
- an annealing step at an annealing temperature greater than or equal to 820 ± 20°C and/or at least 100°C higher than the epitaxy temperature, said annealing step leading to the formation of nanostructures in Al _z Ga _1-z N.

The annealing step makes it possible to control the formation of Al _y Ga _1-y N nanostructures, in particular to obtain a majority of symmetrical quantum dots.

A substep of epitaxial growth makes it possible to form a layer of GaN and/or a layer of Al _y Ga _1-y N. When the integer y is equal to 1, Al _y Ga _1-y N takes the form of binary compound AlN and a layer of AlN is therefore formed.

According to the invention, “alternate epitaxial growth” means growth by epitaxy by deposition of at least two different materials in at least two layers formed one after the other. According to the invention, at least one material is GaN.

It is necessary to form at least one layer other than GaN as the last epitaxial layer before the annealing step (the last epitaxial layer is therefore a layer of Al _y Ga _1-y N which can be an AlN layer if y can be equal to 1) in order to protect the GaN layer during the annealing step.

The process that is the subject of the invention is based on the formation of nanostructures by alternate epitaxial growth, a process based on the epitaxy by alternation of GaN and/or Al _y Ga _1-y N and/or AlN compounds for the manufacture of a compound (designated by the term “pseudo-alloy”) Al _z Ga _1-z N constituting the nanostructures. The annealing step makes it possible to control the formation of these Al _z Ga _{1 - z} N nanostructures.

The invention makes it possible to avoid the creation of point defects within the nanostructures of Al _z Ga _1-z N or at the interface between the layer of Al _x Ga _1-x N and the nanostructures of Al _z Ga _{1- zN} .

The inventors have in fact discovered that these defects could find a cause in the evaporation of the GaN which becomes significant around 800° C., a temperature for which the speed of evaporation is of the order of 0.045 nm/s. However, it was indicated earlier that annealing at this temperature is essential to obtain a homogeneous form of Al _y Ga _{1 -y} N quantum dots, and therefore better photoluminescence yields in the case of LEDs. To give an order of magnitude, considering an annealing time of the order of 5 minutes, and an average temperature of 820°C (evaporation rate of the order of 0.1 nm/s), a thickness of GaN of the order of 30nm can be evaporated. However, since the Al-N bonds are extremely stable under these temperature and annealing conditions, only the GaN is evaporated during the annealing step, so that the Al _y Ga _1-y N is modified due to local evaporation of GaN, which may explain the formation of point defects within the Al _y Ga _1-y N material and/or at the interface between Al _y Ga _1-y N and Al _x Ga _1-x N.

The process that is the subject of the invention anticipates and/or compensates for the loss of GaN by inserting in the process for growing Al _y Ga _{1 -y} N nanostructures at least one monolayer of GaN. This leads to Al _z Ga _1-z N nanostructures without the point defects (or at least of reduced density).

The method that is the subject of the invention thus makes it possible to achieve high performance by simplifying the process for manufacturing heterostructures, in particular by simplifying the manufacturing processes with a single epitaxial growth step (which is an alternate epitaxial growth step).

The method can include several complementary characteristics, described in the following, and which can be taken in isolation or in combination with each other, or with each other.

According to one embodiment, the step of alternate epitaxial growth further comprises a sub-step of epitaxial growth of Al _y Ga _1-y N before the sub-step of epitaxial growth of GaN.

According to one embodiment, the alternate epitaxial growth step comprises several GaN epitaxial growth sub-steps.

According to one embodiment, the step of alternate epitaxial growth further comprises at least one sub-step of epitaxial growth of AlN. The AlN layer can be formed between two layers of GaN and/or between a layer of GaN and a layer of Al _y Ga _1-y N. This is the case where the number y is less than 1.

According to one embodiment, the alternate epitaxial growth step comprises several AlN epitaxial growth sub-steps.

In particular, an AlN epitaxial growth sub-step can be performed before a GaN epitaxial growth sub-step, and/or an AlN epitaxial growth sub-step can be performed after a epitaxial of GaN. Indeed, if there are several layers of AlN and GaN, the combination of these two variants is possible (hence the expression “and/or”).

According to one embodiment, a layer of GaN has a thickness comprised between 1 and 4 monolayers of GaN, preferably between 2 and 4 monolayers of GaN, and preferably equal to 2 monolayers of GaN.

According to one embodiment, a layer of Al _y Ga _1-y N has a thickness of between 1 and 4 monolayers of Al _y Ga _1-y N, preferably between 2 and 4 monolayers of Al _y Ga _{1- y} N, and preferably equal to 2 monolayers of Al _y Ga _1-y N.

According to one embodiment, an AlN layer has a thickness of between 1 and 4 AlN monolayers, preferably between 2 and 4 AlN monolayers, and preferably equal to 2 AlN monolayers.

By “monolayer” of GaN, we mean an atomic plane of Ga bonded to an atomic plane of N, and can be seen as a half structure of the unit cell of the crystalline material GaN. The height of the monolayer corresponds to half of the crystal lattice parameter (c) of GaN, ie 0.26 nm for the wurtzite structure (c is equal to 5.185Å).

Similarly, by "monolayer" of AlN, we mean an atomic plane of Al bonded to an atomic plane of N, and can be seen as a half structure of the unit cell of the crystalline material AlN. The height of the monolayer corresponds to half of the crystal lattice parameter (c) of AlN, ie 0.25 nm for the wurtzite structure (c is equal to 4.981Å).

By "monolayer" of Al _y Ga _1-y N is meant an atomic plane of Al bound to an atomic plane of Ga and an atomic plane of N, and can be seen as a half structure of the unit cell of the crystalline material Al _y Ga _1-y N. The height of the monolayer corresponds to half of the crystal lattice parameter (c) of Al _y Ga _1-y N, i.e. between 0.25 nm (AlN) and 0, 26 nm (GaN) for a wurtzite structure, the variation as a function of the composition y of the AlGaN alloy following to the first order a Vegard law of the form:

According to one embodiment, the method comprising a plurality of alternate epitaxial growth steps leading to the formation of Al _z Ga _1-z N nanostructures. An alternate epitaxial growth step may comprise different epitaxial growth sub-steps by compared to another step of alternate epitaxial growth.

According to one embodiment, the method comprises a preliminary step of placing under vacuum, said preliminary step of placing under low pressure or under vacuum being carried out before at least one step of alternate epitaxial growth.

According to an advantageous embodiment, at least one step of alternate epitaxial growth is carried out under an atmosphere free of NH ₃ .

According to an advantageous embodiment, the epitaxy temperature is greater than or equal to 650°C, and preferably between 650°C and 750°C.

According to one embodiment, the annealing step is carried out at low pressure or under vacuum.

A second object of the invention is a process for manufacturing heterostructures including the following steps:
- supply of an Al buffer layer_xGa_1-xNOT;
- the fabrication of Al nanostructures_zGa_1-zN according to the process for manufacturing nanostructures of the invention;
said Al nanostructures_zGa_1-zN being formed on the buffer layer, and x being a number greater than y and less than 1.

According to one embodiment, the process for manufacturing heterostructures further comprises a step of:
- deposition of an Al _x' Ga _1-x' N encapsulation layer on the Al _z Ga _1-z N nanostructures.

The number x' is a number greater than 0 and greater than z but less than 1, and can be equal to the number x.

According to one embodiment, the layer of Al _x Ga _1-x N is deposited on a substrate.

The substrate can be sapphire, silicon (Si), silicon carbide (SiC), zinc oxide (ZnO), or boron nitride (BN). The substrate can also be a 2D material like graphene.

According to one embodiment, the process for manufacturing heterostructures further comprises a step of depositing a springboard layer between the Al _x Ga _1-x N layer and the substrate.

The use of a springboard layer (in particular if x is less than 1) makes it possible to promote the n- type doping necessary for the manufacture of LEDs, the AlN material being very resistive and the concentrations of carriers much lower than in AlGaN (typically at best 10 ¹⁵ cm ^-3 for AlN versus 10 ¹⁹ cm ^-3 for AlGaN).

The springboard layer can be aluminum nitride (AlN), gallium nitride (GaN) or aluminum and gallium nitride (Al,Ga)N.

The invention also relates to an Al _z Ga _1-z N nanostructure obtained by the process for manufacturing nanostructures according to the invention.

The invention also relates to a heterostructure of semiconductors based on aluminum and gallium nitride integrating the Al _z Ga _1-z N nanostructures obtained by the process for manufacturing nanostructures according to the invention.

Brief description of figures

Other characteristics and advantages of the invention will become apparent with the aid of the description which follows, given by way of illustration and not limitation, given with regard to the appended figures, among which:

represents a first embodiment of the method according to the invention, and a heterostructure obtained.

represents a second embodiment of the method according to the invention, and a heterostructure obtained.

represents a third embodiment of the method according to the invention, and a heterostructure obtained.

represents a fourth embodiment of the method according to the invention, and a heterostructure obtained.

represents a variant embodiment of the method according to the invention, and a heterostructure obtained.

is a photograph of a heterostructure obtained by a method according to the invention.

And

show results obtained on the heterostructure of figure 5.

is a schematic top view of a diode obtained according to the method of the invention.

And

illustrate the operation of the diode obtained, when the parameter y is chosen equal to 0.3 and the width of the diode is fixed at 310 μm.

Detailed description of the invention

FIGS. 1 to 4 illustrate four embodiments of the process for manufacturing Al _z Ga _1-z N nanostructures and show the intermediate and final heterostructures obtained, making it possible in particular to form a light-emitting diode or a laser diode.

Although not shown in Figures 1 to 4, the CEI buffer layer can itself be deposited on a SUB substrate. Furthermore, a springboard layer CT can be provided between the substrate SUB and the buffer layer CEI. This is shown in Figure 5.

The substrate can be made of sapphire, silicon (Si), silicon carbide (SiC), zinc oxide (ZnO), boron nitride (BN), or even a 2D material such as graphene.

The springboard layer can be aluminum nitride (AlN), gallium nitride (GaN) or aluminum and gallium nitride (Al,Ga)N.

According to a first embodiment illustrated in FIG. 1, the process for manufacturing Al _z Ga _1-z N nanostructures comprises the following steps:
- an alternate epitaxial growth step CA carried out at a defined epitaxy temperature and comprising (step a):
a first CA1 epitaxial growth substep of GaN; Then
a second sub-step of epitaxial growth CA2 of Al _y Ga _1-y N performed after the first sub-step of epitaxial growth of GaN, where y is a number greater than 0 and less than or equal to 1;
said alternate epitaxial growth step leading to the formation of a nanostructured Al _z Ga _1-z N pseudo-alloy (BQI intermediate quantum dots) resulting from the combination of the two Al _y Ga _1-y N and GaN layers, where z is a number less than y (step b);
- an annealing step at an annealing temperature equal to 820 ± 20° C. or higher by at least 100° C. with respect to the epitaxy temperature, said annealing step forming the final quantum dots BQ (step c).

The GaN layer is epitaxied on a CEI buffer layer of Al _x Ga _1-x N, where x is a number greater than y and less than or equal to 1, for example with x equal to 0.7.

For example, y is set to a value between 0.1 and 0.5.

The value z depends on the amount of material deposited in the two layers CA1, CA2 and on the respective compositions of these two layers.

After the annealing step, an Al _{x ′} Ga _{1-x ′} N CES encapsulation layer is deposited on the Al _z Ga _1-z N nanostructures (step d). The number x' is a number greater than z and less than or equal to 1, and may be equal to the number x.

Each epitaxial growth can be an epitaxy by Molecular Jet (EJM), or an epitaxy in vapor phase (EPV) with organometallics (EPVOM) or with hydrides (HVPE).

According to a second embodiment illustrated in FIG. 2, the process for manufacturing Al _z Ga _1-z N nanostructures comprises the following steps:
- an alternate epitaxial growth step CA carried out at a defined epitaxy temperature and comprising (step a):
a first substep of epitaxial growth CA2' of Al _y Ga _1-y N, where y is a number greater than 0 and less than or equal to 1; Then
a second epitaxial growth substep CA1 of GaN; Then
a third substep of epitaxial growth CA2 of Al _y Ga _1-y N;
said step of alternate epitaxial growth leading to the formation of a nanostructured Al _z Ga _1-z N pseudo-alloy (BQI intermediate quantum dots) resulting from the combination of the three layers, where z is a number less than y (step b) ,
- an annealing step at an annealing temperature equal to 820 ± 20° C. or higher by at least 100° C. with respect to the epitaxy temperature, said annealing step forming the final quantum dots BQ (step c).

The first layer of Al _y Ga _1-y N is epitaxied on an IEC buffer layer of Al _x Ga _1-x N, where x is a number greater than y and less than or equal to 1, for example with x equal to 0 ,7.

The GaN layer is epitaxied on the first layer of Al _y Ga _{1 - y} N.

For example, y is set to a value between 0.1 and 0.5.

The value z depends on the amount of material deposited in the three layers CA1, CA2, CA2' and the respective compositions of these three layers.

After the annealing step, an Al _{x ′} Ga _{1-x ′} N CES encapsulation layer is deposited on the Al _z Ga _1-z N nanostructures (step d). The number x' is a number greater than z and less than or equal to 1, and may be equal to the number x.

Each epitaxial growth can be an epitaxy by Molecular Jet (EJM), or an epitaxy in vapor phase (EPV) with organometallics (EPVOM) or with hydrides (HVPE).

According to a third embodiment illustrated in FIG. 3, the process for manufacturing Al _z Ga _1-z N nanostructures comprises the following steps:
- an alternate epitaxial growth step CA carried out at a defined epitaxy temperature and comprising (step a):
an alternation of three epitaxial growth sub-steps CA1, CA3, CA1' of GaN (CA1), of AlN (CA3) and of GaN (CA1'); Then
a last substep of epitaxial growth CA2 of Al _y Ga _1-y N, where y is a number greater than 0 and less than 1;
said step of alternate epitaxial growth leading to the formation of nanostructures having the form of BQI intermediate quantum dots in a pseudo-alloy of Al _z Ga _1-z N resulting from the combination of the four layers, where z is a number less than y ( step b);
- an annealing step at an annealing temperature equal to 820 ± 20° C. or higher by at least 100° C. with respect to the epitaxy temperature, said annealing step forming the final quantum dots BQ (step c).

The first layer is a GaN layer and it is epitaxied on an Al _x Ga _1-x N IEC buffer layer, where x is a number greater than y and less than or equal to 1, for example with x equal to 0.7 .

After the annealing step, an Al _{x ′} Ga _{1-x ′} N CES encapsulation layer is deposited on the Al _z Ga _1-z N nanostructures (step d). The number x' is a number greater than z and less than or equal to 1, and may be equal to the number x.

For example, y is set to a value between 0.1 and 0.5.

The value z depends on the amount of material deposited in the four layers CA1, CA1', CA2, CA3 and the respective compositions of these four layers.

Each epitaxial growth can be an epitaxy by Molecular Jet (EJM), or an epitaxy in vapor phase (EPV) with organometallics (EPVOM) or with hydrides (HVPE).

According to a fourth embodiment illustrated in FIG. 4, the process for manufacturing Al _z Ga _1-z N nanostructures comprises the following steps:
- an alternate epitaxial growth step CA carried out at a defined epitaxy temperature and comprising (step a):
a first substep of epitaxial growth CA2' of Al _y Ga _1-y N, where y is a number greater than 0 and less than 1; Then
an alternation of three epitaxial growth sub-steps CA1, CA3, CA1' of GaN (CA1), of AlN (CA3) and of GaN (CA1'); Then
a last substep of epitaxial growth CA2 of Al _y Ga _1-y N;
said step of alternate epitaxial growth leading to the formation of a nanostructured Al _z Ga _1-z N pseudo-alloy (BQI intermediate quantum dots) resulting from the combination of the five layers, where z is a number less than y (step b) ;
- an annealing step at an annealing temperature equal to 820 ± 20° C. or higher by at least 100° C. with respect to the epitaxy temperature, said annealing step forming the final quantum dots BQ (step c).

Alternatively, the last epitaxial growth substep can be in AlN.

The first layer of Al _y Ga _1-y N is epitaxied on an IEC buffer layer of Al _x Ga _1-x N, where x is a number greater than z and less than or equal to 1, for example with x equal to 0 ,7.

The first layer of GaN is epitaxied on the first layer of Al _y Ga _1-y N.

For example, y is set to a value between 0.1 and 0.5.

The z value depends on the amount of material deposited in the five layers CA1, CA1', CA2, CA2', CA3 and the respective compositions of these five layers.

After the annealing step, an Al _{x ′} Ga _{1-x ′} N CES encapsulation layer is deposited on the Al _z Ga _1-z N nanostructures (step d). The number x' is a number greater than y and less than or equal to 1, and can be equal to the number x.

Each epitaxial growth can be an epitaxy by Molecular Jet (EJM), or an epitaxy in vapor phase (EPV) with organometallics (EPVOM) or with hydrides (HVPE).

Other layers of AlN, of GaN and/or of Al _y Ga _1-y N can be added between the layers described above (that is to say other epitaxial growth sub-steps).

According to a variant embodiment which applies in particular to any one of the four embodiments described above, it is possible to provide several (N) stages of alternate epitaxial growth. In other words, the substeps of the alternate epitaxial growth step CA are repeated a number N of times, where N is an integer greater than or equal to 2. This makes it possible to facilitate 3D growth and control of the manufacture of nanostructures (shape, dimensions and composition) consisting of the pseudo-alloy Al _z Ga _1-z N resulting from the various layers Al _y Ga _1-y N, GaN and/or AlN deposited.

An example of this variant is illustrated in Figure 5, in which the method comprises:
- N stages of alternate epitaxial growth CA carried out at a defined epitaxy temperature, each stage of alternate epitaxial growth comprising (stages a and b):
a first CA1 epitaxial growth substep of GaN; Then
a second substep of epitaxial growth CA3 of AlN; Then
a third epitaxial growth substep CA2 of Al _y Ga _1-y N,where y is a number greater than 0 and less than 1;
said N alternate epitaxial growth steps leading to the formation of a nanostructured Al _z Ga _1-z N pseudo-alloy (BQI intermediate quantum dots) resulting from the combination of the 3N layers, where z is a number less than y (step c );
- an annealing step at an annealing temperature equal to 820 ± 20° C. or higher by at least 100° C. with respect to the epitaxy temperature, said annealing step forming the final quantum dots BQ (step d).

The GaN layer is deposited on an IEC buffer layer of Al _x Ga _1-x N, where x is a number greater than y and less than or equal to 1, for example with x equal to 0.7.

After the annealing step, an Al _x' Ga _1-x' N CES encapsulation layer is deposited on the Al _z Ga _1-z N nanostructures (step e). The number x' is a number greater than z and less than or equal to 1, and may be equal to the number x.

For example, y is set to a value between 0.1 and 0.5.

The value z depends on the amount of material deposited in the 3N layers and on the respective compositions of these 3N layers.

Furthermore, FIG. 5 illustrates the case where the buffer layer CEI is itself deposited on a substrate SUB. In addition, a springboard layer CT can be included between the substrate and the buffer layer CEI.

The substrate can be sapphire, silicon (Si), silicon carbide (SiC), zinc oxide (ZnO), boron nitride (BN), or even a 2D material such as graphene.

The springboard layer can be AlN, GaN or AlGaN.

This variant and this example can be applied to all other embodiments.

First example of realization

According to a first exemplary embodiment, the step of alternate epitaxial growth CA comprises a first sub-step of epitaxial growth CA1 of GaN; then a second sub-step of epitaxial growth CA2 of Al _y Ga _1-y N.

All these layers are epitaxial on a plane sapphire substrate (0001), the buffer layer in Al _x Ga _1-x N is oriented according to the growth plane (0001) with a composition x equal to 0.7 and the layer of Al _x' Ga _1-x' N encapsulation deposited on the Al _z Ga _1-z N nanostructures also has a composition x' equal to x, ie 0.7.

In addition, the Al _y Ga _1-y N layer has a y composition between 0.1 and 0.5, and a thickness between 2 and 4 monolayers (i.e. between 0.5 and 1 nanometers ). The GaN layer has a thickness equal to 2 monolayers, ie of the order of 0.5 nanometers.

The Al _z Ga _1-z N pseudo-alloy results from the deposition of the two GaN/Al _y Ga _1-y N layers and from the ratio between the quantity of material deposited for each of the layers and the total quantity of material.

The annealing temperature is about 100°C higher than that of the epitaxy temperature, and/or equal to about 820 ± 20°C.

Second example of realization

According to a second exemplary embodiment, the step of alternate epitaxial growth comprises a first sub-step of epitaxial growth CA2′ of Al _y Ga _1-y N; then a second substep of epitaxial growth CA1 of GaN; then a third sub-step of epitaxial growth CA2 of Al _y Ga _1-y N.

All these layers are epitaxial on a plane sapphire substrate (0001), the buffer layer in Al _x Ga _1-x N is oriented according to the growth plane (0001) with a composition x equal to 0.7 and the layer of Al _x' Ga _1-x' N encapsulation deposited on the Al _z Ga _1-z N nanostructures also has a composition x' equal to x, ie 0.7.

In addition, the two layers of Al _y Ga _1-y N have a y composition between 0.1 and 0.5, and a thickness between 2 and 4 monolayers (i.e. between 0.5 and 1 nanometers). The layer of GaN between the two layers of Al _y Ga _1-y N has a thickness equal to 2 monolayers, ie of the order of 0.5 nanometers.

The annealing temperature is about 100°C higher than that of the epitaxy temperature, and/or equal to about 820 ± 20°C.

The Al _z Ga _1-z N pseudo-alloy results from the deposition of the three layers Al _y Ga _1-y N/GaN/Al _y Ga _1-y N and from the ratio between the quantity of material deposited for each of the layers and the quantity of total material.

With the stacking of a 1 nanometer layer of Al _y Ga _1-y N (4 monolayers), where y is equal to 0.2, a 0.5 nanometer layer of GaN (2 monolayers) and of a 1 nanometer layer of Al _y Ga _1-y N where y is equal to 0.2, we obtain the production of a pseudo-alloy Al _0.18 Ga _0.82 N with a thickness of 2.5 nanometers.

By depositing these layers on a layer of Al _x Ga _1-x N, with x equal to 0.7, the inventors were able to obtain the nanostructures as illustrated in figure 6.

The optical properties of these nanostructures were then studied, in particular by photoluminescence (PL) in temperature. Emission spectra of Al _z Ga _1-z N nanostructures obtained at a temperature of 10K and at a temperature of 300K are shown in Figure 7A, in which a very small decrease in PL intensity is observed, with a Integrated photoluminescence intensity ratio of only 1.6 between 10K and 300K. Furthermore, the measurements presented in FIG. 7B confirm the high confinement of the carriers in the nanostructures as well as a high internal quantum yield.

These results demonstrate the interest of the method of the invention for growing Al _z Ga _1-z N nanostructures emitting in the ultraviolet (between 230 and 340 nm), and exhibiting high internal quantum yields, which can reach values of η _int of the order of 30% (despite the high dislocation densities, ie more than 10 ¹⁰ cm ^-2 ).

Third example of realization

A third example differs from the preceding examples in that the first layer of Al _y Ga _1-y N, with y equal to 0.3, has a thickness of 3 monolayers. The layer of GaN epitaxial on the first layer of Al _y Ga _1-y N has a thickness equal to 2 monolayers, and the second layer of Al _y Ga _1-y N epitaxial on the GaN layer, with y equal to 0.3, has a thickness of 3 monolayers.

Fourth embodiment

A fourth example differs from the preceding examples in that the first layer of Al _y Ga _1-y N, with y equal to 0.5, has a thickness of 3 monolayers. The layer of GaN epitaxial on the first layer of Al _y Ga _1-y N has a thickness equal to 2 monolayers, and the second layer of Al _y Ga _1-y N epitaxial on the GaN layer, with y equal to 0.5, has a thickness of 3 monolayers.

Light-emitting diodes can be fabricated by integrating the heterostructures thus obtained.

FIG. 8 represents a diode D formed on the substrate SUB, and comprising the springboard layer CT, the buffer layer CEI, the quantum dots BQ, the encapsulation layer CES. The diode D and therefore the substrate SUB as well as the springboard layer CT and the buffer layer CEI have a square shape with a width of between 40 and 810 μm, for example 310 μm. The quantum dots BQ and the encapsulation layer CES, formed on the buffer layer CEI have a U-shape, covering the whole of the buffer layer CEI with the exception of a part extending between a central region and an edge of the square shape. The part of the buffer layer CEI not covered by the quantum dots BQ and the encapsulation layer CES is covered with a conductive layer E1 forming a first electrode of the diode D, and the whole of the encapsulation layer CES is covered with a conductive layer forming a second electrode E2 of diode D.

FIGS. 9 and 10 illustrate the operation of the diode, when the parameter y is chosen equal to 0.3 and the width of the diode is fixed at 310 μm.

FIG. 9 represents the electroluminescence spectrum C1 of the diode. Curve C1 shows a peak at about 305 nm reaching a light intensity value of about 60 (in arbitrary units). FIG. 9 also presents, by way of comparison, a curve C2 obtained with an identical diode, subjected to the same current density of approximately 100 A/cm ² , but for which the parameter y has been set at 0.5. At about 295 nm, curve C2 shows a peak reaching a light intensity value of about 38.

FIG. 10 represents a curve C3 of variation of the external quantum efficiency of the diode as a function of the current density applied to the diode. Curve C3 which results from various measurements M1-M7, presents a maximum of approximately 0.05% reached when the current density applied to the diode is at approximately 100 A/cm². For comparison, a diode comprising nanostructures obtained by continuous growth of Al_thereGa_1-yN, with y = 0.3 reaches a maximum external quantum yield of 10^-4 %. The method described above therefore makes it possible to multiply the external quantum efficiency by a factor of 100.

In general, the different modes and variants presented can be combined with each other.

In addition, the present invention is not limited to the embodiments described above but extends to any embodiment falling within the scope of the claims.

The invention thus makes it possible to produce heterostructures comprising active layers based on AlGaN nanostructures, with small thicknesses (of the order of 1 μm, or even less), and this, even with materials with high dislocation densities (at less than 10 ¹⁰ cm ^-2 or even more than 10 ¹¹ cm ^-2 ). It makes it possible to solve the technical problem of the drop in the internal quantum efficiency, which is notably due to the high dislocation densities and which strongly limits the performance of optoelectronic devices based on AlGaN (in particular for LEDs and LDs).

Active layers based on AlGaN nanostructures can be produced on different types of substrates (sapphire, silicon, silicon carbide, zinc oxide, boron nitride, and also 2D materials such as graphene).

The invention can also be applied to different crystallographic orientations (growth planes) and crystal structures (wurtzite, cubic).

The invention makes it possible to dispense with the use of materials having low densities of defects which require either resorting to complex and costly technological processes, or the use of bulk substrates of very expensive AlN, small dimensions and few commercially available.

The invention thus makes it possible to produce electronic and optoelectronic components by taking advantage of the remarkable properties of AlGaN nanostructures.

The invention makes it possible to achieve high internal quantum efficiencies and therefore high performance of these components, and this, by simplifying the manufacturing process of the heterostructures and of the active layers, in particular by reducing the thicknesses deposited and by simplifying the manufacturing processes. to a single epitaxial growth step which is an alternating epitaxial growth step for the fabrication of the nanostructures. In addition, for the rest of the structure of the component sought, it is possible to implement "classic" epitaxy growth processes for the manufacture of the other layers constituting the structure.

In addition, it implements processes commonly used in the opto-electronics and micro-electronics industry, and does not require the development of specific devices. The invention can therefore be carried out on an industrial scale.

The targeted applications therefore concern components of the micro-electronics and opto-electronics industry, and more particularly light-emitting diodes (LEDs) and lasers (LDs) based on (Al, Ga) N materials emitting in the range of lengths d UV wave.

The invention can be applied to all substrates used for the manufacture of active AlGaN layers, in particular sapphire and silicon, or even zinc oxide and boron nitride, which offers possibilities of removing the substrate ( by selective withdrawal).

For example, the very high etching selectivity of Si compared to active nitride layers can allow the production of (micro-)structures (membranes, micro-disks, etc.) suitable for the manufacture of micro-components for electronics and photonics. . For example, it is possible to manufacture structures of the micro-disk type based on quantum dots.

This also makes it possible to use procedures for transferring nitride layers, for example according to "flip-chip" technology or the exfoliation technique (with the use of sheet (or 2D) materials such as boron nitride or graphene) and selective removal of the substrate on highly conductive materials for heat removal (operation of LEDs or LDs at high current densities) or for the deposition of Bragg mirrors or the production of laser cavities.

Claims (17)

Process for the fabrication of nanostructures (BQ) of AlGaN comprising the following steps:
- at least one alternate epitaxial growth step (CA), said alternate epitaxial growth step being carried out at a defined epitaxy temperature and comprising:
an epitaxial growth substage (CA1) of GaN; And
an Al _y Ga _1-y N epitaxial growth (CA2) sub-step performed after the GaN epitaxial growth sub-step, where y is a number greater than 0 and less than or equal to 1;
said step of alternate epitaxial growth leading to the formation of intermediate nanostructures (BQI) in a pseudo-alloy of Al _z Ga _1-z N resulting from the combination of the epitaxial layers in alternate growth, z being a number less than y;
- an annealing step at an annealing temperature greater than or equal to 820 ± 20°C or greater than or equal to at least 100°C relative to the epitaxy temperature leading to the formation of Al _z nanostructures (BQ) Ga _1-z N. Process for manufacturing nanostructures according to claim 1, the step of alternate epitaxial growth (CA) further comprising a sub-step of preliminary epitaxial growth (CA2') in Al _y Ga _1-y N, carried out before the sub-step of epitaxial growth (CA1) of GaN. A method of manufacturing nanostructures according to claim 1 or claim 2, the step of alternate epitaxial growth (CA) comprising several sub-steps of alternate epitaxial growth (CA1, CA1') of GaN. Process for manufacturing nanostructures according to one of the preceding claims, the step of alternate epitaxial growth (CA) further comprising a sub-step of epitaxial growth (CA3) of AlN. A method of manufacturing nanostructures according to claim 4, the step of alternate epitaxial growth (AC) comprising several sub-steps of epitaxial growth of AlN. Process for manufacturing nanostructures according to one of Claims 4 or 5, an AlN epitaxial growth sub-step being carried out before a GaN epitaxial growth sub-step. Process for manufacturing nanostructures according to one of Claims 4 to 6, an AlN epitaxial growth sub-step being carried out after a GaN epitaxial growth sub-step. Process for manufacturing nanostructures according to one of the preceding claims, a layer of GaN having a thickness of between 1 and 4 monolayers of GaN, preferably between 2 and 4 monolayers of GaN, and preferably equal to 2 monolayers of GaN. Process for manufacturing nanostructures according to one of the preceding claims, a layer of Al _y Ga _1-y N having a thickness of between 1 and 4 monolayers of Al _y Ga _1-y N, preferably between 2 and 4 monolayers of Al _y Ga _1-y N, and preferably equal to 2 monolayers of Al _y Ga _1-y N. Process for manufacturing nanostructures according to one of Claims 3 to 9, an AlN layer having a thickness of between 1 and 4 AlN monolayers, preferably between 2 and 4 AlN monolayers, and preferably equal to 2 AlN monolayers. Process for manufacturing nanostructures according to one of the preceding claims, comprising a plurality (N) of alternate epitaxial growth steps leading to the formation of Al _z Ga _1-z N nanostructures (BQ). Process for manufacturing nanostructures according to any one of the preceding claims, at least one step of alternate epitaxial growth being carried out under an atmosphere free of NH ₃ . Process for manufacturing nanostructures according to any one of the preceding claims, the epitaxy temperature being greater than or equal to 650°C, and preferably between 650°C and 750°C. Process for manufacturing heterostructures comprising the following steps:
- the provision of a buffer layer (CEI) of Al _x Ga _1-x N;
- the manufacture of nanostructures (BQ) of Al _z Ga _1-z N according to the method of one of claims 1 to 13;
said Al _z Ga _1-z N nanostructures being formed on the Al _x Ga _1-x N layer, and x being a number greater than y and less than 1. Method of manufacturing heterostructures according to claim 14, further comprising a step of:
- deposition of an encapsulation layer (CES) of Al _{x '} Ga _{1-x '} N on the nanostructures (BQ) of Al _z Ga _1-z N, x' being a number less than 1 and greater than z . Process for manufacturing heterostructures according to Claim 14 or 15, the buffer layer (CEI) of Al _x Ga _1-x N being deposited on a substrate (SUB). Process for manufacturing heterostructures according to any one of Claims 14 to 16, comprising a step of depositing a springboard layer (CT) between the buffer layer (CEI) of Al _x Ga _1-x N and the substrate (SUB ).