EP3542392A1 - Semiconductor heterostructures with wurtzite-type structure on zno substrate - Google Patents

Semiconductor heterostructures with wurtzite-type structure on zno substrate

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Publication number
EP3542392A1
EP3542392A1 EP17797365.8A EP17797365A EP3542392A1 EP 3542392 A1 EP3542392 A1 EP 3542392A1 EP 17797365 A EP17797365 A EP 17797365A EP 3542392 A1 EP3542392 A1 EP 3542392A1
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EP
European Patent Office
Prior art keywords
substrate
heterostructure
layer
crystal structure
semiconductor material
Prior art date
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EP17797365.8A
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German (de)
French (fr)
Inventor
Julien Brault
Mohamed AL KHALFIOUI
Benjamin Damilano
Jean-Michel CHAUVEAU
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Centre National de la Recherche Scientifique CNRS
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Centre National de la Recherche Scientifique CNRS
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Publication of EP3542392A1 publication Critical patent/EP3542392A1/en
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    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen

Definitions

  • the invention relates to a method for producing a semiconductor material heterostructure having a wurtzite crystal structure, such a heterostructure and the manufacture of electronic or optoelectronic devices from such a heterostructure.
  • the electronic and optoelectronic devices based on these materials generally comprise a heterostructure formed by so-called "active" layers deposited by epitaxy techniques on a monocrystalline substrate.
  • Sapphire is currently the most commonly used material for the production of substrates on which layers of materials III-N will be deposited, in particular because of its high availability, its window of transparency in the visible and its stability at high temperature. (> 1500 ° C).
  • the sapphire makes it possible to obtain active layers without deformation or in compressive stress, which can thus reach significant thicknesses (several tens of micrometers) without cracking.
  • this material also has very harmful disadvantages: it is insulating, which prevents the manufacture of devices with a vertical structure, and its low thermal conductivity limits the permissible power density of the devices obtained.
  • the sapphire has a crystalline structure (rhombohedral) different from that of materials III-N (wurtzite) and a high mesh size mismatch.
  • This generates crystalline defects in the structures (stacking faults, dislocations, inversions of domains of different polarity %), which makes it impossible to obtain active layers of good structural quality according to certain orientations (non and semi polar) without resorting to complex technological processes, ie with several steps in the process (masking, surface preparation, resumption of growth, ).
  • Silicon carbide has, itself, a mesh parameter close to that of many materials III-N, can be intentionally doped to allow the realization of vertical structures and its thermal conductivity is high.
  • SiC Silicon carbide
  • its industrial development is constrained by its very high cost compared to sapphire.
  • Si Silicon
  • Si is favored by its compatibility with the production lines of the microelectronics industry.
  • its crystalline structure is of the "diamond” type, and not “wurtzite", which prevents obtaining active layers of good structural quality with certain orientations.
  • the thermal expansion coefficient disagreement with the active layers is very important and can cause extensive stress in the latter and lead to the appearance of cracks. Growth on Si then requires the use of complex and expensive manufacturing processes to compensate for the extensive constraint by compressive stress.
  • ZnO zinc oxide
  • Wurtzite the wideband forbidden semiconductor materials that we want to deposit, close mesh parameters
  • a small difference in the coefficients of thermal expansion with these materials a relatively high thermal conductivity and can be intentionally doped.
  • a crystal structure of wurtzite type comprises two types of atoms; each of these two types of atoms forms a sub-network of the type hep (of the English “hexagonal close-packed", for “compact hexagonal stacking").
  • the wurtzite structure is non-centrosymmetric, and therefore often associated with piezoelectric and / or pyroelectric properties.
  • Figures 1A, 1B and 1C schematically illustrate Wurtzite structure and some of its growth plans.
  • Planars "c”, (0001) and (000-1) are called polar; planes “a” (1 1 -20) and “m” (1 -100) are called non-polar; other planes having an angle with the plane c different from 0 ° and 90 ° are called semi-polar (for example the planes (1 1 -22) and (10-12)).
  • F in t can reach several hundred or even thousands of kV / cm.
  • the optoelectronic properties of the heterostructures are strongly dependent on this field which has harmful consequences on the functioning of the components: for example, in the case of LEDs and laser diodes (LDs), it leads to a reduction of the electron-hole pair recombinations and thus of the radiative efficiency in the quantum wells as well as an offset of the radiative transitions towards the long wavelengths.
  • this field strongly modifies the band structure and the position of the energy levels in the heterostructures and therefore requires complex band engineering during device realization.
  • LEDs and LDs emitting in the visible at long wavelengths (> 500 nm) and in the ultraviolet at short wavelengths ( ⁇ 350 nm) as well as for inter-subband devices (tunneling diodes, electro-optical modulators, photodetectors, quantum cascade components, etc.), it is desirable to suppress this polarization.
  • orientations different from the orientation (0001) for example the non-polar or semi-polar orientations described above with reference to FIGS.
  • active layers of polar or semi-polar orientation deposited on a sapphire, SiC or Si substrate generally have very high defect densities, unless complex and therefore expensive manufacturing processes are used. .
  • the document WO 2015/177220 proposes to reduce the crystalline defects appearing during the epitaxy of the nitride of element III, by producing this epitaxy on the inclined flanks of the grooves which structure the surface of the zinc oxide substrate. However, this does not allow to maintain the same plane of orientation between the substrate and the element III nitride.
  • FR 3031834 propose to reduce these crystalline defects by using a buffer layer comprising aluminum nitride between the substrate and gallium nitride. Nevertheless, the mesh parameters of aluminum nitride and zinc oxide are different, which degrades the crystalline quality of the whole. It is therefore necessary to deposit a sufficiently thick layer of gallium nitride to compensate for this degradation.
  • US 2010/01 17070 discloses a light emitting device comprising semiconductor materials. This device is produced on a zinc oxide substrate on which a structured reflective layer is deposited. This structured layer is intended to improve the extraction of light inside the device. The characteristic dimensions of the structuring are therefore dependent on the desired refractive indices and the emission wavelengths of the device.
  • the aim of the invention is to improve the structural, electronic and optoelectronic properties of heterostructures in semiconductor materials, in particular with a wide band gap, having a structure crystalline wurtzite type made on ZnO substrate, with a polar orientation, non-polar or semi-polar.
  • the inventors have realized that this constraint induces a mechanism of plastic relaxation of the stressed epitaxial layer, which can occur according to various processes such as cracking, the generation of interface dislocations, .... This results in defects that degrade the electrical and / or optoelectronic properties of the heterostructure.
  • the invention makes it possible to avoid this degradation.
  • this object is achieved by a three-dimensional structuration in "mesas" of the surface of the ZnO substrate, having a flat surface, which allows the elastic relaxation of the stress in the active layers, thanks to the presence of edges free.
  • the mesas have lateral dimensions - or at least one lateral dimension - that can reach a few hundred micrometers, or even a millimeter, and each mesa can correspond to an electronic or optoelectronic device made from the heterostructure. They also have a flat upper surface parallel to the surface of the substrate, and vertical side surfaces or inclined relative thereto.
  • An object of the invention is therefore a method of manufacturing a heterostructure of semiconductor materials having a wurtzite crystal structure, comprising the following steps:
  • Said mesas may have a smaller lateral dimension of between 10 and 1000 ⁇ and a height greater than or equal to 100 nm.
  • Said structuring step can be implemented by chemical etching.
  • the method may also comprise a step of thermal treatment of the structured surface of said substrate by annealing under an oxygen stream at a temperature greater than or equal to 600 ° C., implemented before said epitaxial deposition step of at least one layer semiconductor material having a crystal structure wurtzite type.
  • Said epitaxial deposition step of at least one layer of semiconductor material having a wurtzite crystal structure can be implemented by molecular beam epitaxy.
  • the method may also comprise a step of depositing a protective thin layer on at least one surface of said substrate other than the structured surface, implemented before said step of epitaxially deposition of at least one layer of semiconductor material having a crystal structure of wurtzite type.
  • the structured surface may have a non-polar or semi-polar orientation.
  • Said or each said semiconductor material layer having a wurtzite crystal structure may comprise at least one material chosen from a binary nitride, a binary oxide, a Zn (Mg, Cd) O alloy and an Al (Ga, In) N alloy. .
  • Another object of the invention is a method of manufacturing at least one electronic or optoelectronic device comprising:
  • Yet another object of the invention is a heterostructure comprising at least one layer of semiconductor material having a wurtzite crystal structure deposited over a surface of a zinc oxide monocrystalline substrate, characterized in that that said surface is structured in mesas.
  • Said mesas may have a smaller lateral dimension of between 10 and 1000 ⁇ and a height greater than or equal to 100 nm.
  • the structured surface of said substrate may have a non-polar or semi-polar orientation.
  • Said or each said semiconductor material layer having a wurtzite crystal structure may comprise at least one material chosen from a binary nitride, a binary oxide, a Zn (Mg, Cd) O alloy and an Al (Ga, In) N alloy. .
  • Figures 1A, 1B and 1C already described, represent the wurtzite type structure and some of its crystalline planes;
  • FIGS. 2A and 2B illustrate the formation of cracks during the epitaxial growth of GaN layers on a ZnO substrate
  • FIGS. 3A-3E represent different steps of a method according to one embodiment of the invention.
  • Figure 4 shows electron microscopy images of a surface of a ZnO substrate structured in accordance with one embodiment of the invention
  • FIGS. 5A and 5B show the effect of a heat treatment step of a method according to one embodiment of the invention
  • FIGS. 6A and 6B show electron microscopy images of a GaN layer epitaxially grown on a surface of a structured ZnO substrate according to one embodiment of the invention.
  • FIG. 2A is an image of a layer 1, 1 ⁇ thick of GaN epitaxially grown on a plane ZnO substrate c (orientation (0001), polar). Cracks oriented mainly along ⁇ 1 1 -20> directions can be observed. As explained above, these cracks are caused by the voltage stresses induced by the positive parametric mismatch between the ZnO substrate and the epitaxial layer. in GaN. More generally, this effect is observed in alloys (AI, Ga) N and (Zn, Mg) 0.
  • FIG. 2B is a graph of crack density versus layer thickness. It can be seen that the critical thickness is of the order of 300 nm for the GaN / ZnO system, and that the crack density increases with the thickness of GaN, beyond this value. The consequence of these mechanisms of relaxation of the stress is that, in the case of LED structures for example, whose thickness is typically between 2 and 5 ⁇ , very high crack densities are observed.
  • FIGS. 3A-3E illustrate the various steps of a method according to one embodiment of the invention, making it possible to prevent the appearance of these cracks.
  • FIG. 3A shows a planar S substrate made of ZnO having an SD surface on which layers of wurtzite-type semiconductor materials must be epitaxially grown.
  • the orientation of this SD surface may be polar, semi-polar or non-polar.
  • the first step of the process consists of a structuring of the surface SD by three-dimensional patterns M in the form of mesas. These patterns will generate an elastic relaxation of the epitaxial layers which avoids the plastic relaxation of the stress in the active layers. This elastic relaxation is made possible thanks to the possibility of relaxation of the layers on the edge of the mesas M.
  • the structuring of the ZnO can be carried out by wet etching or by dry process or by a combination of the two methods.
  • An advantage of ZnO is the possibility of being able to use simple wet etching processes, usually with a strongly diluted acidic solution.
  • ZnO can be efficiently etched in solutions such as highly diluted HNO 3 / HCl, HF / HNO 3 and also in non-acidic solutions such as acetyl acetone. See for example the article by J. Pearton, JJ Chen, WT Lim, F. Ren and DP Norton, "Wet Chemical Etching of Wide-Bandgap Semiconductors-GaN, ZnO and SiC", ECS Transactions, 6 (2) 501-512. (2007).
  • Patterns are defined by a mask, typically a photoresist or metal, which is removed after the etching step. They can be square, circular, rectangular or diamond-shaped or elongated strips in one of the plane directions. Their lateral dimensions can vary from 100 nanometers to a few centimeters in the case of elongated strips; however, for stress relaxation to be effective it is necessary that the smallest lateral dimension does not exceed a few hundred micrometers, even a few millimeters. The use of patterns smaller than a few micrometers is possible, but hardly compatible with the manufacture of electronic or optoelectronic components. Thus, preferably, the patterns will have a smaller lateral dimension of between 10 and 1000 ⁇ .
  • the engraving depth (and therefore the height of the mesas) must be greater than the thickness of the active layers. Typically, it can vary from 100 nm to several tens of micrometers.
  • FIG. 4 shows optical microscope images of the surface of a ZnO substrate (plane c) structured by square mesas of a few hundred ⁇ of side (460 ⁇ for the left image and 315 ⁇ for the left image). right image) and a few micrometers high, obtained by wet etching using a solution of H 3 PO 4 strongly diluted in water, with a ratio 2 (H 3 PO 4 ) / 100 (H 2 O), in order to limit lateral etching.
  • the surface of the substrate is subjected to a preparation operation by heat treatment at a temperature at least equal to 600 ° C. (or even 800 ° C.) and under an oxygen flow FO (FIG. 3C).
  • This heat treatment can be preceded by a cleaning of the surface by the use of an oxygen-based plasma.
  • atomic steps are obtained on the surface of the patterns.
  • FIGS. 5A and 5B are images obtained by atomic force microscopy of the surface of a ZnO substrate (plane c) before (5A) and after (5B) a heat treatment by annealing at a temperature of 1000 ° C. for 2 minutes under a flow of oxygen.
  • the surface Before the treatment, the surface is not smooth at the atomic scale, is scratched and retains polishing residues (silica particles, one of which has been highlighted by surrounding it with a circle). After the treatment, these scratches and contaminations disappear and we can clearly observe atomic steps.
  • a deposition of a thin layer CP (FIG. 3D). These surfaces comprise the rear face and the lateral faces of the ZnO substrate.
  • This thin layer may be an oxide (for example SiO 2 ) or a refractory nitride (for example Si 3 N 4 ).
  • This deposition is carried out, for example by sputtering, before the growth of the active layers. It allows the use of epitaxial growth techniques such as organometallic vapor phase epitaxy (EPVOM, also known by the acronym MOCVD, for "Metalorganic Chemical Vapor Deposition") and hydride vapor phase epitaxy ( EPVH).
  • EPVOM organometallic vapor phase epitaxy
  • MOCVD Metalorganic Chemical Vapor Deposition
  • EPVH hydride vapor phase epitaxy
  • FIG. 3E illustrates, very schematically, the structure obtained after epitaxial deposition, directly on the structured surface of the substrate, of one or more active layers CA. More precisely, these layers are deposited directly - without the interposition of a buffer layer of a different material - on the flat upper surfaces of the mesas (unlike the document FR3031834 where it is necessary to insert a buffer layer of AlN before the epitaxy of active layers CA); they therefore have the same crystalline orientation as the ZnO substrate.
  • discontinuous layers have free edges, in correspondence of the edges of the mesas M of the substrate, which allows the relaxation of the stresses.
  • the active layers are also deposited in the grooves separating the mesas; these portions of the active layers are however not used.
  • the deposition of the active layers can be carried out by techniques such as EPVOM or EPVH. According to a preferred embodiment of the invention, however, it is rather used molecular beam epitaxy (MBE, or MBE of the English "Molecular Beam Epitaxy").
  • MBE molecular beam epitaxy
  • This growth technique is advantageous because it allows the growth of nitride materials at much lower temperatures (300 to 400 ° C lower) than those used by EPVOM, which reduces the risk of thermal decomposition of ZnO.
  • N 2 instead of ammonia (NH 3 ) as a nitrogen source using an RF plasma cell, which is not possible with the use of EPVOM as a technique. growth.
  • ZnO is very reactive with respect to ammonia.
  • this growth technique also allows the growth of ZnO / (Zn, Mg) O structures with the lowest residual dopings.
  • FIGS. 6A and 6B show optical microscopy images of the structures obtained for two different crystallographic orientations: plane c (0001) - 6A - and plane m (1 -100) - 6B.
  • the thickness of the active layer is 0.7 ⁇ and 0.6 ⁇ , respectively. In both cases, the absence of cracks is confirmed, although the deposited thickness is much greater than the critical cracking thickness (see Figure 2B).
  • FIG. 7A shows an electroluminescence spectrum obtained at ambient temperature for such a polar LED with active layers - oriented (0001) or (000-1) - based on GaN - more precisely, it is a question of a quantum well LED (In, Ga) N / GaN - 400 ⁇ side and an injection current of 20 mA.
  • the spectrum of Figure 7A is dominated by a peak emitting in the blue around 455 nm. This blue emission originates from the recombination of the carriers in the quantum wells (In, Ga) N / GaN, confirming that the fabrication of monolithic structures of GaN-based LEDs on structured ZnO substrates has been successfully carried out.
  • Fig. 7B is a graph of LED output optical power as a function of injection current; the gray curve corresponds to the devices according to the invention, the black curve to those made on unstructured substrate.
  • the invention makes it possible to obtain a strong improvement in the optical power, by at least a factor of 2 at 20 mA (from 40 to 80 ⁇ ⁇ ⁇ ) and 80 mA (from 105 to 220 ⁇ ⁇ ⁇ ) .
  • the applications of the invention mainly concern the manufacture of micro- and optoelectronic components, and more particularly LEDs, lasers, high electron mobility or power transistors, quantum well photodetectors in the near and far infrared. (called QWIP), but also quantum cascading components (lasers and detectors) that require very large active layer thicknesses.
  • QWIP quantum well photodetectors in the near and far infrared.
  • the invention makes it possible to take advantage of the very high etching selectivity of ZnO with respect to the active layers to enable the production of microstructures (membranes, micro-disks, etc.) suitable for the manufacture of microcomponents for electronics. and photonics.
  • microstructures membranes, micro-disks, etc.
  • photonics For example, it is possible to manufacture a suspended structure formed by a GaN layer previously epitaxially grown on a ZnO substrate, and then chemically etched with an acidic solution (for example H 3 PO 4 ) strongly diluted in water.
  • an acidic solution for example H 3 PO 4
  • photonic crystals or metal / metal guides by selectively removing the substrate followed by a transfer to another substrate.

Abstract

Process for fabricating a heterostructure made of semiconductor materials having a crystalline structure of wurtzite type, comprising the following steps: - structuring a surface (SD) of a zinc oxide monocrystalline substrate (S) into mesas (M); - depositing by epitaxy at least one layer (CA) of semiconductor materials having a crystalline structure of wurtzite type, forming said heterostructure, on top of the structured surface. Heterostructure obtained by such a process. Process for fabricating at least one electronic or optoelectronic device from such a heterostructure.

Description

HETEROSTRUCTURES SEMI-CONDUCTRICES AVEC STRUCTURE DE TYPE WURTZITE SUR SUBSTRAT EN ZnO  SEMICONDUCTOR HETEROSTRUCTURES WITH WURTZITE TYPE STRUCTURE ON ZNO SUBSTRATE
L'invention porte sur un procédé de fabrication d'une hétérostructure en matériaux semi-conducteurs présentant une structure cristalline de type wurtzite, sur une telle hétérostructure et sur la fabrication de dispositifs électroniques ou optoélectroniques à partir d'une telle hétérostructure.  The invention relates to a method for producing a semiconductor material heterostructure having a wurtzite crystal structure, such a heterostructure and the manufacture of electronic or optoelectronic devices from such a heterostructure.
Les matériaux semi-conducteurs à large bande interdite (bande interdite supérieure ou égale à 3 eV), et notamment les nitrures d'éléments III (lll-N), ont connu un développement considérable au cours des vingt dernières années, notamment dans le domaine de l'optoélectronique. En particulier, dans la gamme de longueur d'onde allant de l'ultra-violet (UV) au visible, les diodes électroluminescentes (LEDs) et lasers (LDs) sont couramment utilisés pour la signalétique, l'éclairage ou le stockage de données (technologie « Blu-Ray »).  Semiconductor materials with a wide forbidden band (band gap greater than or equal to 3 eV), and in particular nitrides of elements III (III-N), have undergone considerable development over the last twenty years, particularly in the field of Optoelectronics. In particular, in the wavelength range from ultraviolet (UV) to visible light-emitting diodes (LEDs) and lasers (LDs) are commonly used for signage, lighting or data storage ("Blu-Ray" technology).
Les dispositifs électroniques et optoélectroniques à base de ces matériaux comprennent généralement une hétérostructure formée par des couches, dites « actives », déposées par des techniques d'épitaxie sur un substrat monocristallin.  The electronic and optoelectronic devices based on these materials generally comprise a heterostructure formed by so-called "active" layers deposited by epitaxy techniques on a monocrystalline substrate.
Historiquement, trois substrats ont principalement été utilisés: le saphir (Al203), le silicium (Si) et le carbure de silicium (SiC). Aucun de ces substrats ne donne pleine satisfaction. Historically, three substrates have mainly been used: sapphire (Al 2 0 3 ), silicon (Si) and silicon carbide (SiC). None of these substrates give full satisfaction.
Le saphir est actuellement le matériau le plus couramment utilisé pour la réalisation de substrats sur lesquels seront déposées des couches en matériaux lll-N, notamment en raison de sa grande disponibilité, de sa fenêtre de transparence dans le visible et de sa stabilité à haute température (> 1500°C). En outre, le saphir permet d'obtenir des couches actives sans déformation ou en contrainte compressive, qui peuvent de ce fait atteindre des épaisseurs importantes (plusieurs dizaines de micromètres) sans fissuration. Cependant, ce matériau présente également des inconvénients très néfastes : il est isolant, ce qui empêche la fabrication de dispositifs à structure verticale, et sa faible conductivité thermique limite la densité de puissance admissible des dispositifs obtenus. En outre, le saphir présente une structure cristalline (rhomboédrique) différente de celle des matériaux lll-N (wurtzite) et un désaccord de paramètres de maille élevé. Cela génère des défauts cristallins dans les structures (fautes d'empilement, dislocations, inversions de domaines de polarité différente...), ce qui rend impossible l'obtention de couches actives de bonne qualité structurale selon certaines orientations (non et semi polaires) sans recours à des procédés technologiques complexes, i.e. avec plusieurs étapes dans le procédé (masquage, préparation de surface, reprise de croissance,...). Sapphire is currently the most commonly used material for the production of substrates on which layers of materials III-N will be deposited, in particular because of its high availability, its window of transparency in the visible and its stability at high temperature. (> 1500 ° C). In addition, the sapphire makes it possible to obtain active layers without deformation or in compressive stress, which can thus reach significant thicknesses (several tens of micrometers) without cracking. However, this material also has very harmful disadvantages: it is insulating, which prevents the manufacture of devices with a vertical structure, and its low thermal conductivity limits the permissible power density of the devices obtained. In addition, the sapphire has a crystalline structure (rhombohedral) different from that of materials III-N (wurtzite) and a high mesh size mismatch. This generates crystalline defects in the structures (stacking faults, dislocations, inversions of domains of different polarity ...), which makes it impossible to obtain active layers of good structural quality according to certain orientations (non and semi polar) without resorting to complex technological processes, ie with several steps in the process (masking, surface preparation, resumption of growth, ...).
Le carbure de silicium (SiC) présente, lui, un paramètre de maille proche de celui de nombreux matériaux lll-N, peut être dopé intentionnellement pour permettre la réalisation de structures verticales et sa conductivité thermique est élevée. Cependant son développement industriel est bridé par son coût très élevé par rapport au saphir.  Silicon carbide (SiC) has, itself, a mesh parameter close to that of many materials III-N, can be intentionally doped to allow the realization of vertical structures and its thermal conductivity is high. However, its industrial development is constrained by its very high cost compared to sapphire.
Le silicium (Si) est favorisé par sa compatibilité avec les lignes de production de l'industrie microélectronique. Toutefois sa structure cristalline est de type « diamant », et non « wurtzite », ce qui empêche d'obtenir des couches actives de bonne qualité structurale avec certaines orientations. En outre, le désaccord de coefficient de dilatation thermique avec les couches actives est très important et peut engendrer une contrainte extensive dans ces dernières et conduire à l'apparition de fissures. La croissance sur Si nécessite alors le recours à des procédés de fabrication complexes et coûteux afin de compenser la contrainte extensive par une contrainte compressive.  Silicon (Si) is favored by its compatibility with the production lines of the microelectronics industry. However, its crystalline structure is of the "diamond" type, and not "wurtzite", which prevents obtaining active layers of good structural quality with certain orientations. In addition, the thermal expansion coefficient disagreement with the active layers is very important and can cause extensive stress in the latter and lead to the appearance of cracks. Growth on Si then requires the use of complex and expensive manufacturing processes to compensate for the extensive constraint by compressive stress.
Plus récemment, l'utilisation d'oxyde de zinc (ZnO) a été proposée comme alternative à ces trois matériaux. En principe, ZnO présente de multiples avantages : il a la même structure cristalline (wurtzite) que les matériaux semi-conducteurs à large bande interdite que l'on veut déposer, des paramètres de maille proches, une faible différence des coefficients de dilatation thermique avec ces matériaux, une conductivité thermique relativement élevée et peut être dopé intentionnellement. Il est également possible de le séparer aisément des couches actives en raison de la grande sélectivité chimique entre les deux familles de matériaux : nitrures et oxydes. Des substrats massifs de ZnO sont disponibles, avec d'excellentes propriétés structurales et un prix abordable. Ses limitations sont liées principalement à sa faible stabilité thermique et à sa forte réactivité chimique (par exemple avec l'ammoniac (NH3)), qui peuvent conduire à une dégradation de la surface voire à sa décomposition à des températures typiquement supérieures à 750°C. En outre des contraintes extensives peuvent apparaître entre le ZnO et les couches actives à base de nitrures ou d'oxyde. More recently, the use of zinc oxide (ZnO) has been proposed as an alternative to these three materials. In principle, ZnO has many advantages: it has the same crystalline structure (wurtzite) as the wideband forbidden semiconductor materials that we want to deposit, close mesh parameters, a small difference in the coefficients of thermal expansion with these materials, a relatively high thermal conductivity and can be intentionally doped. It is also possible to separate it easily from the active layers because of the great chemical selectivity between the two families of materials: nitrides and oxides. Massive ZnO substrates are available, with excellent structural properties and an affordable price. Its limitations are mainly related to its low thermal stability and its high chemical reactivity (for example with ammonia (NH 3 )), which can lead to degradation of the surface or even its decomposition at temperatures typically greater than 750 ° C. vs. In addition, extensive stresses may appear between the ZnO and active layers based on nitrides or oxide.
Une structure cristalline de type wurtzite comprend deux types d'atomes ; chacun de ces deux types d'atomes forme un sous-réseau de type hep (de l'anglais « hexagonal close-packed », pour « empilement hexagonal compact »). La structure wurtzite est non-centrosymétrique, et donc souvent associée à des propriétés de piézoélectricité et/ou pyroélectricité. Les figures 1 A, 1 B et 1 C illustrent schématiquement la structure wurtzite et certains de ses plans de croissance. Les plans « c », (0001 ) et (000-1 ) sont dits polaires ; les plans « a » (1 1 -20) et « m » (1 -100) sont dits non polaires ; d'autres plans présentant un angle avec le plan c différent de 0° et de 90° sont dits semi- polaires (par exemple les plans (1 1 -22) et (10-12)).  A crystal structure of wurtzite type comprises two types of atoms; each of these two types of atoms forms a sub-network of the type hep (of the English "hexagonal close-packed", for "compact hexagonal stacking"). The wurtzite structure is non-centrosymmetric, and therefore often associated with piezoelectric and / or pyroelectric properties. Figures 1A, 1B and 1C schematically illustrate Wurtzite structure and some of its growth plans. Plans "c", (0001) and (000-1) are called polar; planes "a" (1 1 -20) and "m" (1 -100) are called non-polar; other planes having an angle with the plane c different from 0 ° and 90 ° are called semi-polar (for example the planes (1 1 -22) and (10-12)).
La quasi-totalité des dispositifs à base de semi-conducteurs avec structure de type wurtzite à large bande interdite sont obtenus à partir de couches actives épitaxiées selon un plan de croissance d'orientation (0001 ), donc suivant la direction <0001 >. Ces couches présentent alors un champ électrique interne, défini par Fint par la suite, qui a pour origine : Almost all devices based on semiconductors with Wurtzite type structure with a wide forbidden band are obtained from active layers epitaxied according to a plan of growth orientation (0001), so in the direction <0001>. These layers then have an internal electric field, defined by F int thereafter, which originates from:
1 ) la non coïncidence entre les barycentres des charges positives et négatives dans la structure wurtzite entraînant une composante de polarisation dite « spontanée », très élevée suivant l'axe <0001 >, et  1) the non-coincidence between the barycentres of the positive and negative charges in the wurtzite structure resulting in a so-called "spontaneous" polarization component, very high along the axis <0001>, and
2) les déformations liées au désaccord de paramètres de mailles des différents matériaux entraînant une composante de polarisation dite « piézoélectrique ».  2) the deformations related to the disagreement of mesh parameters of the different materials resulting in a so-called "piezoelectric" polarization component.
Dans une hétérostructure, Fint peut atteindre plusieurs centaines voire milliers de kV/cm. Les propriétés optoélectroniques des hétérostructures sont fortement dépendantes de ce champ qui a des conséquences néfastes sur le fonctionnement des composants : par exemple, dans le cas des LEDs et diodes lasers (LDs), il conduit à une réduction des recombinaisons des paires électron-trou et donc de l'efficacité radiative dans les puits quantiques ainsi qu'à un décalage des transitions radiatives vers les grandes longueurs d'onde. De même, pour les dispositifs inter-sous-bandes, ce champ modifie fortement la structure de bande et la position des niveaux d'énergie dans les hétérostructures et nécessite par conséquent une ingénierie de bande complexe lors de la réalisation des dispositifs. Ainsi, pour les LEDs et LDs émettant dans le visible à grandes longueurs d'onde (> 500 nm) et dans l'ultra-violet à courtes longueurs d'onde (< 350 nm) ainsi que pour les dispositifs inter-sous-bandes (diodes à effet tunnel, modulateurs électro-optiques, photodétecteurs, composants à cascade quantique, etc.), il est souhaitable de supprimer cette polarisation. In a heterostructure, F in t can reach several hundred or even thousands of kV / cm. The optoelectronic properties of the heterostructures are strongly dependent on this field which has harmful consequences on the functioning of the components: for example, in the case of LEDs and laser diodes (LDs), it leads to a reduction of the electron-hole pair recombinations and thus of the radiative efficiency in the quantum wells as well as an offset of the radiative transitions towards the long wavelengths. Similarly, for inter-subband devices, this field strongly modifies the band structure and the position of the energy levels in the heterostructures and therefore requires complex band engineering during device realization. Thus, for LEDs and LDs emitting in the visible at long wavelengths (> 500 nm) and in the ultraviolet at short wavelengths (<350 nm) as well as for inter-subband devices (tunneling diodes, electro-optical modulators, photodetectors, quantum cascade components, etc.), it is desirable to suppress this polarization.
Pour supprimer, ou à tout le moins réduire, le champ Fint il est possible d'utiliser des orientations différentes de l'orientation (0001 ), par exemple les orientations non polaires ou semi-polaires décrites plus haut en référence aux figures 1 A - 1 C. Toutefois, des couches actives d'orientation polaire ou semi-polaire déposées sur substrat saphir, SiC ou Si présentent en général de très fortes densités de défaut, à moins d'avoir recours à des procédés de fabrication complexes et donc coûteux. To suppress, or at least reduce, the field F int it is possible to use orientations different from the orientation (0001), for example the non-polar or semi-polar orientations described above with reference to FIGS. However, active layers of polar or semi-polar orientation deposited on a sapphire, SiC or Si substrate generally have very high defect densities, unless complex and therefore expensive manufacturing processes are used. .
Un des principaux avantages du ZnO en tant que substrat pour le dépôt de couches actives en matériaux semi-conducteurs ayant une structure de type wurtzite est justement de permettre l'utilisation de ces orientations non polaires ou semi-polaires, et cela à un coût modéré car des substrats massifs de ZnO ayant ces orientations sont commercialement disponibles avec d'excellentes propriétés structurales et à un prix abordable. Ainsi plusieurs groupes de recherche, dont celui des inventeurs, ont déjà publié des résultats concernant la croissance de couches actives d'orientations non polaires et semi polaires sur des substrats de ZnO d'orientation (1 1 -20) « plan a », (1 -100) « plan m » ou (10-12). Voir par exemple : J.M. Chauveau, M. Teisseire, H. Kim-Chauveau, C. Deparis, C. Morhain, B. Vinter, « Benefits of homoepitaxy on the properties of nonpolar (Zn,Mg)0/ZnO quantum wells on a-plane ZnO substrates », Appl. Phys. Lett. 97 (2010) 081903 ; One of the main advantages of ZnO as a substrate for the deposition of active layers in semiconductor materials having a wurtzite type structure is precisely to allow the use of these non-polar or semi-polar orientations, and this at a moderate cost because massive ZnO substrates having these orientations are commercially available with excellent structural properties and at an affordable price. Thus several research groups, including that of the inventors, have already published results concerning the growth of active layers of nonpolar and semi-polar orientations on ZnO substrates of orientation (1 1 -20) "plane a", ( 1 -100) "plan m" or (10-12). See for example: JM Chauveau, M. Teisseire, H. Kim-Chauveau, C. Deparis, C. Morhain, B. Vinter, "Benefits of homoepitaxy on the properties of nonpolar (Zn, Mg) 0 / ZnO quantum wells a-plane ZnO substrates Appl. Phys. Lett. 97 (2010) 081903;
- J.M. Chauveau, Y. Xia, I. Ben Taazaet-Belgacem, M. J.M. Chauveau, Y. Xia, Ben Taazaet-Belgacem, M.
Teisseire, B. Roland, M. Nemoz, J. Brault, B. Damilano, M. Leroux, B. Vinter,« Built-in electric field in ZnO based semipolar quantum wells grown on (101 -2) ZnO substrates », J Appl. Phys. Lett. 103 (2013) 262104. Teisseire, B. Roland, M. Nemoz, J. Brault, B. Damilano, M. Leroux, B. Vinter, "Built-in electric field in ZnO based semipolar quantum wells grown on (101 -2) ZnO substrates," Appl. Phys. Lett. 103 (2013) 262104.
Le document WO 2015/177220 propose de réduire les défauts cristallins apparaissant lors de l'épitaxie du nitrure d'élément III, en réalisant cette épitaxie sur les flancs inclinés des gorges qui structurent la surface du substrat d'oxyde de zinc. Cependant, cela ne permet pas de conserver le même plan d'orientation entre le substrat et le nitrure d'élément III.  The document WO 2015/177220 proposes to reduce the crystalline defects appearing during the epitaxy of the nitride of element III, by producing this epitaxy on the inclined flanks of the grooves which structure the surface of the zinc oxide substrate. However, this does not allow to maintain the same plane of orientation between the substrate and the element III nitride.
Les auteurs du document FR 3031834 proposent de réduire ces défauts cristallins en utilisant une couche tampon comprenant du nitrure d'aluminium entre le substrat et le nitrure de gallium. Néanmoins, les paramètres de maille du nitrure d'aluminium et de l'oxyde de zinc sont différents, ce qui dégrade la qualité cristalline de l'ensemble. Il faut donc déposer une couche suffisamment épaisse de nitrure de gallium pour compenser cette dégradation.  The authors of FR 3031834 propose to reduce these crystalline defects by using a buffer layer comprising aluminum nitride between the substrate and gallium nitride. Nevertheless, the mesh parameters of aluminum nitride and zinc oxide are different, which degrades the crystalline quality of the whole. It is therefore necessary to deposit a sufficiently thick layer of gallium nitride to compensate for this degradation.
Le document US 2010/01 17070 présente un dispositif d'émission de lumière comprenant des matériaux semi-conducteurs. Ce dispositif est réalisé sur un substrat d'oxyde de zinc sur lequel une couche structurée réflective est déposée. Cette couche structurée est destinée à améliorer l'extraction de la lumière à l'intérieur du dispositif. Les dimensions caractéristiques de la structuration sont donc dépendantes des indices de réfraction désirés et des longueurs d'onde d'émission du dispositif.  US 2010/01 17070 discloses a light emitting device comprising semiconductor materials. This device is produced on a zinc oxide substrate on which a structured reflective layer is deposited. This structured layer is intended to improve the extraction of light inside the device. The characteristic dimensions of the structuring are therefore dependent on the desired refractive indices and the emission wavelengths of the device.
L'invention vise à améliorer les propriétés structurales, électroniques et optoélectroniques des hétérostructures en matériaux semiconducteurs, notamment à large bande interdite, présentant une structure cristalline de type wurtzite réalisées sur substrat en ZnO, avec une orientation polaire, non polaire ou semi-polaire. The aim of the invention is to improve the structural, electronic and optoelectronic properties of heterostructures in semiconductor materials, in particular with a wide band gap, having a structure crystalline wurtzite type made on ZnO substrate, with a polar orientation, non-polar or semi-polar.
En effet, bien que les paramètres de maille entre le ZnO et les couches actives visées soient proches, il existe presque toujours un désaccord paramétrique entre le substrat et la couche épitaxiale. En particulier, ce désaccord est positif dans le cas du GaN, ΑΙΝ, ainsi que des alliages (AI,Ga)N ou (Zn,Mg)O, c'est-à-dire que les valeurs Aa I aCA et Ac I CCA avec Aa = aSUbstrat - acA et/ou Ac = cSUbstrat - CCA sont supérieures à 0, l'indice « CA » indiquant le paramètre de la couche active ; les paramètres cristallins « a » et « c » sont identifiés sur la figure 1 A. Les inventeurs se sont rendu compte que cette contrainte induit un mécanisme de relaxation plastique de la couche épitaxiale contrainte, qui peut intervenir suivant différents procédés tels que la fissuration, la génération de dislocations d'interface,.... Il en résulte des défauts qui dégradent les propriétés électriques et/ou optoélectroniques de l'hétérostructure. L'invention permet d'éviter cette dégradation. Indeed, although the mesh parameters between the ZnO and the targeted active layers are close, there is almost always a parametric mismatch between the substrate and the epitaxial layer. In particular, this disagreement is positive in the case of GaN, ΑΙΝ, as well as alloys (AI, Ga) N or (Zn, Mg) O, that is to say that the values Aa I a C A and Ac IC C A with Aa = a SU bstrat - acA and / or Ac = c SU bstrat - CCA are greater than 0, the index "CA" indicating the parameter of the active layer; the crystalline parameters "a" and "c" are identified in FIG. 1 A. The inventors have realized that this constraint induces a mechanism of plastic relaxation of the stressed epitaxial layer, which can occur according to various processes such as cracking, the generation of interface dislocations, .... This results in defects that degrade the electrical and / or optoelectronic properties of the heterostructure. The invention makes it possible to avoid this degradation.
Conformément à l'invention, ce but est atteint par une structuration tridimensionnelle en « mesas » de la surface du substrat en ZnO, présentant une surface plane, qui permet la relaxation élastique de la contrainte dans les couches actives, grâce à la présence de bords libres. Les mesas présentent des dimensions latérales - ou au moins une dimension latérale - pouvant atteindre quelques centaines de micromètres, voire un millimètre environ, et chaque mesa peut correspondre à un dispositif électronique ou optoélectronique réalisé à partir de l'hétérostructure. Elles présentent également une surface supérieure plane parallèle à la surface du substrat, ainsi que des surfaces latérales verticales ou inclinées par rapport à cette dernière.  According to the invention, this object is achieved by a three-dimensional structuration in "mesas" of the surface of the ZnO substrate, having a flat surface, which allows the elastic relaxation of the stress in the active layers, thanks to the presence of edges free. The mesas have lateral dimensions - or at least one lateral dimension - that can reach a few hundred micrometers, or even a millimeter, and each mesa can correspond to an electronic or optoelectronic device made from the heterostructure. They also have a flat upper surface parallel to the surface of the substrate, and vertical side surfaces or inclined relative thereto.
Le principe de la structuration en mesa d'un substrat a déjà été utilisé pour l'épitaxie de nitrures d'éléments III sur substrats en silicium : voir l'article de Baoshun Zhang, Hu Liang, Yong Wang, Zhihong Feng, Kar Wei Ng, Kei May Lau, «High-performance lll-nitride blue LEDs grown and fabricated on patterned Si substrates», J. Crystal Growth 298, 725 (2007). Il convient néanmoins de souligner que le mécanisme d'apparition et de relaxation des contraintes est différent pour des substrats en Si et en ZnO. Dans le premier cas, l'apparition de défauts est la conséquence des différences de coefficients de dilatation thermique entre les couches actives et le substrat. Ce mécanisme intervient donc pendant la phase de refroidissement qui suit la phase de croissance épitaxiale. En revanche, dans le cas des couches actives sur ZnO, l'apparition de défauts est la conséquence des désaccords paramétriques des mailles cristallines et intervient donc pendant l'étape de croissance épitaxiale. The principle of the mesa structuring of a substrate has already been used for the epitaxy of III elements nitride on silicon substrates: see the article by Baoshun Zhang, Hu Liang, Yong Wang, Zhihong Feng and Kar Wei Ng , Kei May Lau, "High-performance lll-nitride blue LEDs grown and fabricated on patterned substrates", J. Crystal Growth 298, 725 (2007). It should be emphasized, however, that the mechanism of appearance and Stress relaxation is different for Si and ZnO substrates. In the first case, the appearance of defects is the consequence of the differences in coefficients of thermal expansion between the active layers and the substrate. This mechanism therefore occurs during the cooling phase following the epitaxial growth phase. On the other hand, in the case of the active layers on ZnO, the appearance of defects is the consequence of the parametric disagreements of the crystalline meshes and thus intervenes during the step of epitaxial growth.
Un objet de l'invention est donc un procédé de fabrication d'une hétérostructure en matériaux semi-conducteurs présentant une structure cristalline de type wurtzite, comprenant les étapes suivantes :  An object of the invention is therefore a method of manufacturing a heterostructure of semiconductor materials having a wurtzite crystal structure, comprising the following steps:
structuration d'une surface d'un substrat monocristallin d'oxyde de zinc en mesas ; et  structuring a surface of a monocrystalline zinc oxide substrate into mesas; and
dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite, formant ladite hétérostructure, au dessus de la surface structurée.  epitaxially depositing at least one layer of semiconductor material having a wurtzite crystal structure, forming said heterostructure, above the structured surface.
Selon des modes de réalisation particulier d'un tel procédé :  According to particular embodiments of such a method:
Lesdites mesas peuvent présenter une plus petite dimension latérale comprise entre 10 et 1000 μηι et une hauteur supérieure ou égale à 100 nm.  Said mesas may have a smaller lateral dimension of between 10 and 1000 μηι and a height greater than or equal to 100 nm.
Ladite étape de structuration peut être mise en œuvre par gravure chimique.  Said structuring step can be implemented by chemical etching.
Le procédé peut comprendre également une étape de traitement thermique de la surface structurée dudit substrat par recuit sous flux d'oxygène à une température supérieure ou égale à 600°C, mise en œuvre avant ladite étape de dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite. The method may also comprise a step of thermal treatment of the structured surface of said substrate by annealing under an oxygen stream at a temperature greater than or equal to 600 ° C., implemented before said epitaxial deposition step of at least one layer semiconductor material having a crystal structure wurtzite type.
Ladite étape de dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite peut être mise en œuvre par épitaxie par jets moléculaires. Le procédé peut comprendre également une étape de dépôt d'une couche mince de protection sur au moins une surface dudit substrat autre que la surface structurée, mise en œuvre avant ladite étape de dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite. Said epitaxial deposition step of at least one layer of semiconductor material having a wurtzite crystal structure can be implemented by molecular beam epitaxy. The method may also comprise a step of depositing a protective thin layer on at least one surface of said substrate other than the structured surface, implemented before said step of epitaxially deposition of at least one layer of semiconductor material having a crystal structure of wurtzite type.
La surface structurée peut présenter une orientation non- polaire ou semi-polaire.  The structured surface may have a non-polar or semi-polar orientation.
Ladite ou chaque dite couche en matériau semiconducteur présentant une structure cristalline de type wurtzite peut comprendre au moins un matériau choisi parmi un nitrure binaire, un oxyde binaire, un alliage Zn(Mg, Cd)0 et un alliage AI(Ga, ln)N.  Said or each said semiconductor material layer having a wurtzite crystal structure may comprise at least one material chosen from a binary nitride, a binary oxide, a Zn (Mg, Cd) O alloy and an Al (Ga, In) N alloy. .
Un autre objet de l'invention est un procédé de fabrication d'au moins un dispositif électronique ou optoélectronique comprenant :  Another object of the invention is a method of manufacturing at least one electronic or optoelectronic device comprising:
la fabrication d'une hétérostructure en au moins un matériau semi-conducteur présentant une structure cristalline de type wurtzite par un procédé tel que mentionné ci-dessus;  the manufacture of a heterostructure in at least one semiconductor material having a wurtzite crystal structure by a process as mentioned above;
la fabrication dudit dispositif électronique ou optoélectronique à partir d'une région de ladite hétérostructure correspondant à une mesa de la surface structurée du substrat.  manufacturing said electronic or optoelectronic device from a region of said heterostructure corresponding to a mesa of the structured surface of the substrate.
Encore un autre objet de l'invention est une hétérostructure comprenant au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite, déposée au-dessus d'une surface d'un substrat monocristallin en oxyde de zinc, caractérisée en ce que ladite surface est structurée en mesas.  Yet another object of the invention is a heterostructure comprising at least one layer of semiconductor material having a wurtzite crystal structure deposited over a surface of a zinc oxide monocrystalline substrate, characterized in that that said surface is structured in mesas.
Selon des modes de réalisation particuliers d'une telle hétérostructure :  According to particular embodiments of such a heterostructure:
Lesdites mesas peuvent présenter une plus petite dimension latérale comprise entre 10 et 1000 μηι et une hauteur supérieure ou égale à 100 nm.  Said mesas may have a smaller lateral dimension of between 10 and 1000 μηι and a height greater than or equal to 100 nm.
La surface structurée dudit substrat peut présenter une orientation non-polaire ou semi-polaire. Ladite ou chaque dite couche en matériau semiconducteur présentant une structure cristalline de type wurtzite peut comprendre au moins un matériau choisi parmi un nitrure binaire, un oxyde binaire, un alliage Zn(Mg, Cd)O et un alliage AI(Ga, ln)N. The structured surface of said substrate may have a non-polar or semi-polar orientation. Said or each said semiconductor material layer having a wurtzite crystal structure may comprise at least one material chosen from a binary nitride, a binary oxide, a Zn (Mg, Cd) O alloy and an Al (Ga, In) N alloy. .
D'autres caractéristiques, détails et avantages de l'invention ressortiront à la lecture de la description faite en référence aux dessins annexés donnés à titre d'exemple, dans lesquelles:  Other characteristics, details and advantages of the invention will emerge on reading the description made with reference to the accompanying drawings given by way of example, in which:
Les figures 1 A, 1 B et 1 C, déjà décrites, représentent la structure de type wurtzite et certains de ses plans cristallins ;  Figures 1A, 1B and 1C, already described, represent the wurtzite type structure and some of its crystalline planes;
- Les figures 2A et 2B illustrent la formation de fissures lors de la croissance épitaxiale de couches de GaN sur un substrat en ZnO ;  FIGS. 2A and 2B illustrate the formation of cracks during the epitaxial growth of GaN layers on a ZnO substrate;
Les figures 3A - 3E représentent différentes étapes d'un procédé selon un mode de réalisation de l'invention ;  FIGS. 3A-3E represent different steps of a method according to one embodiment of the invention;
La figure 4 montre des images de microscopie électronique d'une surface d'un substrat en ZnO structurée conformément à un mode de réalisation de l'invention ;  Figure 4 shows electron microscopy images of a surface of a ZnO substrate structured in accordance with one embodiment of the invention;
Les figures 5A et 5B montrent l'effet d'une étape de traitement thermique d'un procédé selon un mode de réalisation de l'invention ;  FIGS. 5A and 5B show the effect of a heat treatment step of a method according to one embodiment of the invention;
- Les figures 6A et 6B montrent des images de microscopie électronique d'une couche de GaN épitaxiée sur une surface d'un substrat en ZnO structurée conformément à un mode de réalisation de l'invention ; et  FIGS. 6A and 6B show electron microscopy images of a GaN layer epitaxially grown on a surface of a structured ZnO substrate according to one embodiment of the invention; and
La figure 7 illustre un résultat technique de l'invention. Les figures 2A et 2B mettent en évidence le problème - non clairement identifié dans l'art antérieur - auquel la présente invention apporte une solution. La figure 2A est une image d'une couche de 1 ,1 μηι d'épaisseur de GaN épitaxiée sur un substrat de ZnO plan c (orientation (0001 ), polaire). On peut observer des fissures orientées principalement le long des directions <1 1 -20>. Comme cela a été expliqué plus haut, ces fissures sont provoquées par les contraintes en tension induites par le désaccord paramétrique positif entre le substrat en ZnO et la couche épitaxiée en GaN. Plus généralement, cet effet est observé dans les alliages (AI,Ga)N et (Zn,Mg)0. Figure 7 illustrates a technical result of the invention. Figures 2A and 2B highlight the problem - not clearly identified in the prior art - at which the present invention provides a solution. FIG. 2A is an image of a layer 1, 1 μηι thick of GaN epitaxially grown on a plane ZnO substrate c (orientation (0001), polar). Cracks oriented mainly along <1 1 -20> directions can be observed. As explained above, these cracks are caused by the voltage stresses induced by the positive parametric mismatch between the ZnO substrate and the epitaxial layer. in GaN. More generally, this effect is observed in alloys (AI, Ga) N and (Zn, Mg) 0.
Les fissures apparaissent dès que l'épaisseur de la couche épitaxiée dépasse une valeur critique ; elles se propagent depuis la surface jusqu'au substrat à travers la couche. Le critère de relaxation étant l'énergie élastique emmagasinée pendant la croissance, le nombre de fissures par unité de surface de la couche va augmenter avec l'épaisseur et la déformation initiale, quelle que soit la nature de la couche épitaxiée. La figure 2B est un graphique de la densité de fissures en fonction de l'épaisseur de la couche. On peut constater que l'épaisseur critique est de l'ordre de 300 nm pour le système GaN / ZnO, et que la densité de fissures augmente avec l'épaisseur de GaN, au-delà de cette valeur. La conséquence de ces mécanismes de relaxation de la contrainte est que, dans le cas de structures LEDs par exemple, dont l'épaisseur est typiquement comprise entre 2 et 5 μηπ, de très fortes densités de fissures sont observées. Ces fissures rendent notamment une technologie planaire impossible (technologie de LEDs la plus couramment utilisée) car elles empêchent le passage latéral du courant électrique. En outre, si le métal utilisé pour les contacts électriques est déposé dans les fissures, la zone active des diodes peut être court-circuitée.  Cracks appear as soon as the thickness of the epitaxial layer exceeds a critical value; they spread from the surface to the substrate through the layer. The relaxation criterion being the elastic energy stored during growth, the number of cracks per unit area of the layer will increase with the thickness and the initial deformation, regardless of the nature of the epitaxial layer. Figure 2B is a graph of crack density versus layer thickness. It can be seen that the critical thickness is of the order of 300 nm for the GaN / ZnO system, and that the crack density increases with the thickness of GaN, beyond this value. The consequence of these mechanisms of relaxation of the stress is that, in the case of LED structures for example, whose thickness is typically between 2 and 5 μηπ, very high crack densities are observed. These cracks in particular make a planar technology impossible (LED technology most commonly used) because they prevent lateral passage of electric current. In addition, if the metal used for the electrical contacts is deposited in the cracks, the active zone of the diodes can be short-circuited.
Les figures 3A - 3E illustrent les différentes étapes d'un procédé selon un mode de réalisation de l'invention, permettant d'empêcher l'apparition de ces fissures.  FIGS. 3A-3E illustrate the various steps of a method according to one embodiment of the invention, making it possible to prevent the appearance of these cracks.
La figure 3A montre un substrat planaire S en ZnO, présentant une surface SD sur laquelle doivent être épitaxiées des couches en matériaux semi-conducteurs à structure de type wurtzite. L'orientation de cette surface SD peut être polaire, semi-polaire ou non polaire.  FIG. 3A shows a planar S substrate made of ZnO having an SD surface on which layers of wurtzite-type semiconductor materials must be epitaxially grown. The orientation of this SD surface may be polar, semi-polar or non-polar.
La première étape du procédé, illustrée par la figure 3B, consiste en une structuration de la surface SD par des motifs tridimensionnels M en forme de mesas. Ces motifs vont engendrer une relaxation élastique des couches épitaxiées qui permet d'éviter la relaxation plastique de la contrainte dans les couches actives. Cette relaxation élastique est rendue possible grâce à la possibilité de relaxation des couches en bord des mesas M. La structuration du ZnO peut être réalisée par gravure par voie humide ou par voie sèche voire par une combinaison des deux méthodes. Un avantage du ZnO est la possibilité de pouvoir utiliser des procédés de gravure par voie humide simples, en général à l'aide d'une solution acide fortement diluée. Par exemple, il a été montré que le ZnO pouvait être efficacement gravé dans des solutions telles que HNO3/HCI, HF/HNO3 fortement diluée et également dans des solutions non acides comme l'acétyle acétone. Voir par exemple l'article de J. Pearton, J.J. Chen, W.T. Lim, F. Ren et D.P. Norton, «Wet Chemical Etching of Wide Bandgap Semiconductors-GaN, ZnO and SiC», ECS Transactions, 6 (2) 501 -512 (2007). The first step of the process, illustrated in FIG. 3B, consists of a structuring of the surface SD by three-dimensional patterns M in the form of mesas. These patterns will generate an elastic relaxation of the epitaxial layers which avoids the plastic relaxation of the stress in the active layers. This elastic relaxation is made possible thanks to the possibility of relaxation of the layers on the edge of the mesas M. The structuring of the ZnO can be carried out by wet etching or by dry process or by a combination of the two methods. An advantage of ZnO is the possibility of being able to use simple wet etching processes, usually with a strongly diluted acidic solution. For example, it has been shown that ZnO can be efficiently etched in solutions such as highly diluted HNO 3 / HCl, HF / HNO 3 and also in non-acidic solutions such as acetyl acetone. See for example the article by J. Pearton, JJ Chen, WT Lim, F. Ren and DP Norton, "Wet Chemical Etching of Wide-Bandgap Semiconductors-GaN, ZnO and SiC", ECS Transactions, 6 (2) 501-512. (2007).
Les motifs sont définis grâce à un masque, typiquement en résine photosensible ou en métal, qui est enlevé après l'étape de gravure. Ils peuvent être carrés, circulaires, rectangulaires ou en forme de losanges ou de bandes allongées dans une des directions du plan. Leurs dimensions latérales peuvent varier de 100 nanomètres à quelques centimètres dans le cas des bandes allongées ; cependant, pour que la relaxation des contraintes soit efficace il est nécessaire que la plus petite dimension latérale ne dépasse pas quelques centaines de micromètres, voire quelques millimètres. L'utilisation de motifs de dimensions inférieures à quelques micromètres est possible, mais difficilement compatible avec la fabrication de composants électroniques ou optoélectroniques. Ainsi, de préférence, les motifs présenteront une plus petite dimension latérale comprise entre 10 et 1000 μηι.  Patterns are defined by a mask, typically a photoresist or metal, which is removed after the etching step. They can be square, circular, rectangular or diamond-shaped or elongated strips in one of the plane directions. Their lateral dimensions can vary from 100 nanometers to a few centimeters in the case of elongated strips; however, for stress relaxation to be effective it is necessary that the smallest lateral dimension does not exceed a few hundred micrometers, even a few millimeters. The use of patterns smaller than a few micrometers is possible, but hardly compatible with the manufacture of electronic or optoelectronic components. Thus, preferably, the patterns will have a smaller lateral dimension of between 10 and 1000 μηι.
La profondeur de gravure (et donc la hauteur des mesas) doit être supérieure à l'épaisseur des couches actives. Typiquement, elle peut varier de 100 nm à plusieurs dizaines de micromètres.  The engraving depth (and therefore the height of the mesas) must be greater than the thickness of the active layers. Typically, it can vary from 100 nm to several tens of micrometers.
La figure 4 montre des images obtenues au microscope optique de la surface d'un substrat de ZnO (plan c) structurée par des mesas carrées de quelques centaines de μηι de côté (460 μηι pour l'image de gauche et 315 μηι pour l'image de droite) et de quelques micromètres de haut, obtenus par gravure par voie humide en utilisant une solution de H3PO4 fortement diluée dans de l'eau, avec un rapport 2(H3PO4)/100(H2O), afin de limiter la gravure latérale. FIG. 4 shows optical microscope images of the surface of a ZnO substrate (plane c) structured by square mesas of a few hundred μηι of side (460 μηι for the left image and 315 μηι for the left image). right image) and a few micrometers high, obtained by wet etching using a solution of H 3 PO 4 strongly diluted in water, with a ratio 2 (H 3 PO 4 ) / 100 (H 2 O), in order to limit lateral etching.
Après l'étape de structuration, la surface du substrat est soumise à une opération de préparation par traitement thermique à une température au moins égale à 600°C (voire à 800°C) et sous un flux d'oxygène FO (figure 3C). Ce traitement thermique peut être précédé par un nettoyage de la surface par l'utilisation d'un plasma à base d'oxygène. Après cette deuxième étape, des marches atomiques sont obtenues à la surface des motifs.  After the structuring step, the surface of the substrate is subjected to a preparation operation by heat treatment at a temperature at least equal to 600 ° C. (or even 800 ° C.) and under an oxygen flow FO (FIG. 3C). . This heat treatment can be preceded by a cleaning of the surface by the use of an oxygen-based plasma. After this second step, atomic steps are obtained on the surface of the patterns.
Les figures 5A et 5B sont des images obtenues au microscope à force atomique de la surface d'un substrat de ZnO (plan c) avant (5A) et après (5B) un traitement thermique par recuit à une température de 1000°C pendant 2 minutes sous un flux d'oxygène. Avant le traitement, la surface n'est pas lisse à l'échelle atomique, est rayée et conserve des résidus de polissage (particules de silice, dont une a été mise en évidence en l'entourant par un cercle). Après le traitement, ces rayures et contaminations ont disparu et on peut observer clairement des marches atomiques.  FIGS. 5A and 5B are images obtained by atomic force microscopy of the surface of a ZnO substrate (plane c) before (5A) and after (5B) a heat treatment by annealing at a temperature of 1000 ° C. for 2 minutes under a flow of oxygen. Before the treatment, the surface is not smooth at the atomic scale, is scratched and retains polishing residues (silica particles, one of which has been highlighted by surrounding it with a circle). After the treatment, these scratches and contaminations disappear and we can clearly observe atomic steps.
Ensuite, il est possible de protéger les surfaces du substrat sur lesquelles aucune croissance n'est envisagée par un dépôt d'une couche mince CP (figure 3D). Ces surfaces comprennent la face arrière et les faces latérales du substrat ZnO. Cette couche mince peut être un oxyde (par exemple SiO2) ou un nitrure réfractaire (par exemple Si3N4). Ce dépôt est effectué, par exemple par pulvérisation cathodique, avant la croissance des couches actives. Il permet l'utilisation de techniques de croissance épitaxiale telles que l'épitaxie en phase vapeur aux organométalliques (EPVOM, également connue sous l'acronyme anglais MOCVD, pour « Metalorganic Chemical Vapor Déposition ») et l'épitaxie en phase vapeur aux hydrures (EPVH). En effet, l'EPVOM est la technique actuellement utilisée à l'échelle industrielle pour la réalisation des dispositifs à base de GaN. L'EPVH est également utilisée pour la fabrication de (pseudo-)substrats de GaN en raison des très fortes vitesses de croissance (de l'ordre de 100 μιτι/η). La figure 3E illustre, de manière très schématique, la structure obtenue après dépôt épitaxial, directement sur la surface structurée du substrat, d'une ou plusieurs couches actives CA. Plus précisément, ces couches sont déposées directement - sans interposition d'une couche tampon d'un matériau différent - sur les surfaces supérieures planes des mesas (contrairement au document FR3031834 où il faut nécessairement insérer une couche tampon d'AIN avant l'épitaxie des couches actives CA) ; elles présentent donc la même orientation cristalline que le substrat en ZnO. Ces couches, discontinues, présentent des bords libres, en correspondance des bords des mesas M du substrat, ce qui permet la relaxation des contraintes. On remarque que les couches actives sont également déposées dans les sillons qui séparent les mesas ; ces portions des couches actives ne sont cependant pas utilisées. Then, it is possible to protect the surfaces of the substrate on which no growth is envisaged by a deposition of a thin layer CP (FIG. 3D). These surfaces comprise the rear face and the lateral faces of the ZnO substrate. This thin layer may be an oxide (for example SiO 2 ) or a refractory nitride (for example Si 3 N 4 ). This deposition is carried out, for example by sputtering, before the growth of the active layers. It allows the use of epitaxial growth techniques such as organometallic vapor phase epitaxy (EPVOM, also known by the acronym MOCVD, for "Metalorganic Chemical Vapor Deposition") and hydride vapor phase epitaxy ( EPVH). Indeed, EPVOM is the technique currently used on an industrial scale for the realization of GaN-based devices. EPVH is also used for the fabrication of (pseudo-) GaN substrates because of the very high growth rates (of the order of 100 μιτι / η). FIG. 3E illustrates, very schematically, the structure obtained after epitaxial deposition, directly on the structured surface of the substrate, of one or more active layers CA. More precisely, these layers are deposited directly - without the interposition of a buffer layer of a different material - on the flat upper surfaces of the mesas (unlike the document FR3031834 where it is necessary to insert a buffer layer of AlN before the epitaxy of active layers CA); they therefore have the same crystalline orientation as the ZnO substrate. These discontinuous layers have free edges, in correspondence of the edges of the mesas M of the substrate, which allows the relaxation of the stresses. Note that the active layers are also deposited in the grooves separating the mesas; these portions of the active layers are however not used.
Comme cela a été évoqué plus haut, le dépôt des couches actives peut s'effectuer par des techniques telles que l'EPVOM ou l'EPVH. Selon un mode de réalisation préféré de l'invention, cependant, on utilise plutôt l'épitaxie par jets moléculaires (EJM, ou MBE de l'anglais « Molecular Beam Epitaxy »). Cette technique de croissance est avantageuse car elle permet la croissance des matériaux nitrures à des températures très inférieures (de 300 à 400°C de moins) à celles utilisées par l'EPVOM, ce qui réduit les risques de décomposition thermique du ZnO. En outre, elle permet l'utilisation de N2 au lieu de l'ammoniac (NH3) comme source d'azote en utilisant une cellule plasma RF, ce qui n'est pas possible avec l'utilisation de l'EPVOM comme technique de croissance. Or, le ZnO est très réactif vis-à-vis de l'ammoniac. Par ailleurs, cette technique de croissance permet aussi la croissance de structures ZnO/(Zn,Mg)O présentant les dopages résiduels les plus faibles. As mentioned above, the deposition of the active layers can be carried out by techniques such as EPVOM or EPVH. According to a preferred embodiment of the invention, however, it is rather used molecular beam epitaxy (MBE, or MBE of the English "Molecular Beam Epitaxy"). This growth technique is advantageous because it allows the growth of nitride materials at much lower temperatures (300 to 400 ° C lower) than those used by EPVOM, which reduces the risk of thermal decomposition of ZnO. In addition, it allows the use of N 2 instead of ammonia (NH 3 ) as a nitrogen source using an RF plasma cell, which is not possible with the use of EPVOM as a technique. growth. However, ZnO is very reactive with respect to ammonia. Moreover, this growth technique also allows the growth of ZnO / (Zn, Mg) O structures with the lowest residual dopings.
Le principe de l'invention a été validé en réalisant la croissance par EJM de couches actives en GaN sur des substrats de ZnO structurés. Les figures 6A et 6B montrent des images de microscopie optique des structures obtenues pour deux orientations cristallographiques différentes : plan c (0001 ) - 6A - et plan m (1 -100) - 6B. L'épaisseur de la couche active est de 0,7 μηι et 0,6 μηι, respectivement. Dans les deux cas, l'absence de fissures est confirmée, bien que l'épaisseur déposée soit très supérieure à l'épaisseur critique de fissuration (cf. la figure 2B). Ces résultats démontrent clairement le principe de l'invention et son adaptabilité pour faire croître des matériaux à structure de type wurtzite contraints selon les différentes orientations cristallographiques, permettant son extension aux hétérostructures non et semi-polaires de grandes épaisseurs. The principle of the invention has been validated by performing the growth by EJM of GaN active layers on structured ZnO substrates. FIGS. 6A and 6B show optical microscopy images of the structures obtained for two different crystallographic orientations: plane c (0001) - 6A - and plane m (1 -100) - 6B. The thickness of the active layer is 0.7 μηι and 0.6 μηι, respectively. In both cases, the absence of cracks is confirmed, although the deposited thickness is much greater than the critical cracking thickness (see Figure 2B). These results clearly demonstrate the principle of the invention and its adaptability to grow wurtzite-type structure materials constrained according to the different crystallographic orientations, allowing its extension to large and non-semi-polar heterostructures.
Des LEDs présentant une géométrie carrée avec des mesas de taille variant entre 140 et 460 μηι ont également été fabriquées à partir d'hétérostructures (In, Ga)N/GaN réalisées conformément à l'invention. Chaque LED correspond à une mesa du substrat structuré. La figure 7A montre un spectre d'électroluminescence obtenu à température ambiante pour une telle LED polaire avec des couches actives - d'orientation (0001 ) ou (000-1 ) - à base de GaN - plus précisément, il s'agit d'une LED à puits quantiques (In, Ga)N/GaN - de 400 μηι de côté et un courant d'injection de 20 mA. Le spectre de la figure 7A est dominé par un pic émettant dans le bleu autour de 455 nm. Cette émission bleue a pour origine la recombinaison des porteurs dans les puits quantiques (ln,Ga)N/GaN, confirmant que la fabrication de structures monolithiques de LEDs à base de GaN sur substrats structurés de ZnO a été réalisée avec succès.  LEDs having a square geometry with mesas of size ranging between 140 and 460 μηι were also manufactured from heterostructures (In, Ga) N / GaN made according to the invention. Each LED corresponds to a mesa of the structured substrate. FIG. 7A shows an electroluminescence spectrum obtained at ambient temperature for such a polar LED with active layers - oriented (0001) or (000-1) - based on GaN - more precisely, it is a question of a quantum well LED (In, Ga) N / GaN - 400 μηι side and an injection current of 20 mA. The spectrum of Figure 7A is dominated by a peak emitting in the blue around 455 nm. This blue emission originates from the recombination of the carriers in the quantum wells (In, Ga) N / GaN, confirming that the fabrication of monolithic structures of GaN-based LEDs on structured ZnO substrates has been successfully carried out.
Les performances de ces LEDs ont été comparées à celle de dispositifs identiques, mais réalisés sur un substrat ZnO non structuré. La figure 7B est un graphique de la puissance optique de sortie des LEDs en fonction du courant d'injection ; la courbe grise correspond aux dispositifs selon l'invention, la courbe noire à ceux réalisés sur substrat non structuré. The performance of these LEDs has been compared to that of identical devices, but performed on an unstructured ZnO substrate. Fig. 7B is a graph of LED output optical power as a function of injection current; the gray curve corresponds to the devices according to the invention, the black curve to those made on unstructured substrate.
On peut observer que l'invention permet d'obtenir une forte amélioration de la puissance optique, d'au moins un facteur 2 à 20 mA (de 40 à 80 μ\Λ ) et 80 mA (de 105 à 220 μ\Ν). It can be observed that the invention makes it possible to obtain a strong improvement in the optical power, by at least a factor of 2 at 20 mA (from 40 to 80 μ \ Λ) and 80 mA (from 105 to 220 μ \ Ν) .
Les applications de l'invention concernent principalement la fabrication de composants micro- et optoélectronique, et plus particulièrement des LEDs, lasers, transistors à haute mobilité électronique ou de puissance, photodétecteurs à puits quantiques dans l'infrarouge proche et lointain (appelés QWIP en anglais), mais aussi de composants à cascades quantiques (lasers et détecteurs) qui requièrent de très grandes épaisseurs de couches actives. The applications of the invention mainly concern the manufacture of micro- and optoelectronic components, and more particularly LEDs, lasers, high electron mobility or power transistors, quantum well photodetectors in the near and far infrared. (called QWIP), but also quantum cascading components (lasers and detectors) that require very large active layer thicknesses.
Par ailleurs, l'invention permet de mettre à profit la très forte sélectivité de gravure du ZnO par rapport aux couches actives pour permettre la réalisation de microstructures (membranes, micro-disques...) adaptées à la fabrication de microcomposants pour l'électronique et la photonique. Par exemple, il est possible de fabriquer une structure suspendue formée par une couche de GaN préalablement épitaxiée sur un substrat de ZnO, puis sous- gravée chimiquement par une solution acide (par exemple H3PO4) fortement diluée dans de l'eau. Aussi, est-il possible de réaliser des cristaux photoniques ou des guides métal/métal par un retrait sélectif du substrat suivi d'un report sur un autre substrat. Furthermore, the invention makes it possible to take advantage of the very high etching selectivity of ZnO with respect to the active layers to enable the production of microstructures (membranes, micro-disks, etc.) suitable for the manufacture of microcomponents for electronics. and photonics. For example, it is possible to manufacture a suspended structure formed by a GaN layer previously epitaxially grown on a ZnO substrate, and then chemically etched with an acidic solution (for example H 3 PO 4 ) strongly diluted in water. Also, is it possible to make photonic crystals or metal / metal guides by selectively removing the substrate followed by a transfer to another substrate.

Claims

REVENDICATIONS
1 . Procédé de fabrication d'une hétérostructure en matériaux semi-conducteurs présentant une structure cristalline de type wurtzite, comprenant les étapes suivantes : 1. A method of manufacturing a heterostructure of semiconductor materials having a wurtzite crystal structure, comprising the steps of:
structuration d'une surface (SD) d'un substrat (S) monocristallin d'oxyde de zinc en mesas (M) présentant une surface plane, les mesas présentant une surface supérieure plane parallèle à la surface du substrat; et  structuring of a surface (SD) of a single crystal (S) zinc mononium substrate (S) having a planar surface, the mesas having a planar upper surface parallel to the surface of the substrate; and
- dépôt par épitaxie d'au moins une couche (CA) en matériau semi-conducteur présentant une structure cristalline de type wurtzite, formant ladite hétérostructure, directement sur la surface supérieure des mesas de la surface structurée.  epitaxial deposition of at least one layer (CA) of semiconductor material having a wurtzite crystal structure, forming said heterostructure, directly on the upper surface of the mesas of the structured surface.
2. Procédé selon la revendication 1 dans lequel lesdites mesas présentent une plus petite dimension latérale comprise entre 10 et 1000 μηι et une hauteur supérieure ou égale à 100 nm. 2. Method according to claim 1 wherein said mesas have a smaller lateral dimension of between 10 and 1000 μηι and a height greater than or equal to 100 nm.
3. Procédé selon l'une des revendications précédentes dans lequel ladite étape de structuration est mise en œuvre par gravure chimique. 3. Method according to one of the preceding claims wherein said structuring step is implemented by chemical etching.
4. Procédé selon l'une des revendications précédentes comprenant également une étape de traitement thermique de la surface structurée dudit substrat par recuit sous flux d'oxygène (FO) à une température supérieure ou égale à 600°C, mise en œuvre avant ladite étape de dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite. 4. Method according to one of the preceding claims also comprising a step of heat treatment of the structured surface of said substrate by annealing under an oxygen stream (FO) at a temperature greater than or equal to 600 ° C, implemented before said step epitaxially depositing at least one layer of semiconductor material having a wurtzite crystal structure.
5. Procédé selon l'une des revendications précédentes dans lequel ladite étape de dépôt par épitaxie d'au moins une couche (CA) en matériau semi-conducteur présentant une structure cristalline de type wurtzite est mise en œuvre par épitaxie par jets moléculaires. 5. Method according to one of the preceding claims wherein said epitaxial deposition step of at least one layer (CA) of semiconductor material having a crystal structure wurtzite type is implemented by molecular beam epitaxy.
6. Procédé selon l'une des revendications précédentes comprenant également une étape de dépôt d'une couche mince de protection (CP) sur au moins une surface dudit substrat autre que la surface structurée, mise en œuvre avant ladite étape de dépôt par épitaxie d'au moins une couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite. 6. Method according to one of the preceding claims also comprising a step of depositing a thin protective layer (CP) on at least one surface of said substrate other than the structured surface, implemented before said epitaxial deposition step d at least one layer of semiconductor material having a wurtzite crystal structure.
7. Procédé selon l'une des revendications précédentes dans lequel la surface structurée présente une orientation non-polaire ou semi- polaire. 7. Method according to one of the preceding claims wherein the structured surface has a non-polar or semi-polar orientation.
8. Procédé selon l'une des revendications précédentes dans lequel ladite ou chaque dite couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite comprend au moins un matériau choisi parmi un nitrure binaire, un oxyde binaire, un alliage Zn(Mg, Cd)0 et un alliage AI(Ga, ln)N. 8. Method according to one of the preceding claims wherein said or each said layer of semiconductor material having a wurtzite crystal structure comprises at least one material selected from a binary nitride, a binary oxide, a Zn alloy (Mg, Cd) 0 and an Al (Ga, ln) N alloy.
9. Procédé de fabrication d'au moins un dispositif électronique ou optoélectronique comprenant : A method of manufacturing at least one electronic or optoelectronic device comprising:
la fabrication d'une hétérostructure en au moins un matériau semi-conducteur présentant une structure cristalline de type wurtzite par un procédé selon l'une des revendications précédentes ;  the manufacture of a heterostructure in at least one semiconductor material having a wurtzite crystal structure by a method according to one of the preceding claims;
la fabrication dudit dispositif électronique ou optoélectronique à partir d'une région de ladite hétérostructure correspondant à une mesa de la surface structurée du substrat.  manufacturing said electronic or optoelectronic device from a region of said heterostructure corresponding to a mesa of the structured surface of the substrate.
10. Hétérostructure comprenant au moins une couche (CA) en matériau semi-conducteur présentant une structure cristalline de type wurtzite, déposée directement au-dessus d'une surface (SD) d'un substrat (S) monocristallin en oxyde de zinc, caractérisée en ce que ladite surface est structurée en mesas (M) et présente une surface plane, les mesas présentant une surface supérieure plane parallèle à la surface du substrat. A heterostructure comprising at least one layer (CA) of semiconductor material having a wurtzite crystal structure, deposited directly above a surface (SD) of a zinc oxide monocrystalline substrate (S), characterized in that said surface is structured in mesas (M) and has a flat surface, the mesas having a flat upper surface parallel to the surface of the substrate.
1 1 . Hétérostructure selon la revendication 10 dans laquelle lesdites mesas présentent une plus petite dimension latérale comprise entre1 1. A heterostructure according to claim 10 wherein said mesas have a smaller lateral dimension between
10 et 1000 μηι et une hauteur supérieure ou égale à 100 nm. 10 and 1000 μηι and a height greater than or equal to 100 nm.
12. Hétérostructure selon l'une des revendications 10 ou 1 1 dans lequel la surface structurée dudit substrat présente une orientation non- polaire ou semi-polaire. The heterostructure according to one of claims 10 or 11 wherein the structured surface of said substrate has a non-polar or semi-polar orientation.
13. Hétérostructure selon l'une des revendications 10 à 12 dans lequel ladite ou chaque dite couche en matériau semi-conducteur présentant une structure cristalline de type wurtzite comprend au moins un matériau choisi parmi un nitrure binaire, un oxyde binaire, un alliage Zn(Mg, Cd)0 et un alliage AI(Ga, ln)N. 13. Heterostructure according to one of claims 10 to 12 wherein said or each said layer of semiconductor material having a wurtzite crystal structure comprises at least one material selected from a binary nitride, a binary oxide, a Zn alloy ( Mg, Cd) 0 and an Al (Ga, ln) N alloy.
EP17797365.8A 2016-11-18 2017-11-15 Semiconductor heterostructures with wurtzite-type structure on zno substrate Pending EP3542392A1 (en)

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