FR3094513B1 - Procédé d'authentification d'un processeur - Google Patents

Procédé d'authentification d'un processeur Download PDF

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Publication number
FR3094513B1
FR3094513B1 FR1903346A FR1903346A FR3094513B1 FR 3094513 B1 FR3094513 B1 FR 3094513B1 FR 1903346 A FR1903346 A FR 1903346A FR 1903346 A FR1903346 A FR 1903346A FR 3094513 B1 FR3094513 B1 FR 3094513B1
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France
Prior art keywords
arithmetic
logic unit
processor
result
opcode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1903346A
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English (en)
Other versions
FR3094513A1 (fr
Inventor
Michael Peeters
Fabrice Marinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Proton World International NV
Original Assignee
Proton World International NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Proton World International NV filed Critical Proton World International NV
Priority to FR1903346A priority Critical patent/FR3094513B1/fr
Priority to US16/833,012 priority patent/US11379238B2/en
Publication of FR3094513A1 publication Critical patent/FR3094513A1/fr
Priority to US17/721,193 priority patent/US11853765B2/en
Application granted granted Critical
Publication of FR3094513B1 publication Critical patent/FR3094513B1/fr
Priority to US18/532,946 priority patent/US20240103873A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G06F21/12—Protecting executable software
    • G06F21/121—Restricting unauthorised execution of programs
    • G06F21/125—Restricting unauthorised execution of programs by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2129—Authenticate client device independently of the user
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure

Abstract

Procédé d'authentification d'un processeur La présente description concerne un procédé (200) d'authentification d'un processeur (2000), comportant une unité arithmétique et logique (2060), comprenant les étapes suivantes : la réception, sur une première borne de l'unité arithmétique et logique (2060), d'au moins un opérande (OP1, ..., OPN) décodé d'un code opératoire à exécuter (OPCODE) ; et la réception, sur une deuxième borne de l'unité arithmétique et logique (2060), d'une première instruction (ISNTR-SIG) combinant une deuxième instruction (INSTR) du code opératoire à exécuter (OPCODE) et au moins un résultat (R) précédent de ladite unité arithmétique et logique (2060), ledit au moins un résultat (R) précédent étant stocké dans une banque de registres de résultats (2040). Figure pour l'abrégé : Fig. 3
FR1903346A 2019-03-29 2019-03-29 Procédé d'authentification d'un processeur Active FR3094513B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1903346A FR3094513B1 (fr) 2019-03-29 2019-03-29 Procédé d'authentification d'un processeur
US16/833,012 US11379238B2 (en) 2019-03-29 2020-03-27 Processor authentication method through signed instruction
US17/721,193 US11853765B2 (en) 2019-03-29 2022-04-14 Processor authentication method
US18/532,946 US20240103873A1 (en) 2019-03-29 2023-12-07 Processor authentication method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1903346A FR3094513B1 (fr) 2019-03-29 2019-03-29 Procédé d'authentification d'un processeur
FR1903346 2019-03-29

Publications (2)

Publication Number Publication Date
FR3094513A1 FR3094513A1 (fr) 2020-10-02
FR3094513B1 true FR3094513B1 (fr) 2023-07-14

Family

ID=67660260

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1903346A Active FR3094513B1 (fr) 2019-03-29 2019-03-29 Procédé d'authentification d'un processeur

Country Status (2)

Country Link
US (3) US11379238B2 (fr)
FR (1) FR3094513B1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2957438B1 (fr) 2010-03-09 2012-03-30 Proton World Int Nv Detection d'un deroutement d'un canal de communication d'un dispositif de telecommunication couple a un circuit nfc
FR2969341B1 (fr) 2010-12-20 2013-01-18 Proton World Int Nv Gestion de canaux de communication dans un dispositif de telecommunication couple a un circuit nfc

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6594752B1 (en) 1995-04-17 2003-07-15 Ricoh Company, Ltd. Meta-address architecture for parallel, dynamically reconfigurable computing
JPH1063500A (ja) * 1996-08-23 1998-03-06 Matsushita Electric Ind Co Ltd 信号処理装置
US5974529A (en) * 1998-05-12 1999-10-26 Mcdonnell Douglas Corp. Systems and methods for control flow error detection in reduced instruction set computer processors
US6574728B1 (en) * 1999-08-10 2003-06-03 Cirrus Logic, Inc. Condition code stack architecture systems and methods
US6308256B1 (en) 1999-08-18 2001-10-23 Sun Microsystems, Inc. Secure execution of program instructions provided by network interactions with processor
US7941651B1 (en) * 2002-06-27 2011-05-10 Intel Corporation Method and apparatus for combining micro-operations to process immediate data
GB0215028D0 (en) 2002-06-28 2002-08-07 Critical Blue Ltd Microarchitecture description
US7035891B2 (en) * 2002-08-27 2006-04-25 Intel Corporation Reduced-hardware soft error detection
US20060095975A1 (en) * 2004-09-03 2006-05-04 Takayoshi Yamada Semiconductor device
US7581079B2 (en) 2005-03-28 2009-08-25 Gerald George Pechanek Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
US9177111B1 (en) 2006-11-14 2015-11-03 Hitachi Global Storage Technologies Netherlands B.V. Systems and methods for protecting software
US8402448B2 (en) * 2008-09-18 2013-03-19 Infineon Technologies Ag Compiler system and a method of compiling a source code into an encrypted machine language code
US8452934B2 (en) * 2008-12-16 2013-05-28 Sandisk Technologies Inc. Controlled data access to non-volatile memory
US20110167496A1 (en) 2009-07-07 2011-07-07 Kuity Corp. Enhanced hardware command filter matrix integrated circuit
DE102011005209B4 (de) * 2011-03-07 2016-06-23 Infineon Technologies Ag Programmanweisungsgesteuerte Instruktionsflusskontrolle
US8892851B2 (en) * 2011-11-02 2014-11-18 International Business Machines Corporation Changing opcode of subsequent instruction when same destination address is not used as source address by intervening instructions
US9652246B1 (en) * 2012-12-20 2017-05-16 Marvell International Ltd. Banked physical register data flow architecture in out-of-order processors
US11468168B1 (en) * 2017-04-11 2022-10-11 Apple Inc. Systems and methods for optimizing authentication branch instructions
FR3076923A1 (fr) * 2018-01-16 2019-07-19 Stmicroelectronics (Rousset) Sas Procede et circuit d'authentification
US11269986B2 (en) * 2018-10-26 2022-03-08 STMicroelectronics (Grand Ouest) SAS Method for authenticating a program and corresponding integrated circuit

Also Published As

Publication number Publication date
US20240103873A1 (en) 2024-03-28
FR3094513A1 (fr) 2020-10-02
US20220244961A1 (en) 2022-08-04
US11853765B2 (en) 2023-12-26
US20200310805A1 (en) 2020-10-01
US11379238B2 (en) 2022-07-05

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