FR3091937B1 - Instruction de double chargement - Google Patents

Instruction de double chargement Download PDF

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Publication number
FR3091937B1
FR3091937B1 FR1906116A FR1906116A FR3091937B1 FR 3091937 B1 FR3091937 B1 FR 3091937B1 FR 1906116 A FR1906116 A FR 1906116A FR 1906116 A FR1906116 A FR 1906116A FR 3091937 B1 FR3091937 B1 FR 3091937B1
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France
Prior art keywords
instruction
execution unit
variable pitch
register
load instruction
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Active
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FR1906116A
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English (en)
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FR3091937A1 (fr
Inventor
Alan Graham Alexander
Simon Christian Knowles
Mrudula Gore
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Graphcore Ltd
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Graphcore Ltd
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
    • G06F9/3455—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results using stride
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Biophysics (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Neurology (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

INSTRUCTION DE DOUBLE CHARGEMENT Processeur comprenant une unité d’exécution, de la mémoire et un ou plusieurs bancs de registres. L’unité d’exécution est agencée pour exécuter des instances d’instructions de code machine provenant d’un jeu d’instructions. Les types d’instructions définis dans le jeu d’instructions comprennent une instruction de double chargement pour charger à partir de la mémoire dans au moins l’un desdits un ou plusieurs bancs de registres. L’unité d’exécution est agencée de manière à, lorsque l’instruction de chargement est exécutée, réaliser une première opération de chargement à progression à pas fixe, et une deuxième opération de chargement à progression à pas variable, le pas variable étant spécifié dans un registre de pas variable dans l’un desdits au moins un banc de registres. Figure pour l'abrégé : Fig. 5
FR1906116A 2019-01-22 2019-06-07 Instruction de double chargement Active FR3091937B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1900848.1A GB2580664B (en) 2019-01-22 2019-01-22 Double load instruction
GB1900848.1 2019-01-22

Publications (2)

Publication Number Publication Date
FR3091937A1 FR3091937A1 (fr) 2020-07-24
FR3091937B1 true FR3091937B1 (fr) 2021-12-24

Family

ID=65656024

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1906116A Active FR3091937B1 (fr) 2019-01-22 2019-06-07 Instruction de double chargement

Country Status (7)

Country Link
US (1) US11061679B2 (fr)
JP (1) JP6843187B2 (fr)
CN (1) CN111459548B (fr)
CA (1) CA3040894C (fr)
DE (1) DE102019112186A1 (fr)
FR (1) FR3091937B1 (fr)
GB (1) GB2580664B (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB202112803D0 (en) 2021-09-08 2021-10-20 Graphcore Ltd Processing device using variable stride pattern

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002517038A (ja) 1998-05-27 2002-06-11 エイアールエム リミテッド 再循環レジスタファイル
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7275148B2 (en) * 2003-09-08 2007-09-25 Freescale Semiconductor, Inc. Data processing system using multiple addressing modes for SIMD operations and method thereof
US7487296B1 (en) * 2004-02-19 2009-02-03 Sun Microsystems, Inc. Multi-stride prefetcher with a recurring prefetch table
US8145877B2 (en) * 2008-03-31 2012-03-27 Xilinx, Inc. Address generation for quadratic permutation polynomial interleaving
US8458685B2 (en) * 2009-06-12 2013-06-04 Cray Inc. Vector atomic memory operation vector update system and method
US8850166B2 (en) 2010-02-18 2014-09-30 International Business Machines Corporation Load pair disjoint facility and instruction therefore
WO2013048369A1 (fr) * 2011-09-26 2013-04-04 Intel Corporation Instruction et logique pour fournir à une opération de charge/opération de stockage de vecteur une fonctionnalité de poussée
US10049061B2 (en) * 2012-11-12 2018-08-14 International Business Machines Corporation Active memory device gather, scatter, and filter
US9619229B2 (en) * 2012-12-27 2017-04-11 Intel Corporation Collapsing of multiple nested loops, methods and instructions
US9582422B2 (en) * 2014-12-24 2017-02-28 Intel Corporation Hardware prefetcher for indirect access patterns
US20160313995A1 (en) * 2015-04-24 2016-10-27 Optimum Semiconductor Technologies, Inc. Computer processor with indirect only branching
US9875214B2 (en) * 2015-07-31 2018-01-23 Arm Limited Apparatus and method for transferring a plurality of data structures between memory and a plurality of vector registers
US20170192783A1 (en) * 2015-12-30 2017-07-06 Elmoustapha Ould-Ahmed-Vall Systems, Apparatuses, and Methods for Stride Load
US20170192782A1 (en) * 2015-12-30 2017-07-06 Robert Valentine Systems, Apparatuses, and Methods for Aggregate Gather and Stride
US10108538B1 (en) 2017-07-31 2018-10-23 Google Llc Accessing prologue and epilogue data
US20190332924A1 (en) * 2018-04-27 2019-10-31 International Business Machines Corporation Central scheduler and instruction dispatcher for a neural inference processor
US10769070B2 (en) * 2018-09-25 2020-09-08 Arm Limited Multiple stride prefetching
GB2584268B (en) 2018-12-31 2021-06-30 Graphcore Ltd Load-Store Instruction

Also Published As

Publication number Publication date
GB2580664B (en) 2021-01-13
CN111459548A (zh) 2020-07-28
CN111459548B (zh) 2024-03-22
US11061679B2 (en) 2021-07-13
JP2020119490A (ja) 2020-08-06
DE102019112186A1 (de) 2020-07-23
US20200233670A1 (en) 2020-07-23
CA3040894C (fr) 2022-03-22
JP6843187B2 (ja) 2021-03-17
CA3040894A1 (fr) 2020-07-22
FR3091937A1 (fr) 2020-07-24
GB2580664A (en) 2020-07-29
GB201900848D0 (en) 2019-03-13

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