FR3089322B1 - Gestion des restrictions d’accès au sein d’un système sur puce - Google Patents
Gestion des restrictions d’accès au sein d’un système sur puce Download PDFInfo
- Publication number
- FR3089322B1 FR3089322B1 FR1872038A FR1872038A FR3089322B1 FR 3089322 B1 FR3089322 B1 FR 3089322B1 FR 1872038 A FR1872038 A FR 1872038A FR 1872038 A FR1872038 A FR 1872038A FR 3089322 B1 FR3089322 B1 FR 3089322B1
- Authority
- FR
- France
- Prior art keywords
- master
- slave device
- smi
- slave
- equipments
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17356—Indirect interconnection networks
- G06F15/17368—Indirect interconnection networks non hierarchical topologies
- G06F15/17381—Two dimensional, e.g. mesh, torus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/62—Protecting access to data via a platform, e.g. using keys or access control rules
- G06F21/6218—Protecting access to data via a platform, e.g. using keys or access control rules to a system of files or objects, e.g. local or distributed file system or database
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Bioethics (AREA)
- Computer Security & Cryptography (AREA)
- General Health & Medical Sciences (AREA)
- Health & Medical Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Databases & Information Systems (AREA)
- Storage Device Security (AREA)
- Multi Processors (AREA)
- Computer And Data Communications (AREA)
- Small-Scale Networks (AREA)
Abstract
Le système comprend au moins plusieurs équipements maîtres (Mi) possédant chacun une interface de programmation (SMi), plusieurs équipements esclaves (SMi, Si) incluant lesdites interfaces de programmation, un circuit d’interconnexion (1) couplé entre les équipements maîtres et les équipements esclaves. Chaque transaction est affectée d’un attribut (ATTi) capable de prendre au moins deux valeurs d’attribut correspondant à au moins deux états souhaités pour l’équipement maître. Chaque équipement esclave (SMi, Si) est associé à un identifiant (IDSMi, IDSi) capable de prendre au moins deux valeurs correspondant respectivement à au moins deux propriétés souhaitées pour l’équipement esclave. Chaque équipement maître hérite automatiquement de la propriété de son interface de programmation. Des moyens de filtrage (LGS1, LGCD, LGCM, LGS2 et LGS3) sont configurés pour en présence d’une transaction destinée à un équipement esclave, comparer la valeur d’attribut correspondante avec la valeur de l’identifiant de cet équipement esclave et rejeter ou non la transaction en fonction du résultat de la comparaison. Figure pour l’abrégé: Fig. 1
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1872038A FR3089322B1 (fr) | 2018-11-29 | 2018-11-29 | Gestion des restrictions d’accès au sein d’un système sur puce |
US16/684,296 US11386037B2 (en) | 2018-11-29 | 2019-11-14 | Management of access restriction within a system on chip |
CN201922091490.1U CN210983400U (zh) | 2018-11-29 | 2019-11-28 | 片上系统和微控制器 |
CN201911193454.4A CN111241029A (zh) | 2018-11-29 | 2019-11-28 | 片上系统内的访问限制管理 |
DE102019132485.8A DE102019132485A1 (de) | 2018-11-29 | 2019-11-29 | Verwaltung von Zugriffsbeschränkungen innerhalb eines System-on-Chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1872038 | 2018-11-29 | ||
FR1872038A FR3089322B1 (fr) | 2018-11-29 | 2018-11-29 | Gestion des restrictions d’accès au sein d’un système sur puce |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3089322A1 FR3089322A1 (fr) | 2020-06-05 |
FR3089322B1 true FR3089322B1 (fr) | 2020-12-18 |
Family
ID=66166170
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1872038A Active FR3089322B1 (fr) | 2018-11-29 | 2018-11-29 | Gestion des restrictions d’accès au sein d’un système sur puce |
Country Status (4)
Country | Link |
---|---|
US (1) | US11386037B2 (fr) |
CN (2) | CN210983400U (fr) |
DE (1) | DE102019132485A1 (fr) |
FR (1) | FR3089322B1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR3089322B1 (fr) * | 2018-11-29 | 2020-12-18 | St Microelectronics Rousset | Gestion des restrictions d’accès au sein d’un système sur puce |
FR3124284B1 (fr) * | 2021-06-21 | 2024-04-19 | St Microelectronics Srl | Système sur puce comprenant une interface de connexion entre des dispositifs maîtres et des dispositifs esclaves |
FR3142570A1 (fr) * | 2022-11-25 | 2024-05-31 | STMicroelectronics (Alps) SAS | Système sur puce comportant un système d’isolation des ressources et procédé de gestion de l’isolation des ressources correspondant. |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826640B1 (en) * | 2003-06-04 | 2004-11-30 | Digi International Inc. | Bus bandwidth control system |
TWI255405B (en) * | 2005-01-05 | 2006-05-21 | Via Tech Inc | Bus controller and controlling method for use in computer system |
GB2440758B (en) * | 2006-08-08 | 2011-03-30 | Advanced Risc Mach Ltd | Interconnect logic for a data processing apparatus |
US7849247B2 (en) * | 2008-10-14 | 2010-12-07 | Freescale Semiconductor, Inc. | Interrupt controller for accelerated interrupt handling in a data processing system and method thereof |
US8789170B2 (en) * | 2010-09-24 | 2014-07-22 | Intel Corporation | Method for enforcing resource access control in computer systems |
FR3003054B1 (fr) * | 2013-03-06 | 2016-08-19 | Sagem Defense Securite | Procede et dispositif de filtrage de transactions pour systeme sur puce |
WO2015113046A1 (fr) | 2014-01-27 | 2015-07-30 | Rambus Inc. | Mise en oeuvre de contrôle d'accès par système-sur-puce |
US9720868B2 (en) * | 2014-07-07 | 2017-08-01 | Xilinx, Inc. | Bridging inter-bus communications |
US9645963B2 (en) * | 2015-02-16 | 2017-05-09 | Nxp Usa, Inc. | Systems and methods for concurrently testing master and slave devices in a system on a chip |
US10095631B2 (en) * | 2015-12-10 | 2018-10-09 | Arm Limited | System address map for hashing within a chip and between chips |
KR20170077943A (ko) | 2015-12-28 | 2017-07-07 | 삼성전자주식회사 | 접근 제어 유닛을 포함하는 시스템 온 칩 및 시스템 온 칩을 포함하는 모바일 장치 |
CN106933751B (zh) | 2015-12-29 | 2019-12-24 | 澜起科技股份有限公司 | 用于保护动态随机访问存储器的方法和设备 |
GB2548387B (en) * | 2016-03-17 | 2020-04-01 | Advanced Risc Mach Ltd | An apparatus and method for filtering transactions |
US20180121125A1 (en) | 2016-11-01 | 2018-05-03 | Qualcomm Incorporated | Method and apparatus for managing resource access control hardware in a system-on-chip device |
FR3089322B1 (fr) * | 2018-11-29 | 2020-12-18 | St Microelectronics Rousset | Gestion des restrictions d’accès au sein d’un système sur puce |
-
2018
- 2018-11-29 FR FR1872038A patent/FR3089322B1/fr active Active
-
2019
- 2019-11-14 US US16/684,296 patent/US11386037B2/en active Active
- 2019-11-28 CN CN201922091490.1U patent/CN210983400U/zh active Active
- 2019-11-28 CN CN201911193454.4A patent/CN111241029A/zh active Pending
- 2019-11-29 DE DE102019132485.8A patent/DE102019132485A1/de active Pending
Also Published As
Publication number | Publication date |
---|---|
FR3089322A1 (fr) | 2020-06-05 |
CN111241029A (zh) | 2020-06-05 |
US11386037B2 (en) | 2022-07-12 |
DE102019132485A1 (de) | 2020-06-04 |
CN210983400U (zh) | 2020-07-10 |
US20200174964A1 (en) | 2020-06-04 |
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