FR3083362B1 - Procede de programmation d'un dispositif de memoire non volatile et dispositif de memoire non volatile correspondant - Google Patents
Procede de programmation d'un dispositif de memoire non volatile et dispositif de memoire non volatile correspondant Download PDFInfo
- Publication number
- FR3083362B1 FR3083362B1 FR1855927A FR1855927A FR3083362B1 FR 3083362 B1 FR3083362 B1 FR 3083362B1 FR 1855927 A FR1855927 A FR 1855927A FR 1855927 A FR1855927 A FR 1855927A FR 3083362 B1 FR3083362 B1 FR 3083362B1
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- FR
- France
- Prior art keywords
- programming
- memory device
- volatile memory
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- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Abstract
Procédé de programmation d'un groupe de N cellules-mémoire d'un dispositif de mémoire non volatile sur une fenêtre de programmation ayant une durée supérieure à la durée de programmation d'une cellule-mémoire , comprenant une subdivision de ladite fenêtre de programmation en M intervalles temporels, M étant supérieur à deux, une détermination par simulation (S1), en tenant compte d'un critère de référence, d'un profil de programmation (PRP) comportant pour chaque intervalle temporel, un nombre maximum de cellules-mémoires dont la programmation peut être déclenchée au sein de cet intervalle temporel, un stockage (S2) du profil de programmation dans le dispositif de mémoire (1), et une programmation du dispositif de mémoire sur ladite fenêtre de programmation, par intervalle, en utilisant ledit profil de programmation (PRP).
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1855927A FR3083362B1 (fr) | 2018-06-29 | 2018-06-29 | Procede de programmation d'un dispositif de memoire non volatile et dispositif de memoire non volatile correspondant |
| US16/432,369 US10832780B2 (en) | 2018-06-29 | 2019-06-05 | Method for programming a non-volatile memory device and corresponding non-volatile memory device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR1855927 | 2018-06-29 | ||
| FR1855927A FR3083362B1 (fr) | 2018-06-29 | 2018-06-29 | Procede de programmation d'un dispositif de memoire non volatile et dispositif de memoire non volatile correspondant |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3083362A1 FR3083362A1 (fr) | 2020-01-03 |
| FR3083362B1 true FR3083362B1 (fr) | 2021-08-06 |
Family
ID=63963147
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR1855927A Active FR3083362B1 (fr) | 2018-06-29 | 2018-06-29 | Procede de programmation d'un dispositif de memoire non volatile et dispositif de memoire non volatile correspondant |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10832780B2 (fr) |
| FR (1) | FR3083362B1 (fr) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6606267B2 (en) * | 1998-06-23 | 2003-08-12 | Sandisk Corporation | High data rate write process for non-volatile flash memories |
| US8327062B2 (en) * | 2008-12-09 | 2012-12-04 | Infineon Technologies Ag | Memory circuit and method for programming in parallel a number of bits within data blocks |
| FR3080703B1 (fr) * | 2018-04-27 | 2020-04-03 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de programmation d'une memoire resistive |
-
2018
- 2018-06-29 FR FR1855927A patent/FR3083362B1/fr active Active
-
2019
- 2019-06-05 US US16/432,369 patent/US10832780B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20200005872A1 (en) | 2020-01-02 |
| US10832780B2 (en) | 2020-11-10 |
| FR3083362A1 (fr) | 2020-01-03 |
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| PLSC | Publication of the preliminary search report |
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| TP | Transmission of property |
Owner name: STMICROELECTRONICS INTERNATIONAL N.V., CH Effective date: 20230612 |
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