FR3082076A1 - SELF-POWERED SWITCHING DEVICE AND METHOD FOR OPERATING SUCH A DEVICE - Google Patents

Abstract

An integrated circuit (11) for switching a load comprising a housing, power pins (11a, 11b), a power pin (Va), a fault pin (FAULT), a first electronic chip (15) comprising a high voltage transistor in depletion mode, a second electronic chip (16) comprising a low voltage transistor in enrichment mode (6), a circuit for monitoring the proper functioning of the integrated circuit (11) connected to the pin power supply (Va), the monitoring circuit (30) establishing a failure signal reported on the fault pin (FAULT). The invention also relates to a switching device comprising at least one such integrated switching circuit and a control member.

Description

SELF-POWERED SWITCHING DEVICE AND METHOD FOR

OPERATION OF SUCH A DEVICE

FIELD OF THE INVENTION

The present invention relates to a device for switching an electric charge. More specifically, it relates to a switching device comprising a switch and a circuit for controlling this switch. The device may include a self-supply circuit for part of the control circuit. The invention also relates to an integrated switching circuit enabling the device to be implemented when it is combined with a control member.

TECHNOLOGICAL BACKGROUND OF THE INVENTION

It is known from the state of the art of devices for switching a load associating, in a series connection, a high voltage transistor in depletion mode and a low voltage transistor in enrichment mode to form a switch. The transistors are controlled to selectively place the device in a conducting state of conduction or a blocking state according to the value of an external switching signal, applied to a node of the device. The switching device is intended to be integrated into a system in which it is electrically connected to a load consisting of a power circuit and a generator, and makes it possible to transfer energy from the generator to the power circuit during conduction periods. The voltage supplied by the generator is usually of high value, for example 400V, 600V or more.

The two transistors can be mounted in cascode, and in this case the source of the low voltage transistor is electrically connected to the gate of the high voltage transistor. A device control circuit can selectively place this device in a conducting state or a blocking state by means of a control signal applied to the gate of the low voltage transistor.

The two transistors can alternatively be connected in cascade, and in this case the control circuit generates a first and a second control signal applied respectively to the gate of the low voltage transistor and to the gate of the high voltage transistor to selectively place this device in the passing state or the blocking state.

In both cases, the switching device is normally blocking, that is to say that in the absence of power to the device, and in particular in the absence of power to the control circuit, the switching device is in an inactive mode, in the blocking state. This avoids inadvertently closing the device on the load, which could cause serious safety problems.

In addition to its functions for controlling the conduction state, it is desirable that the control circuit ensures the proper functioning of the switching device. In the event of detection of a malfunction or of an event capable of causing such a malfunction, it generates the command signal or signals placing the device in an inactive mode, in which it is made blocking. This is particularly the case when the operating temperature of the device is excessive or when certain voltages deviate from their set voltages.

The switching device can be produced by combining a plurality of integrated and / or discrete circuits on an electrical routing support. These circuits implement the functionalities of the control circuit and the switch (the high and low voltage transistors connected in series). In practice, the chosen architecture of the switching device is dictated by the existence or the availability of integrated circuits implementing the desired functionalities.

Document WO2017203186 thus discloses a relatively simple integrated switching circuit, in the sense that it only integrates the high and low voltage transistors implementing the switching functionality. The functionalities of the control circuit must therefore be achieved using additional components, which can make the design of the switching device complex.

Providing an integrated switching circuit with complementary functions may require supplying it electrically, by applying a voltage which comes from a dedicated supply circuit of the system to a supply pin of the integrated circuit. When the supply voltage must be referenced to a voltage different from the electrical ground of the switching device (as is the case of a high switch of a half-bridge device), the supply circuit puts in uses high voltage components such as diodes, inductors and / or capacitors. These components are configured to take energy from the switched load of the system and to condition this energy to supply the integrated circuit with a relatively low amplitude supply voltage (a few volts with respect to the reference voltage) and stable. Such a supply circuit is complex to produce, which therefore does not simplify the design of the switching device.

OBJECT OF THE INVENTION

The present invention aims to provide an integrated switching circuit making it possible to produce a switching device of simplified architecture. It also aims to provide a switching device implementing the integrated switching circuit.

BRIEF DESCRIPTION OF THE INVENTION

With a view to achieving this aim, the object of the invention provides an integrated circuit for switching a load comprising

- a housing ;

- a first and a second power pin, a power pin, a fault pin and, optionally a mid-point pin;

a first electronic chip placed in the housing comprising a high voltage transistor in depletion mode, the first electronic chip comprising a gate pad, a drain pad electrically connected to the first power pin and a source pad electrically connected to the pin from midpoint;

a second electronic chip placed in the housing comprising a low-voltage transistor in enrichment mode, the second electronic chip comprising at least one drain pad electrically connected to the source pad of the first electronic chip and a source pad electrically connected to the second power pin;

- a circuit for monitoring the proper functioning of the integrated circuit placed in the housing and connected to the power supply pin, the monitoring circuit establishing a fault signal reported on the fault pin.

According to other advantageous and non-limiting characteristics of the invention, taken alone or in any technically feasible combination:

the integrated circuit comprises a switching pin and a drive circuit electrically connected to the switching pin and to the gate of the low voltage transistor;

- the monitoring circuit and the driving circuit are integrated in the second electronic chip;

- The second electronic chip comprises a plurality of connection pads, all arranged on the same face of the second electronic chip;

- The housing comprises an electrically insulating housing support, the first and the second electronic chip being fixed to the housing support;

- the monitoring circuit is integrated into a third electronic chip;

- The second electronic chip comprises a gate pad and the integrated circuit comprises a driving pin electrically connected to the gate pad of the second electronic chip;

- The integrated circuit comprises a deactivation pin electrically connected to a deactivation circuit of a self-supply, the deactivation circuit being disposed in the housing;

the monitoring circuit is electrically connected to the power supply pin to establish a failure signal when the voltage carried by the power supply pin is below a predetermined minimum threshold value;

- The monitoring circuit includes a circuit for measuring a switching current.

The invention also relates to a switching device comprising:

- an electrical routing support and at least two connection terminals;

- a control member arranged on the routing support and having a plurality of pins;

- At least one integrated circuit conforming to what has been explained above and disposed on the routing support, the first and second power pins of the integrated circuit being electrically and respectively connected to the connection terminals;

the fault pin of the integrated circuit being electrically connected to one of the pins of the control member.

BRIEF DESCRIPTION OF THE DRAWINGS

Other characteristics and advantages of the invention will emerge from the detailed description of the invention which will follow with reference to the appended figures in which:

- Figure 1 shows an example of implementation of a switching device according to the invention;

- Figure 2 shows a timing diagram of the voltages developing in a device according to the invention during its operation;

- Figures 3a to 3d schematically represent the state of a device according to the invention at different stages of its operation;

- Figure 4 shows an improved version of a switching device 1 according to the invention;

- Figure 5 shows an example of implementation of a supply voltage regulation circuit;

- Figure 6 shows in a simplified manner the general principles of the preferred embodiments of the invention;

- Figures 7a, 7b and 7c respectively show a first, a second and a third embodiment of the switching device;

- Figure 8 shows another switching device according to the invention;

- Figure 9 shows a portion of a control circuit of a device according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

The term “pin” will be used in the rest of this description to mean any element of an integrated circuit emerging from a housing and making it possible to give electrical access to one of the nodes of the circuit. The node can be a contact pad of an electronic chip implementing the circuit, and the electronic chip is placed in the housing. The pin can thus be formed or comprise a projecting conducting element of the housing or a simple contact surface disposed on one of the faces of the housing.

For the sake of simplification of the description, the same references are used for identical elements or ensuring the same function in the different modes of implementation of the device. An electrical signal produced by an integrated circuit and the pin of an integrated circuit carrying this signal will thus be designated by the same reference.

There is shown schematically in Figure 1 an example of implementation of a switching device 1 according to the invention.

It comprises two switching terminals 2a, 2b to which can be connected, as shown in dotted lines in this figure, a load P and a generator G symbolizing a power circuit to which the switching device 1 is connected. The voltage Vbus of the generator G can be high, for example 400V, 600 V or more, and the current liable to flow in the high intensity power device, for example greater than 1 A.

As is well known per se, the switching device 1 makes it possible to selectively apply the voltage of the generator G to the load P according to the state of a digital switching signal COM which can be applied to a terminal of the device to be supplied to a control circuit 4. It is also conceivable that this switching signal COM is generated by the switching device 1 itself, or more precisely by the control circuit 4 of this device 1.

High and low voltage transistors

The communication device 1 comprises a high voltage transistor 5 in depletion mode.

By “high voltage transistor”, we mean a transistor comprising a drain, a source and a gate, the low amplitude voltage applied to the gate (of the order of a few volts) making it possible to make electrically conducting or blocking the connection between the drain and source. In the blocked state, the voltage developing between the drain and the source can be of high amplitude, for example 400V, 600 V or more, without damaging the transistor.

A transistor in depletion mode has a negative threshold voltage (typically within the scope of the present invention between -8V and -5V). The voltage between the gate and the source must therefore be negative, lower than this threshold voltage, to make this transistor blocking.

The high voltage transistor in depletion mode 5 can be an HEMT transistor, for example based on GaN or SIC. This type of transistor has an avalanche voltage (i.e. the maximum voltage applicable between the drain and the source of the transistor without it being damaged, it may be a breakdown voltage) of high amplitude, chosen to be greater than the generator circuit voltage of the power circuit, for example more than 400V or 600V.

In practice, the high voltage transistor is produced in the form of a first electronic chip comprising on one of its faces a gate, drain and source pad electrically connected, respectively, to the gate, to the drain and to the source of the high voltage transistor 5.

The switching device 1 also includes a low voltage transistor 6 in enrichment mode, comprising a drain, a source and a gate.

A transistor in enrichment mode has a positive threshold voltage. The voltage between the gate and the source must therefore be positive and greater than this threshold voltage, to make this transistor pass.

The avalanche voltage of the low voltage transistor is lower than that of the high voltage transistor. It may for example be of the order of 30 V. The low voltage transistor 6 may be a silicon-based MOSFET transistor. The low voltage transistor 6 is then produced in the form of a second silicon-based electronic chip. The second electronic chip can have a vertical architecture and be provided with source, drain and gate pads respectively connected to the source, to the drain and to the gate of the low-voltage transistor 6. In the case of such a vertical architecture, the source and drain pads are arranged on opposite faces of the second chip. The second chip can alternatively have a lateral architecture and be provided with source and drain pads respectively connected to the source and to the drain of the low voltage transistor 6, and other functional pads, all the pads being arranged on the same face of the microchip. The functional pads are connected to other circuits of the electronic chip implementing other functions than that provided by the low voltage transistor, as will be described in more detail later.

The low voltage transistor 6 and the high voltage transistor 5 are arranged in series between the two switching terminals 2a, 2b. Thus, the drain of the high voltage transistor is connected to one of these two of these terminals, and the source of the low voltage transistor is connected to the other of these terminals. The source of the high voltage transistor 5 is connected to the drain of the low voltage transistor 6 at a middle node M. In the example shown, the first terminal 2a is connected to the load and the second terminal 2b to an electrical ground of the system, but the invention is in no way limited to this particular configuration.

In the example shown the low voltage transistor 6 and the high voltage transistor 5 are mounted in cascode, that is to say that the source of the low voltage transistor, here connected to the ground of the system, is also electrically connected to the high voltage transistor gate 5.

In this configuration, the conducting or blocking state of the device 1 is determined by the voltage applied to the gate of the low-voltage transistor 6. A voltage greater than the threshold voltage Vt of this transistor making it conducting, and a voltage lower than this threshold voltage Vt making it blocking.

When the low voltage transistor 6 and high voltage transistor 5 are included in the same integrated switching circuit, the first and the second electronic chip are arranged in the same housing. The drain pad of the first chip is electrically connected to a first power pin of the integrated circuit. The source pad of the second electronic chip is electrically connected to a second power pin of the integrated circuit. These power pins can respectively form or be connected to the two terminals of the switching device. The source pad of the first chip is electrically connected to the drain pad of the second chip to form the middle node M of the integrated circuit. In the case of a cascode circuit, the source pad of the second chip is also connected to the gate pad of the first chip.

In the case where the second chip has a lateral architecture in which all the pads are arranged on the same face, it is possible to fix the face opposite to that carrying the pads of the first and the second chip on the same housing support, insulating and preferably chosen from a material having a high thermal conductivity. Other electronic chips, implementing other functions can also be attached to this support, and the different studs of the chips connected together and / or to the pins of the case by electrical connections. These electrical connections can be made up or include wired electrical connections, soldered on the pads and / or on the pins of the integrated circuit to connect them together.

Control circuit

Continuing the description of the switching device 1 in FIG. 1, this also includes a control circuit 4. As we have seen, this circuit can receive a switching signal COM produced outside of the device 1. Alternatively , the control circuit 4 can itself develop this switching signal according to the state of the device, that is to say from measurements of

certain tensions or certain currents taken from the device, and who are communicated through the intermediary of electrical connections (not shown on the face 1 of principle). What than either the way the circuit of

command 4 receives or processes a switching signal COM, the control circuit processes this signal to establish and generate a control signal IN which is applied to the gate of the low voltage transistor 6, to effectively place the device 1 in a conducting state or blocker. As such, and as shown in FIG. 9, the control circuit 4 includes a drive circuit 20 which receives the digital switching signal COM as an input. The drive circuit also receives a supply voltage Va and a reference voltage from the switching device (for example an electrical ground) and supplies a control signal IN which switches between these two voltages according to the value of the switching signal COM . The control signal IN is applied to the gate of the low voltage transistor 6.

As will be detailed in another part of this description, the drive circuit can be integrated into an integrated switching circuit, for example in the second chip comprising the low voltage transistor 6 or in another electronic chip of the integrated circuit. In this case, the switching signal COM is supplied on a switching pin of the integrated switching circuit, electrically connected to a switching pad of the second chip or of this other electronic chip, itself electrically connected to the input of the driver 20.

Alternatively, the drive circuit can be placed outside the integrated switching circuit. The control signal IN is then supplied to a control pin IN of the integrated circuit, electrically connected to a gate pad of the second electronic chip.

The control circuit 4 can also include other functions. It can in particular implement functions for monitoring the proper functioning of the switching device so as to block its operation if a failure is detected.

It may thus be a question of monitoring the temperature of the first and / or of the second electronic chip, or of another point of the device, and ensuring that it does not exceed a threshold temperature. It may also be a question of monitoring that the supply or reference voltage of the device (or of a part of the device) does indeed have regular characteristics, that is to say within a specified range of values surrounding a set value. . The control circuit 4 can also condition the voltages and / or currents of the device to make them available and allow their processing. It may thus be desired to develop a signal Is representative of the switching current flowing between the drain of the high voltage transistor and the source of the low voltage transistor. This signal can thus be taken into account to block the operation of the device if the current flowing in this branch exceeds a determined value.

With reference to FIG. 9, the control circuit 4 can be configured so that a fault signal FAULT supplied by a monitoring circuit 30 (of temperature, supply voltage and / or switching current Is for example) indicating a risk for the proper functioning of the device, places the device in a safe position, for example by switching or maintaining the gate control signal IN of the low voltage transistor in an open state.

The monitoring circuit 30 is here formed of a generator of reference voltage (s) BG, for example one (or more) bandgap voltage (s). This reference voltage BG is supplied to a first comparator circuit UVLO connected to the supply voltage Va, and making it possible to determine whether the supply voltage is lower than the reference voltage BG, for example 3V when the supply voltage set point is 5V. The same principle can be used to determine if the supply voltage exceeds a threshold voltage, represented by another voltage supplied by the generator BG.

The monitoring circuit 30 of FIG. 9 also includes a second comparator circuit TSD, generating a variable voltage depending on the temperature of a particular node of the device, for example a junction of one of the transistors 5, 6. By comparison of the voltage supplied by this circuit and a calibrated BG generator voltage, it can be determined whether the monitored temperature exceeds a maximum acceptable temperature.

The monitoring circuit 30 of FIG. 9 also includes a third comparator circuit ISHI, receiving a voltage from the reference voltage generator BG and a voltage representative of the switching current Is. The third comparator circuit makes it possible to signal that the switching current exceeds a maximum current at which the reference voltage is calibrated. The voltage representative of the switching current Is, is produced by an amplifier circuit Am of the control circuit, from a voltage taken from a terminal of a shunt reference resistor Ro of low value placed in the source of the low transistor tension 6.

In the example shown in FIG. 9, the fault signal FAULT corresponds to the OR combination of the signals supplied by the first, the second and the third comparator. But one could of course form this fault signal FAULT from other signals, in addition to or in replacement of those which have been given here as an example.

Self-supply circuit

As we have seen, the control circuit 4 includes active circuits which therefore need to be electrically supplied. To this end, the device 1 can be provided with a self-supply circuit 7. This circuit comprises an input 7a electrically connected to the middle node M defined between the high voltage transistor 5 and the low voltage transistor 6. It also has an output 7b, supplying a supply voltage Va, and electrically connected to the control circuit 4. The electrical supply voltage Va is of low value, in comparison with the voltages which may appear at the switching terminals 2a , 2b or the midpoint M. It is of the order of a few volts, such as 5V for example.

The self-supply circuit 7 comprises a reservoir capacity Cm, one of the electrodes of which is connected to the output 7b and the other to the electrical ground of the system or to another reference voltage of this system. This capacity Cm has the function of storing charges taken from the middle node M in order to establish the supply voltage Va which can be supplied to the control circuit 4, or to a part of it.

The voltage Vm at the middle node M varies during the operation of the device between a reference voltage (which may be the electrical ground of the system), when the device is on, and the avalanche voltage of the low-voltage transistor when the device is blocker. The self-supply circuit 7 comprises a diode 7d connected between the input 7a and the terminal of the tank capacity Cm carrying the supply voltage Va. This avoids discharging the reservoir capacity Cm in one of the high or low voltage transistors 5, 6, and therefore preserving the charges, in the event that the voltage of the midpoint M comes to pass below the available supply voltage across the tank capacity Cm (which is the case when the low voltage transistor 6 is on).

The self-supply circuit 7 also includes a switch 7c arranged in series with the diode, that is to say between the input 7a and the terminal of the tank capacity Cm carrying the supply voltage Va, corresponding to the output 7b. The switch 7c is normally on, that is to say that the switch is closed in the absence of any command and the tank capacity is well connected in this case to the midpoint M of the device 1.

The characteristic “normally on” of the switch 7c is important, because it ensures that when the device 1 is started, that is to say when it is brought into electrical contact with the load at the two terminals of switching 2a, 2b, the supply circuit can take loads at the midpoint M to fill the tank capacity Cm, develop and supply a sufficient supply voltage Va, so that it can activate the control device 4, or part of it. The operation of the device will be explained in more detail later in this presentation.

The switch 7c is made open by means of a deactivation signal DIS produced by the control circuit 4. When the control circuit 4 is energized and in operation, it establishes and generates the deactivation signal DIS of the switch 7c when the control signal IN is generated to place the device 1 in a passing state. This isolates the supply circuit 7 from the high and low voltage transistors 5, 6 during this period of time. More specifically, the reservoir capacity Cm is electrically isolated from the midpoint, in order to prevent it from discharging.

By way of illustration, FIG. 2 shows a timing diagram of the voltages developing in the device 1 during its operation.

Generally, the device 1 is controlled by the control circuit 4 to alternate:

a blocking phase during which the control circuit 4 generates a control signal IN to open the low voltage transistor 6. This signal is at 0V on the timing diagram of FIG. 2. It is lower than the threshold voltage Vt of the low voltage transistor 6 to make it blocking.

- A pass-through (or conduction) phase during which the control circuit 4 generates a control signal IN to close the low-voltage transistor 6. This signal can be a few volts, but in any case, greater than the threshold voltage Vt of the low voltage transistor 6 to turn it on. During this phase also the control circuit generates a deactivation signal DIS so that the switch 7c of the supply circuit 7 is open.

Returning to the description of FIG. 2, the instant t0 is defined as the instant at which the device 1 is physically connected to its load. At this instant t0, the tank capacity Cm is therefore completely discharged, the supply voltage Va is zero. The control circuit 4 is not able to function, that is to say to supply the commands such as the control of the gate of the low voltage transistor IN or the control of the switch DIS. The “cascode” configuration of the low and high voltage transistors 5, 6 however ensures that the device 1 is indeed in a blocking state.

FIG. 3a schematically represents the state of this device at this starting time t0. The control circuit 4 is not supplied, the control signal IN has a zero voltage lower than the threshold voltage Vt of the low voltage transistor in enrichment mode, this transistor is therefore open. The normally-on switch 7c of the supply circuit 7 is closed, the control circuit 4 being unable to supply a deactivation signal DIS. The voltage of the source of the high voltage transistor in depletion mode 6 (corresponding to the control voltage Vgs of this transistor) is also substantially zero at the start time t0, but however greater than the threshold voltage Vt 'of this transistor (this threshold voltage being negative) which is therefore conducting. During the moments which follow the instant t0, charges are therefore taken at the midpoint thanks to a current I flowing in the high voltage transistor 5, the reservoir capacity Cm is charged and a supply voltage Va is gradually established . The voltage across the terminals of the high voltage transistor VDM, the latter being on, is substantially zero (and in any event at least an order of magnitude lower than the voltage of the generator Vbus) if the drain resistance is neglected. source of this transistor.

When this supply voltage Va is sufficient, for example when it reaches a nominal supply voltage of the control circuit 4 which can be, for example, 5V, the control circuit 4 is activated and becomes functional. In other words, the control circuit 4 is then electrically supplied by the supply circuit 7, it is therefore functional and ready to generate the commands making it possible to operate the device 1.

Of course, the threshold voltage Vt ′ of the high voltage transistor was chosen so that it is greater (in absolute value) than a supply voltage Va sufficient for the control device 4 to be functional.

The voltage of the midpoint Vm is equivalent to the supply voltage. This voltage therefore rises gradually with the supply voltage. We designate t0 ', the instant at which the progression of the voltage from the midpoint is such that the control voltage Vgs (corresponding to the opposite of the voltage Vm from the midpoint) goes below the threshold voltage Vt' of the high-voltage transistor . From this instant t0 ′, the high voltage transistor 5 opens, and the voltage applied between its terminals VDM is substantially established at the voltage of the generator Vbus). However, the leakage current passing through this transistor leads to continuing the rise in the voltage of the midpoint until then the avalanche voltage VBR of the low voltage transistor 6. The schematic state of the device 1 from this instant t0 ' is shown in Figure 3b.

In the example shown by way of illustration of the operation of the device 1 in FIGS. 2 and 3b, the control device generates the signal DIS for deactivation of the switch 7c at an instant tl, after the instant at which the point medium has reached the avalanche voltage VBR of the low voltage transistor 6. To avoid charging the reservoir capacity Vm up to the avalanche voltage VBR of the low voltage transistor 6, which could be excessive, provision may be made for the device 4 (or the self-supply circuit itself) generates a command to open the DIS switch when it starts and / or when the supply voltage reaches a predetermined threshold value Vamax and as long as the voltage Va supply is sufficient. Whatever the cause, the switch 7c is open at the instant tl, and the charges of the tank capacity Cm taken to supply the control circuit are not renewed. The supply voltage Va therefore weakens from this instant tl.

At time t2, the control circuit 4 generates a control of the gate of the low voltage transistor IN aimed at making it closed and causing the device 1 to enter a conduction phase. As we have seen, this can be caused by the switching of the external COM switching signal. The control circuit 4 took care to precede this event by deactivation of the switch 7c of the supply circuit 7 at the instant tl to, as we have seen, avoid keeping this circuit connected to the midpoint M during this phase. In general therefore, and if this is not already the case, the control circuit 4 is configured to deactivate the switch 7c of the supply circuit by generating an opening command DIS of this switch, before generate the control signal of the gate of the low voltage transistor IN to make it closed. It can be envisaged that the switch 7c is controlled to be opened simultaneously with the generation of the control signal IN (that is to say having tl = t2).

The control device 4 generates the control signal IN of the gate of the low voltage transistor 6 to place the device 1 in a passing state for a period of time extending up to an instant t3, as shown in the figures 2 and 3c. During this entire period of time, between the instant t2 and t3, the control circuit 4 maintains the deactivation signal DIS of the switch 7c so that it is open. The tank capacity Cm therefore continues to discharge as the consumption of charges supplying the control circuit progresses.

At the instant t3, the control device 4 switches the control IN of the gate of the low-voltage transistor 6 to make it open, and interrupt the conduction phase of the device 1. This instant t3 can be caused by the switching of the signal COM external switching device 1 or established by the control circuit 4 itself, for example at the end of a determined duration of the conduction phase.

Shortly after this instant t3, or even at the same instant, the control device 4 switches the deactivation signal DIS of the switch 7c, at an instant t4 greater than or equal to t3, so as to re-contact the tank capacity Cm with the midpoint M and allow it to be reloaded. Between the instants t3 and t4, if these two instants are different and which are in any case very close to one another, the voltage of the midpoint rises towards the avalanche voltage VBR of the low voltage transistor 6 The high voltage transistor 5 is kept closed and, by neglecting the source drain resistance of the high voltage transistor 5, the voltage applied between its terminals VDM is substantially zero. The state of the device between times t3 and t4 is schematically represented in FIG. 3d.

At time t4, the device finds itself in a state similar to that in which it was at time tO or t0 '. The passing and blocking phases of the device can then follow one another (depending on the state of the switching signal COM) and reproduce the cycle which has just been presented.

In a further illustration of the operation of a device 1 according to the invention, there is shown in FIG. 2 a situation where at an instant t5 the deactivation signal DIS of the switch 7c is generated when the supply voltage Va reaches a predetermined threshold value Vamax, lower than the avalanche voltage VBR of the low-voltage transistor 6. This voltage Vamax is chosen to be greater than the nominal supply voltage of the control circuit 4. In order to avoid charging the capacity reservoir excessively, up to the avalanche voltage VBR of the low-voltage transistor 6, the control circuit is configured to generate the deactivation signal DIS of the switch 7c to open it and stop charging the reservoir capacity Cm , as soon as the supply voltage Va delivered by the supply circuit 7c exceeds this threshold value Vamax.

It is thus observed in FIG. 2, from this instant t5, that the opening of the switch 7c causes the midpoint voltage Vm to rise sharply to the avalanche voltage of the low voltage transistor VBR. It is also noted that at the same time, the gate source voltage Vgs of the high voltage transistor 5 goes under the threshold voltage Vt 'of this transistor, which leads to making it open and applying the voltage of the generator Vbus between its terminals. The electrical consumption of the control circuit 4 continues, which leads to a decrease in the supply voltage Va delivered by the supply circuit.

According to a variant not shown, and as has already been mentioned, it can also be provided that the control circuit 4 itself is configured to detect the passage of the supply voltage Va below a predetermined minimum threshold value Vamin. Under this supply threshold voltage, the correct operation of the control circuit 4 is no longer guaranteed. Also, the control circuit 4 is configured so that this detection causes the emission of a FAULT failure signal and the passage of the device 1 in a safety configuration. It may for example involve switching or maintaining the control signal of the gate of the low voltage transistor 6 in an open state as soon as the supply voltage crosses this minimum threshold Vamin downward. The device 1 is then placed in a blocking and secure state.

FIG. 4 represents an improved version of a switching device 1 according to the invention, and more particularly of the self-supply circuit 7, on which the high voltage 5 and low voltage 6 transistors have been omitted for more visibility.

In addition to the elements already described in relation to the device of FIG. 1, the self-supply circuit 7 of the improved version of the device 1 comprises, in the self-supply circuit, a voltage regulator LDO arranged between the capacity tank Cm and a regulated capacity Cr connected to the output 7b of the circuit and supplying the supply voltage Va to the control circuit. These additional components make it possible to deliver a supply voltage Va much less oscillating than that appearing at the terminals of the tank capacity Cm and which fluctuates according to the loading / unloading cycles linked to the passing blocking phases of the device 1.

It will be noted that the voltage appearing at the terminals of the tank capacity Cm is nevertheless supplied to the control circuit 4, at a high impedance measurement input of this circuit, the measurement of this voltage can be useful, as has been explained above, to generate the deactivation signal of the switch 7c when the measured voltage exceeds a predetermined threshold Vamax or to place the device in a safety configuration if the measured voltage is lower than the minimum threshold voltage Vamin. But this functionality is not imperative. The voltage Va can for example be regulated or reduced to a reference value from the voltage delivered by the capacitor Vm, this voltage possibly reaching the avalanche voltage VBR of the low voltage transistor 6.

As is well known per se, and represented in FIG. 5, the LDO regulation circuit typically comprises a transistor, the gate of which is connected to the output of a comparator of a reference voltage (such as a bandgap voltage ) and a voltage representative of that appearing at the terminals of the regulated capacity Cr. The comparator turns the transistor on or off so as to transfer charges from the tank capacity Cm to the regulated capacity Cr as required so that the voltage Va across the regulated capacity Cr is substantially equal to a setpoint voltage sufficient to supply the control circuit 4 and make it functional. This setpoint voltage is determined by the value of the resistors of a divider bridge whose midpoint voltage is compared to the reference voltage.

Rather than integrating this function of regulating the supply voltage Va in the self-supply circuit 7 as is proposed here, provision can be made to integrate this function in the control circuit 4. We then find a similar configuration. to that shown in Figure 1.

In general, the self-supply circuit 7 therefore makes it possible to accumulate charges in the tank capacity Cm during the phases where the device 1 is blocking. During the phases where the device 1 is on, the supply circuit is isolated from the nodes where a strong current flows. The tank capacity Cm will therefore be chosen so that it accumulates enough charges to supply the control circuit when the self-supply circuit 7 is isolated. Similarly, the switch 7c will be kept closed long enough, during the phases where the device 1 is blocking, to sufficiently charge the tank capacity Cm. In practice, this period during which the switch 7c is closed may be very short (for example of the order of a few hundred nanoseconds for example), so as not to limit the ability of the device 1 to switch from one phase to another at very high frequency.

It will be noted that the self-supply circuit 7 is only exposed to voltages of small magnitude (of the order of the avalanche voltage VBR of the low-voltage transistor 6), referenced to the voltage of the source of the low voltage transistor, so that it can be made up of components which are easy to manufacture or supply, and therefore inexpensive. It is thus possible to envisage integrating it at least in part into the second chip, comprising the low voltage transistor.

Modes of realization

We now present several particularly advantageous embodiments of the switching device 1 which has just been presented functionally.

With reference to FIG. 6, the various elements making up the switching device 1 are arranged on an electrical routing support 10, for example a printed circuit comprising electrical tracks for connecting the elements together. The routing support 10 comprises in particular the switching terminals 2a, 2b to which the load P and the generator G can be attached.

In all the embodiments which will be presented, and according to one aspect of the present invention, the switching device 1 (therefore comprising the control circuit 4, the high voltage 5 and low voltage transistors 6, and where appropriate, the self-supply circuit 7) is implemented by means of a control unit MCU, for example a microcontroller, which controls at least one integrated switching circuit 11. These elements are arranged on, and electrically connected to each other by , the routing support 10.

The control unit MCU has the function of supervising the operation of the integrated switching circuit 11. The function of the integrated switching circuit 11 is to carry out the switching as such and to implement functions for monitoring the proper functioning of the device 1. This function breakdown of device 1 is particularly advantageous in that it implements a relatively simple integrated switching circuit 11, integrating a reduced number of functions, and which can be used in numerous configurations. It can therefore be produced in high volume and at low cost. The controller, when programmable, can be easily configured or reconfigured, to take advantage of the functionalities of the integrated switching circuit 11.

The control unit MCU is electrically connected to a circuit or a power supply terminal A supplying the electrical energy necessary for its operation.

The control unit MCU generates the switching signal COM which it supplies directly or indirectly to the integrated switching circuit 11, in order to selectively block or pass the low voltage transistor of the circuit.

The control unit MCU is also electrically connected to a fault pin FAULT of the integrated switching circuit 11. As we have seen, this pin provides the fault signal FAULT indicating irregular operation of the integrated circuit 11. This irregular operation may correspond, by way of example and as already noted, to a temperature of the integrated switching circuit 11 in excess of a limit temperature or to a supply voltage of the integrated switching circuit 11 outside of a specified range, or less than a given limit. When the fault signal FAULT is activated, and for example received on an interrupt pin of the control unit MCU, the latter is configured to place the integrated switching circuit 11 in the safety position, by switching or holding the switching signal COM so that it makes blocking of the low voltage transistor 6.

As is usual, and optionally, the control unit MCU can also produce an activation signal EN applied to an activation branch EN of the integrated switching circuit 11 to selectively make it active or inactive, for example for limit the consumption of the device when it is not in use.

The integrated switching circuit 11 is formed of a housing, a first power pin 11a and a second power pin 11b. The integrated circuit comprises at least first electronic chip 15 integrating the high voltage transistor and a second electronic chip 16 integrating the low voltage transistor. In the example shown in Figure 6, the two electronic chips 15, 16 are electrically connected together (and with the two power pins 11a, 11b) to form a cascode circuit, as has already been described in detail in an earlier passage in this description.

In addition to the pins already described in the preceding paragraphs, the integrated switching circuit 11 also includes a supply pin Va. Depending on the chosen mode of implementation of the switching device 1, this supply pin Va can be electrically connected to the circuit or to the supply terminal A of the device 1 or to a self-supply circuit (not shown in the figure). 6). In all cases, and whatever the manner in which the integrated switching circuit 11 is supplied, it has a supply pin Va, electrically connected to all the supply pads of the electronic chips of the integrated circuit. This supply voltage can be relative to a mass of the device 1 or another reference voltage.

To allow it to be supplied by an external self-supply circuit, the integrated switching circuit 11 can also include a mid-point pin M making it possible to supply outside the housing the voltage of the middle node between the high-voltage transistor and the low voltage transistor. This mid point pin M makes it possible to connect a self-supply circuit 7 as described above or a countermeasure circuit making it possible to control the voltage developing at this middle node.

Finally, and as already mentioned, the integrated switching circuit 11 includes a fault pin FAULT for supplying the control member with a fault signal. The FAULT fault pin is electrically connected to a monitoring circuit (an example of which has been given with reference to FIG. 9) which can be integrated into the second chip 16 or integrated into another chip 17 arranged in the housing. The fault pin is electrically connected to a fault pad of the second chip 16 or of the other chip 17.

These elements making up a switching device 1 according to the invention can be declined according to several embodiments which will therefore be described below.

First embodiment

FIG. 7a thus represents a first embodiment of the switching device 1. In this first embodiment, the drive circuit 20 of the control device 4 is not integrated into the integrated switching circuit 11 but forms an additional element disposed on the routing support 10. The switching signal COM produced by the control unit MCU is supplied at the input of the drive circuit 20, and the latter produces a control signal IN which is directly supplied to the gate of the low voltage transistor 6 of the second chip 16. For this purpose, the integrated switching circuit 11 and provided with a control pin IN, electrically connected on the one hand to the output of the driving circuit 20, and on the other part to a gate pad of the second chip 16. It is noted that the drive circuit 20 is connected to the power source or terminal A and to the electrical ground of the device 1.

In the representation of FIG. 7a, the monitoring circuit is integrated into a third chip 17. It could however be envisaged that this circuit is integrated into the second chip 16.

The switching device 1 of this embodiment comprises a self-supply circuit 7 disposed on the routing support, and electrically connected to the mid-point pin M and to the supply pin Va of the integrated switching circuit 11 The deactivation signal DIS of the self-supply circuit 7 is produced and supplied by the control unit MCU. This member is optionally connected to the supply voltage Va if it is desired to be able to control the deactivation signal DIS so that the voltage Va does not exceed a maximum supply voltage Vamax. Alternatively, the supply circuit 7 or the integrated switching circuit can comprise the LDO regulation circuit described in relation to the description of FIGS. 4 and 5.

In an alternative to this first embodiment, one could have connected the supply pin Va to the circuit or to the supply terminal A and in this case it would not have been useful to connect the deactivation signal DIS and the supply voltage Go to the control unit.

Second embodiment

Figure 7b shows a second embodiment of a switching device 1 according to the invention. This second embodiment is particularly advantageous in that it limits the number of elements arranged on the routing support, without making the integrated switching circuit 11 excessively complex. It also makes it possible to route between the integrated switching circuit 11 and the control unit MCU for digital signals only, which contributes to simplifying the design of the switching device.

In this embodiment, the second electronic chip 16 integrates the driving circuit 20 and the monitoring circuit. A third chip 17 is therefore not necessary. The second chip 16 advantageously has a lateral architecture, and the first and second chip 15, 16 can therefore be fixed, by their rear faces, on an insulating and thermally conductive housing support.

The integrated switching circuit 11 comprises a switching switching pin COM electrically connected to the control unit MCU and to a switching pad of the first chip 16, connected to the input of the driving circuit 20 integrated in the first chip 16 and directly connected to the gate of the low voltage transistor 6. It is therefore not necessary for the gate to have a gate pad.

In this example also, the second chip 16 generates the deactivation signal DIS of the self-supply circuit 7. The integrated circuit 11 therefore has a deactivation pin DIS, connected to a deactivation terminal providing the deactivation signal produced by a second chip circuit.

One could also envisage, in an alternative implementation of this second embodiment, as in the first embodiment, of developing the deactivation signal DIS by the control unit MCU.

Third embodiment

FIG. 7c represents a third embodiment of a switching device 1 according to the invention. This embodiment corresponds to the second embodiment of FIG. 7b in which most of the elements making up the self-supply circuit 7 have been integrated into the second chip 16 of the integrated switching circuit 11, and in particular the diode 7d and the switch 7c. The tank capacity Cm was left outside of the integrated switching circuit 11, connected between the supply pin Va and the earth of the system or another reference voltage.

Other embodiment

FIG. 8 shows another switching device 1 according to the invention, having a half-bridge architecture, the well-known operation of which is not repeated here. On an electrical routing support 10 there is the control unit MCU connected to its supply circuit or terminal A. We also find in device 1 of FIG. 8 two integrated switching circuits 11, 11 ', respectively forming the low switch and the high switch of a half-bridge, and similar to those described in the previous embodiments. The routing support 10 is provided with three terminals for respectively connecting, in half-bridge:

a generator G with a first power pin 11a 'of the second integrated switching circuit 11';

a resonant load P to a second power pin 11b 'of the second integrated switching circuit 11' and to a first power pin 11a of the first integrated switching circuit 11;

a mass of the system connected to the second power pin 11b of the first switching integrated circuit 11.

The first integrated circuit 11 is connected to the circuit or to the supply terminal A (also supplying the control unit MCU) by means of its supply pin Va. The midpoint pin M of this first integrated switching circuit 11 is not used. The first integrated switching circuit 11 is also connected to the control unit MCU by its switching pin COM_L and its failure branch FAULT_L, as has been explained with reference to the preceding figures.

The second integrated switching circuit 11 'is referenced to the voltage present on its second power pin 11b'. The supply voltage Va must therefore be relative to this reference voltage, and the voltage of the circuit or of the supply terminal A cannot be directly connected to the supply pin Va 'of this integrated circuit. A self-supply circuit 7 is therefore provided, arranged between the mid-point pin M ′ and the reference voltage of the second integrated circuit 11 ′. The voltage Va 'supplied by the self-supply circuit 7 is reported on a supply pin Va'. The other signals, and in particular the switching signal COM_H and the failure signal FAULT_H are reported to the control unit MCU by means of an isolation device I, for example optoelectronics.

We can observe on the switching device 1 of this figure 8 all the advantage of having an integrated switching circuit 11, 11 ′ which can operate indifferently with a supply voltage coming from a circuit or a terminal of power supply, or a self-supply circuit. The availability of a plurality of fault signals FAULT_L, FAULT_H from the plurality of integrated switching circuits 11 allows the control member to properly supervise the operation of the device 1, and in particular to place each of the two integrated circuits of switching 11, 11 'in blocking mode, as soon as one of these circuits 11, 11' signals a fault.

Of course, the invention is not limited to the modes of implementation described and it is possible to add variants without departing from the scope of the invention as defined by the claims.

Thus, although the low voltage transistor 6 and the low voltage transistor 5 are shown connected in cascode configuration, a switching device 1 according to the invention can be implemented in a “cascade” configuration. In this configuration, the gate of the high voltage transistor 5 is not connected to the source of the low voltage transistor 6, and the control circuit 4 then generates a second control signal IN 'to control the gate of the high voltage transistor 5. The two signals IN, IN '' will be checked to allow charges to be accumulated in the self-supply circuit 7 during the phases where the device 1 is blocking, as has been illustrated in the present description.

Claims (11)

1. Integrated circuit (11) for switching a load comprising: - a housing ; - a first and a second power pin (11a, 11b), a power pin (Va), a fault pin (FAULT) and, optionally, a mid-point pin (M); - a first electronic chip (15) disposed in the housing comprising a high voltage transistor in depletion mode (5), the first electronic chip (15) comprising a gate pad, a drain pad electrically connected to the first power pin ( lia) and a source pad electrically connected to the midpoint pin (M); a second electronic chip (16) disposed in the housing comprising a low voltage transistor in enrichment mode (6), the second electronic chip (16) comprising at least one drain pad electrically connected to the source pad of the first electronic chip ( 15) and a source pad electrically connected to the second power pin (11b); - a monitoring circuit (30) for the proper functioning of the integrated circuit (11) disposed in the housing and connected to the supply pin (Va), the monitoring circuit (30) establishing a failure signal reported on the pin failure (FAULT). 2. Integrated circuit (11) according to the preceding claim comprising a switching pin (COM) and a drive circuit (20) electrically connected to the switching pin (COM) and to the gate of the low voltage transistor. 3. Integrated circuit (11) according to the preceding claim wherein the monitoring circuit (30) and the driving circuit (20) are integrated in the second electronic chip (16). 4. Integrated circuit (11) according to the preceding claim wherein the second electronic chip (16) comprises a plurality of connection pads, all arranged on the same face of the second electronic chip (16). 5. Integrated circuit (11) according to the preceding claim wherein the housing comprises an electrically insulating housing support, the first and the second electronic chip (15, 16) being fixed to the housing support. 6. Integrated circuit (11) according to claim 1 wherein the monitoring circuit (30) is integrated in a third electronic chip (17). 7. Integrated circuit (11) according to one of claims 1 or 6 in which the second electronic chip (16) comprises a gate pad and the integrated circuit (11) comprises a driving pin (IN) electrically connected to the gate pad of the second electronic chip (16). 8. Integrated circuit (11) according to one of the preceding claims comprising a deactivation pin (DIS) electrically connected to a deactivation circuit of a self-supply, the deactivation circuit being disposed in the housing. 9. Integrated circuit (11) according to one of the preceding claims in which the monitoring circuit (30) is electrically connected to the power supply pin (Va) to establish a fault signal (FAULT) when the voltage carried by the power supply pin (Va) is below a predetermined minimum threshold value (Vamin). 10. Integrated circuit (11) according to one of the preceding claims wherein the monitoring circuit (30) comprises a circuit for measuring a switching current. 11. Switching device (1) comprising: - an electrical routing support (10) and at least two connection terminals (2a, 2b); - a control member (MCU) disposed on the routing support (10) and having a plurality of pins; - at least one integrated switching circuit (11) according to one of the preceding claims disposed on the routing support (10), the first and second power pins of the integrated circuit (11a, 11b) being electrically and respectively connected at the connection terminals (2a, 2b); - the fault pin (FAULT) of the integrated circuit (11) being electrically connected to one of the pins of the control unit (MCU).