FR3081155B1 - Procede de fabrication d'un composant electronique a multiples ilots quantiques - Google Patents

Procede de fabrication d'un composant electronique a multiples ilots quantiques Download PDF

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Publication number
FR3081155B1
FR3081155B1 FR1854109A FR1854109A FR3081155B1 FR 3081155 B1 FR3081155 B1 FR 3081155B1 FR 1854109 A FR1854109 A FR 1854109A FR 1854109 A FR1854109 A FR 1854109A FR 3081155 B1 FR3081155 B1 FR 3081155B1
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FR
France
Prior art keywords
main control
control gates
electronic component
multiple quantum
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1854109A
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English (en)
Other versions
FR3081155A1 (fr
Inventor
Louis Hutin
Sylvain Barraud
Benoit Bertrand
Maud Vinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Priority to FR1854109A priority Critical patent/FR3081155B1/fr
Priority to US16/413,652 priority patent/US11088259B2/en
Publication of FR3081155A1 publication Critical patent/FR3081155A1/fr
Application granted granted Critical
Publication of FR3081155B1 publication Critical patent/FR3081155B1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66977—Quantum effect devices, e.g. using quantum reflection, diffraction or interference effects, i.e. Bragg- or Aharonov-Bohm effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66984—Devices using spin polarized carriers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)

Abstract

L’invention concerne un procédé de fabrication d’un composant électronique (1) à multiples îlots quantiques, comprenant les étapes de : -fourniture d’un substrat (100) surmonté d’un nanofil (111) en matériau semi-conducteur non intentionnellement dopé, surmonté par au moins deux grilles de commande principales (112) de façon à former des qubits respectifs sous ces grilles de commande principales, lesdites deux grilles de commande principales étant séparées par une gorge (114), le sommet et les faces latérales des deux grilles de commande principales et le fond de la gorge étant recouverts par une couche de diélectrique (106) ; -dépôt d’un matériau conducteur : -dans ladite gorge (122) ; et -sur le sommet des deux grilles de commande principales ; -planarisation jusqu’à ladite couche de diélectrique au sommet des deux grilles de commande principales (112), de façon à obtenir un élément en matériau conducteur (122) auto-aligné entre lesdites grilles de commande principales. Figure à publier avec l’abrégé : Fig. 37
FR1854109A 2018-05-17 2018-05-17 Procede de fabrication d'un composant electronique a multiples ilots quantiques Active FR3081155B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1854109A FR3081155B1 (fr) 2018-05-17 2018-05-17 Procede de fabrication d'un composant electronique a multiples ilots quantiques
US16/413,652 US11088259B2 (en) 2018-05-17 2019-05-16 Method of manufacturing an electronic component including multiple quantum dots

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1854109 2018-05-17
FR1854109A FR3081155B1 (fr) 2018-05-17 2018-05-17 Procede de fabrication d'un composant electronique a multiples ilots quantiques

Publications (2)

Publication Number Publication Date
FR3081155A1 FR3081155A1 (fr) 2019-11-22
FR3081155B1 true FR3081155B1 (fr) 2021-10-22

Family

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Family Applications (1)

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FR1854109A Active FR3081155B1 (fr) 2018-05-17 2018-05-17 Procede de fabrication d'un composant electronique a multiples ilots quantiques

Country Status (2)

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US (1) US11088259B2 (fr)
FR (1) FR3081155B1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3081155B1 (fr) * 2018-05-17 2021-10-22 Commissariat Energie Atomique Procede de fabrication d'un composant electronique a multiples ilots quantiques
US11417765B2 (en) * 2018-06-25 2022-08-16 Intel Corporation Quantum dot devices with fine-pitched gates
US11107966B2 (en) * 2019-11-11 2021-08-31 International Business Machines Corporation Two-sided Majorana fermion quantum computing devices fabricated with ion implant methods
US11107965B2 (en) * 2019-11-11 2021-08-31 International Business Machines Corporation Majorana fermion quantum computing devices fabricated with ion implant methods
FR3119044B1 (fr) * 2021-01-18 2024-04-05 Commissariat Energie Atomique Procédé de fabrication de grilles d’échange auto-alignées et dispositif semi-conducteur associé
FR3120740A1 (fr) * 2021-03-15 2022-09-16 Commissariat A L'energie Atomique Et Aux Energies Alternatives Dispositif à deux niveaux de grilles de commande électrostatique superposés

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8829492B2 (en) 2010-11-05 2014-09-09 Chungbuk National University Industry-Academic Cooperation Foundation Multiple quantum dot device and a production method for the device
US9842921B2 (en) * 2013-03-14 2017-12-12 Wisconsin Alumni Research Foundation Direct tunnel barrier control gates in a two-dimensional electronic system
US9691033B2 (en) 2013-03-20 2017-06-27 Newsouth Innovations Pty Limited Quantum computing with acceptor-based qubits
EP3152153B1 (fr) 2014-06-06 2022-01-19 NewSouth Innovations Pty Limited Appareil de traitement avancé
EP3082073B1 (fr) * 2015-04-12 2019-01-16 Hitachi Ltd. Traitement d'informations quantiques
US10929769B2 (en) 2016-06-08 2021-02-23 Socpra Sciences Et Génie S.E.C. Electronic circuit for control or coupling of single charges or spins and methods therefor
WO2017213637A1 (fr) * 2016-06-08 2017-12-14 Intel Corporation Dispositifs à points quantiques pourvus de grilles à motifs
FR3081155B1 (fr) * 2018-05-17 2021-10-22 Commissariat Energie Atomique Procede de fabrication d'un composant electronique a multiples ilots quantiques

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Publication number Publication date
US20190371908A1 (en) 2019-12-05
US11088259B2 (en) 2021-08-10
FR3081155A1 (fr) 2019-11-22

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