FR3040539A1 - HIGH-VOLTAGE GALLIUM NITRIDE SCHOTTKY DIODE - Google Patents

Abstract

The invention relates to a Schottky diode comprising, between a lower face and an upper face: a silicon support (31); an undoped GaN layer (5); one or more patterns formed in an AlGaN layer (7) each extending between a first metallization (37) forming an ohmic contact and a second metallization (40) forming a Schottky contact; first vias (46) extending from the second metallizations to the upper face; and second vias (38) extending from the first metallizations to the lower face.

Description

HIGH VOLTAGE GALLIUM NITRIDE SCHOTTKY DIODE

Field

The present application relates to electronic components, and more particularly gallium nitride Schottky diodes, GaN, capable of operating at high voltage and high power.

Presentation of the prior art

US Pat. No. 8791,508 discloses electronic components such as diodes and transistors in which the main current flows laterally in a thin layer of gallium aluminum nitride, AlGaN, formed on a GaN layer.

FIG. 1A is a sectional view of a GaN Schottky diode portion which corresponds to FIG. 7 of US Pat. No. 8791,508. An undoped silicon support 1 is covered with a layer 3 of aluminum nitride, of which a layer 5 of undoped GaN, and a layer 7 of undoped AlGaN. Palladium metallizations 9 are deposited on the layer 7 and are framed by titanium-aluminum Ti-Al metallizations 11 formed through the layer 7. The metallizations 9 form Schottky contacts with the AlGaN layer and the metallizations 11 are in contact with each other. ohmic contact by their flanks with the AlGaN layer. Gold metallizations are deposited on the metallizations 9 and metallizations 17 in gold are deposited on the metallizations 11. The assembly is covered with an isolation layer 19.

The layer 7 of AlGaN in connection with the GaN layer 5 is capable of conducting a current laterally between the Schottky 9 and Ohmic metallizations 11. When the diode is forward biased, a current flows laterally from the sidewalls of the metallizations 11 towards the periphery of the metallizations 9.

FIG. 1B is an example of a plan view according to section B-B of FIG. Metallizations 9 and 11 comprise a set of alternating parallel strips. The bands 9 constitute the teeth of a first comb, and the bands 11 constitute the teeth of a second comb interwoven with the first. Only three teeth are shown in FIG. 1A, with a larger number of teeth shown in FIG. 1B for ease of understanding. Each of the combs is connected to a terminal, 20, 21, of the diode.

A problem is that, if the teeth of the combs are long and narrow, a non-negligible resistance appears in the on state. summary

Thus, an embodiment provides a Schottky diode comprising, between a lower face and an upper face: a silicon support; an undoped GaN layer; one or more patterns formed in an AlGaN layer each of which extends between a first metallization forming an ohmic contact and a second metallization forming a Schottky contact; first vias extending from the second metallizations to the upper face; and second vias extending from the first metallizations to the lower face.

According to one embodiment, the patterns are repeated periodically.

According to one embodiment, the silicon support is doped silicon.

According to one embodiment, the Shottky diode further comprises, between the silicon support and the GaN layer, an undoped silicon layer.

According to one embodiment, the Shottky diode further comprises, between the silicon support and the undoped silicon layer, a silicon oxide layer.

According to one embodiment, the second vias extend to the silicon support.

According to one embodiment, the Shottky diode comprises, in the undoped silicon layer, zones of doped silicon in contact with the second vias.

According to one embodiment, the second metallization comprises first islands repeated periodically.

According to one embodiment, the first metallization forms a honeycomb network.

According to one embodiment, the first metallization comprises second islands repeated periodically.

According to one embodiment, the first islands and the second islands form a checkerboard pattern.

Brief description of the drawings

These and other features and advantages will be set forth in detail in the following description of particular embodiments made without implied limitation in relation to the appended figures in which: FIG. 1A, previously described, is a partial view and in section of a GaN Schottky diode; Figure IB, described above, is a top view of a GaN Schottky diode; Figure 2 is a partial schematic sectional view of an embodiment of a GaN Schottky diode; FIG. 3 is a view from above of an example of a GaN Schottky diode topology; FIG. 4 is a view from above of another example of a GaN Schottky diode topology; and FIG. 5 is a partial schematic sectional view of another embodiment of a GaN Schottky diode. detailed description

The same elements have been designated with the same references in the various figures and, moreover, the various figures are not drawn to scale. For the sake of clarity, only the elements that are useful for understanding the described embodiments have been shown and are detailed.

In the following description, when reference is made to absolute position qualifiers, such as the terms "high", "low", etc., or relative, such as the terms "above", "higher", " ", etc., or to qualifiers for orientation, such as the terms" horizontal "," vertical ", etc., reference is made to the orientation of the sectional views.

Figure 2 is a partial schematic sectional view of an embodiment of a GaN Schottky diode.

To achieve the structure of FIG. 2, one may start from a wafer 30 of silicon-on-insulator (SOI) type, consisting of a P-type doped silicon support 31, covered with a layer 32 of silicon oxide. , on which is a layer 33 of silicon. On the layer 33, an undoped silicon layer 34, the function of which will be explained below, is preferably grown epitaxially. After that, a layer 3 of aluminum nitride, AlN, is epitaxially deposited on the undoped silicon layer 34. This layer 3 serves as an interface layer for the epitaxy of an undoped GaN layer on which an undoped AlGaN layer 7 is epitaxially deposited.

Conductive zones 36, only two of which are shown, are then produced. Each conductive zone comprises an upper portion or metallization 37 whose level reaches or exceeds the surface of the AlGaN layer 7 and which extends through the layer 7 in part of the GaN layer 5. In this way, each of the metallizations 37 is in ohmic contact with the layer 7 by its flanks. Each conductive zone 36 also comprises a vertical portion or via 38 which extends from a central portion of the upper portion through the layers 5, 3, 34, 33 and 32 and joins the support 31. The conductive zones 36 are for example Ti-Al.

Metallizations 40, only one of which is shown making Schottky contact with the AlGaN layer 7, are then deposited on the layer 7 between the metallizations 37. The surface of the assembly is then coated with an insulation layer 42. for example silicon oxide or silicon nitride. Openings are etched through the isolation layer 42 to the metallizations 40. A metallization 44, filling these openings and covering the surface of the device, is made. The openings filled with metal form vias 46 connecting the Schottky metallizations 40 to the metallization 44. The metallizations 40 are for example platinum or palladium or nickel or nickel-gold.

A metallization 48 in contact with the support 31 of doped silicon is made on the lower face of the wafer 30. The metallizations 44 and 48 may be made of copper or aluminum and may cover all of the lower and upper surfaces of the diode, to reduce the access resistance of the cathode and the anode. The metallizations 44 and 48 are respectively connected to cathode and anode terminals K and A. In the on state, a current coming from the terminal A flows from the support 31 of doped silicon and the vias 38 towards the metallizations 37. The current then flows horizontally, or laterally, in the layer 7 of AlGaN in connection with the layer 5 of GaN, to the Schottky metallizations 40, then propagates in the vias 46 to reach the terminal K. A l blocked state, the voltage applied between terminals K and A can reach several hundred volts. The insulating layers present between the conductive support 31 connected to the terminal A and the metallization 40 connected to the terminal K are subjected to this voltage. Insulating layer 34 of undoped silicon adds additional thickness to layers 3, 5 and 7, thus improving, if necessary, the voltage withstand.

In plan view, Schottky 40 and ohmic metallizations 37 may correspond to parallel and alternating teeth, in a manner similar to that described with reference to FIG. 1B. Each Schottky tooth 40 is then connected to the metallization 44 by several vias 46 arranged regularly. Each ohmic tooth is likewise connected to the support 31 by several vias.

The vias 38 apply the potential of the terminal A at several points of each ohmic tooth 37. Similarly, the vias 46 apply the potential of the terminal K at several points of each Schottky tooth. It is clear that the presence of multiple vias 38 and 46 can limit the resistance of access to the diode.

FIG. 3 is a view from above of another example of a GaN Schottky diode topology corresponding to the sectional view of FIG. 2. This top view is produced in the absence of the insulating layer 42 and the metallization. 44. Although only three metallizations have been shown in Figure 2, a larger number of metallizations is shown in Figure 3 to facilitate understanding.

The ohmic metallizations 37 form a continuous network of regular honeycomb hexagons. In the example shown, cylindrical vias 38, shown in dashed lines, are located at the nodes of the network. In the center of each of the hexagons is a hexagonal Schottky metallization island 40 of the same orientation as that of the network hexes. Each island 40 is in contact in its central part with a via 46. Thus, a ring of the layer 7 is present between each Schottky island 40 and the ohmic metallization 37 which surrounds it. According to numerical simulations carried out by the inventor, this configuration minimizes the surface of the diode. In addition, this configuration makes it possible to limit the surface area and the cost of the Schottky metallizations.

FIG. 4 is a view from above of another example of a GaN Schottky diode topology corresponding to the sectional view of FIG. 2.

The Schottky metallizations 37 and the ohmic metallizations 40 are islands of square shape and of the same dimensions which form two sets arranged in a checkerboard pattern. Each of the islands 36 and 40 occupies a central portion of each box, not shown, of the checkerboard. The vias 38 are in the center of the islands 37 and the vias 46 are in contact with the central part of the islets 40. This topology proves more effective than that with parallel strips.

Figure 5 is a partial schematic sectional view of another embodiment of a GaN Schottky diode. To achieve the structure of Figure 5, one starts from a massive doped silicon substrate, not an SOI wafer.

On a p-type doped silicon substrate 31a, an undoped silicon layer 34a is formed by epitaxy. In a next step, P type doped zones 50 are formed over the entire thickness of the layer 34a opposite the ohmic metallizations 37.

The diode comprises, from bottom to top, a metallization 48, the substrate 31a, the layer 34a with the two zones 50, a layer 3 of AlN, a layer 5 of GaN, a layer 7 of AlGaN, a layer of Isolation 42 and a metallization 44. Metallizations 37 are located above the zones 50, through the layer 7, between a level located in the layer 5 and a level located in the layer 42. The metallizations 37 are connected to the zones 50 through vias 38 passing through the layers 3 and 5. The Schottky metallizations 40 in contact with the layer 7 are located at a lower portion of the layer 42. The metallization 44 is in contact via vias 46 with Schottky metallizations 40.

The metallizations 37 are thus connected to the substrate 31a via vias 38 and conductive zones 50.

The metallizations 44 and 48 may be copper or aluminum and may cover all of the lower and upper surfaces of the Schottky diode to reduce the access resistance of the cathode and the anode. Alternatively, the doped areas 50 may be omitted from the structure of FIG. 5. To ensure the contact of the metallizations 37 with the substrate 31a, the vias 38 then extend through the undoped silicon layer 34a.

An advantage of the Schottky diodes according to the embodiments described above is that the resistance is low in the on state.

Another advantage is that the surface of the component is reduced because no additional space is required to make contact pads.

Another advantage is that the provision of an undoped silicon layer 34, 34a on a doped silicon support 31, 31a provides a less brittle (less brittle) structure than when the support is entirely undoped silicon. As a result, the GaN layer 5 may be thicker without the thermal processes associated with its epitaxy possibly breaking the support.

Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although particular periodic patterns repeated in hexagonal and square gratings have been described in connection with FIGS. 3 and 4, it is clear that other, preferably periodic, patterns may be provided.

Although the described structures are made from P-type doped silicon supports, identical structures can be made from N-type doped supports.

Claims (11)

1. Schottky diode comprising, between a lower face and an upper face: a silicon support (31, 31a); an undoped GaN layer (5); one or more patterns formed in an AlGaN layer (7) each extending between a first metallization (37) forming an ohmic contact and a second metallization (40) forming a Schottky contact; first vias (46) extending from the second metallizations (40) to the upper face; and second vias (38) extending from the first metallizations (37) to the lower face. The Schottky diode according to claim 1, wherein the patterns are periodically repeated. 3. Schottky diode according to claim 1 or 2, wherein the silicon support (31, 31a) is doped silicon. The Schottky diode according to claim 3, further comprising, between the silicon support and the GaN layer, an undoped silicon layer (34, 34a). The Schottky diode according to claim 4, further comprising, between the silicon carrier (31,31a) and the undoped silicon layer (34,34a), a silicon oxide layer (32). 6. Schottky diode according to any one of claims 3 to 5, wherein the second vias (38) extend to the support (31, 31a) of silicon. 7. Schottky diode according to claim 4, comprising, in the layer (34, 34a) of undoped silicon, zones (50) of doped silicon in contact with the second vias (38). 8. Schottky diode according to any one of claims 1 to 7, wherein the second metallization (40) comprises first islands repeated periodically. The Schottky diode according to claim 8, wherein the first metallization (37) forms a honeycomb network. 10. Schottky diode according to claim 8, wherein the first metallization (37) comprises second islands repeated periodically. The Schottky diode according to claim 10, wherein the first islands and the second islands form a checkerboard pattern.