FR3027128B1 - Appareil, systemes et procedes pour fournir une memoire cache a gestion efficace de la memoire - Google Patents

Appareil, systemes et procedes pour fournir une memoire cache a gestion efficace de la memoire Download PDF

Info

Publication number
FR3027128B1
FR3027128B1 FR1559545A FR1559545A FR3027128B1 FR 3027128 B1 FR3027128 B1 FR 3027128B1 FR 1559545 A FR1559545 A FR 1559545A FR 1559545 A FR1559545 A FR 1559545A FR 3027128 B1 FR3027128 B1 FR 3027128B1
Authority
FR
France
Prior art keywords
memory
systems
methods
recently used
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1559545A
Other languages
English (en)
Other versions
FR3027128A1 (fr
Inventor
Kanishk Rastogi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Western Digital Technologies Inc
Original Assignee
HGST Netherlands BV
Western Digital Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HGST Netherlands BV, Western Digital Technologies Inc filed Critical HGST Netherlands BV
Publication of FR3027128A1 publication Critical patent/FR3027128A1/fr
Application granted granted Critical
Publication of FR3027128B1 publication Critical patent/FR3027128B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0871—Allocation or management of cache space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G06F12/127—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning using additional replacement algorithms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/466—Transaction processing
    • G06F9/467—Transactional memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/22—Employing cache memory using specific memory technology
    • G06F2212/225—Hybrid cache memory, e.g. having both volatile and non-volatile portions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/31—Providing disk cache in a specific location of a storage system
    • G06F2212/313—In storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

La présente invention concerne un appareil, des systèmes et des procédés mettant en œuvre un mécanisme de suppression des données moins fréquemment utilisées pour identifier un bloc de mémoire d'une mémoire cache en vue de le supprimer. Le mécanisme moins fréquemment utilisé peut présenter un mode de fonctionnement similaire au mécanisme de suppression des données les moins récemment utilisées tout en nécessitant l'utilisation d'un mémoire moindre. Un contrôleur de mémoire peut mettre en œuvre le mécanisme de suppression des données moins récemment utilisées par la sélection d'un bloc de mémoire et la détermination de si oui ou non le bloc de mémoire est un des blocs de mémoire moins récemment utilisés. Si c'est le cas, le contrôleur de mémoire peut supprimer les données dans le bloc de mémoire sélectionné ; si ce n'est pas le cas, le contrôleur de mémoire peut poursuivre pour sélectionner d'autres blocs de mémoire jusqu'à ce que le contrôleur de mémoire sélectionne un des blocs de mémoire moins récemment utilisés.
FR1559545A 2014-10-08 2015-10-07 Appareil, systemes et procedes pour fournir une memoire cache a gestion efficace de la memoire Active FR3027128B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/509,597 US9501419B2 (en) 2014-10-08 2014-10-08 Apparatus, systems, and methods for providing a memory efficient cache
US14509597 2014-10-08

Publications (2)

Publication Number Publication Date
FR3027128A1 FR3027128A1 (fr) 2016-04-15
FR3027128B1 true FR3027128B1 (fr) 2019-04-26

Family

ID=54606223

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1559545A Active FR3027128B1 (fr) 2014-10-08 2015-10-07 Appareil, systemes et procedes pour fournir une memoire cache a gestion efficace de la memoire

Country Status (4)

Country Link
US (1) US9501419B2 (fr)
DE (1) DE102015013125A1 (fr)
FR (1) FR3027128B1 (fr)
GB (1) GB2533992B (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170123796A1 (en) * 2015-10-29 2017-05-04 Intel Corporation Instruction and logic to prefetch information from a persistent memory
WO2019147288A1 (fr) * 2018-01-29 2019-08-01 Hewlett-Packard Development Company, L.P. Protection de données dans un environnement de pré-système d'exploitation
US11294725B2 (en) 2019-11-01 2022-04-05 EMC IP Holding Company LLC Method and system for identifying a preferred thread pool associated with a file system
US11150845B2 (en) 2019-11-01 2021-10-19 EMC IP Holding Company LLC Methods and systems for servicing data requests in a multi-node system
US11288211B2 (en) * 2019-11-01 2022-03-29 EMC IP Holding Company LLC Methods and systems for optimizing storage resources
US11409696B2 (en) 2019-11-01 2022-08-09 EMC IP Holding Company LLC Methods and systems for utilizing a unified namespace
US11288238B2 (en) 2019-11-01 2022-03-29 EMC IP Holding Company LLC Methods and systems for logging data transactions and managing hash tables
US11741056B2 (en) 2019-11-01 2023-08-29 EMC IP Holding Company LLC Methods and systems for allocating free space in a sparse file system
US11392464B2 (en) 2019-11-01 2022-07-19 EMC IP Holding Company LLC Methods and systems for mirroring and failover of nodes
US20210240524A1 (en) * 2020-01-31 2021-08-05 Qualcomm Incorporated Methods and apparatus to facilitate tile-based gpu machine learning acceleration
US11893279B2 (en) * 2021-08-25 2024-02-06 Micron Technology, Inc. Access tracking in memory
US20240134801A1 (en) * 2022-10-19 2024-04-25 Samsung Electronics Co., Ltd. Methods and system for efficient access to solid state drive

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450562A (en) * 1992-10-19 1995-09-12 Hewlett-Packard Company Cache-based data compression/decompression
US5802568A (en) * 1996-06-06 1998-09-01 Sun Microsystems, Inc. Simplified least-recently-used entry replacement in associative cache memories and translation lookaside buffers
US8195878B2 (en) 2009-02-19 2012-06-05 Pmc-Sierra, Inc. Hard disk drive with attached solid state drive cache
US9582222B2 (en) 2009-04-30 2017-02-28 Western Digital Technologies, Inc. Pre-cache similarity-based delta compression for use in a data storage system
US8392658B2 (en) * 2009-07-10 2013-03-05 Apple Inc. Cache implementing multiple replacement policies
US8285936B2 (en) * 2009-10-20 2012-10-09 The Regents Of The University Of Michigan Cache memory with power saving state
US20120089781A1 (en) * 2010-10-11 2012-04-12 Sandeep Ranade Mechanism for retrieving compressed data from a storage cloud
JP5691448B2 (ja) * 2010-11-30 2015-04-01 富士ゼロックス株式会社 印刷文書処理システム、キャッシュ装置、データ処理装置及びプログラム
US8615636B2 (en) * 2011-03-03 2013-12-24 International Business Machines Corporation Multiple-class priority-based replacement policy for cache memory
US8972661B2 (en) * 2011-10-31 2015-03-03 International Business Machines Corporation Dynamically adjusted threshold for population of secondary cache
US10152423B2 (en) 2011-10-31 2018-12-11 International Business Machines Corporation Selective population of secondary cache employing heat metrics
US8966178B2 (en) 2012-01-17 2015-02-24 International Business Machines Corporation Populating a first stride of tracks from a first cache to write to a second stride in a second cache
US20130242425A1 (en) * 2012-03-16 2013-09-19 Toshiba America Electronics Components, Inc. Write reordering in a hybrid disk drive
US8732404B2 (en) 2012-03-28 2014-05-20 Altibase Corp. Method and apparatus for managing buffer cache to perform page replacement by using reference time information regarding time at which page is referred to
US9442858B2 (en) 2012-07-13 2016-09-13 Ianywhere Solutions, Inc. Solid state drives as a persistent cache for database systems
EP2706467A1 (fr) * 2012-09-05 2014-03-12 Awingu Nv Méthode d'accès à un contenu dans un système de stockage cloud et agent cloud, agent de cache cloud, et application cliente correspondants
CN104781797B (zh) * 2012-09-14 2017-05-31 英派尔科技开发有限公司 多处理器架构中的高速缓存一致性目录
US9003126B2 (en) * 2012-09-25 2015-04-07 Intel Corporation Apparatus, system and method for adaptive cache replacement in a non-volatile main memory system
CN103150136B (zh) 2013-03-25 2014-07-23 中国人民解放军国防科学技术大学 基于ssd的大容量缓存中的lru策略实现方法

Also Published As

Publication number Publication date
GB201517712D0 (en) 2015-11-18
FR3027128A1 (fr) 2016-04-15
US20160103765A1 (en) 2016-04-14
GB2533992A (en) 2016-07-13
DE102015013125A1 (de) 2016-04-14
GB2533992B (en) 2017-03-08
US9501419B2 (en) 2016-11-22

Similar Documents

Publication Publication Date Title
FR3027128B1 (fr) Appareil, systemes et procedes pour fournir une memoire cache a gestion efficace de la memoire
CY1121962T1 (el) Υποδοχεις τ κυτταρου
AR101262A1 (es) Plataforma de purificación para anticuerpos biespecíficos
EA202091540A1 (ru) Антитела к lilrb2
FR3033061B1 (fr) Systeme et procede de copie a l'ecriture sur un ssd
GB2538456A (en) Determining treatment fluid composition using a mini-reservoir device
BR112017017233A2 (pt) métodos e sistemas para enviar ordens
RU2014148962A (ru) Система и способ ограничения работы доверенных приложений при наличии подозрительных приложений
BR112016024515A2 (pt) proteínas do agonista do receptor trail de cadeia única
ECSP21052184A (es) Inhibidores de apol1 y sus métodos de uso
GB2530972A (en) Encrypted purging of data from content node storage
MX370212B (es) Evaluacion de reputacion de archivos.
CO2017010840A2 (es) Técnicas para manejar marcadores para archivos multimedia
CL2021000426A1 (es) Inhibidores de la interacción proteína-proteína keap1-nrf2.
FR3041806B1 (fr) Dispositif de memoire non volatile, par exemple du type eeprom, ayant une capacite memoire importante, par exemple 16mbits
GB2534009A8 (en) Aggregate service with user interface
CY1124700T1 (el) Κλειδι
FR3026447B1 (fr) Dispositif formant cle pour le maintien d'un frein d'ecrou
CY1125297T1 (el) Αναστολεις της il-8 για χρηση στην αγωγη της περιφερικης νευροπαθειας που επαγεται απο χημειοθεραπεια
MA38395A1 (fr) Marqueurs associés à des inhibiteurs de la voie wnt
WO2016050835A3 (fr) Inhibiteurs sélectifs de l'élastase neutrophilique pour traiter des états de douleur neuropathique et de douleur chronique comprenant une composante neuropathique
DK3752838T3 (da) Fremgangsmåde til bestemmelse af den samlede histaminnedbrydningskapacitet i biologiske prøver
FR3024525B1 (fr) Systemes et procedes de protection d'un conduit de vehicule
FR3020917B1 (fr) Lame courbe d'ebranchage, son utilisation, tete d'ebranchage et kit de coupe correspondants.
Imine et al. Foundations and Practice of Security

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLSC Publication of the preliminary search report

Effective date: 20181102

PLFP Fee payment

Year of fee payment: 5

TP Transmission of property

Owner name: WESTERN DIGITAL TECHNOLOGIES, INC., US

Effective date: 20200319

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8

PLFP Fee payment

Year of fee payment: 9