FR3020885B1 - Systeme et procede de mise en memoire cache des resultats de requete de lecture de dispositif a etat solide - Google Patents
Systeme et procede de mise en memoire cache des resultats de requete de lecture de dispositif a etat solide Download PDFInfo
- Publication number
- FR3020885B1 FR3020885B1 FR1554092A FR1554092A FR3020885B1 FR 3020885 B1 FR3020885 B1 FR 3020885B1 FR 1554092 A FR1554092 A FR 1554092A FR 1554092 A FR1554092 A FR 1554092A FR 3020885 B1 FR3020885 B1 FR 3020885B1
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- FR
- France
- Prior art keywords
- solid state
- state device
- caching
- data segment
- request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000007787 solid Substances 0.000 title abstract 7
- 238000000034 method Methods 0.000 title abstract 5
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/122—Replacement control using replacement algorithms of the least frequently used [LFU] type, e.g. with individual count value
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/064—Management of blocks
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/604—Details relating to cache allocation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Communication Control (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14275468 | 2014-05-12 | ||
US14/275,468 US9990298B2 (en) | 2014-05-12 | 2014-05-12 | System and method for caching solid state device read request results |
Publications (2)
Publication Number | Publication Date |
---|---|
FR3020885A1 FR3020885A1 (fr) | 2015-11-13 |
FR3020885B1 true FR3020885B1 (fr) | 2019-05-31 |
Family
ID=53489071
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1554092A Active FR3020885B1 (fr) | 2014-05-12 | 2015-05-07 | Systeme et procede de mise en memoire cache des resultats de requete de lecture de dispositif a etat solide |
Country Status (4)
Country | Link |
---|---|
US (1) | US9990298B2 (fr) |
DE (1) | DE102015005817B4 (fr) |
FR (1) | FR3020885B1 (fr) |
GB (1) | GB2528534B (fr) |
Families Citing this family (7)
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KR102540765B1 (ko) * | 2016-09-07 | 2023-06-08 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
US10503443B2 (en) * | 2016-09-13 | 2019-12-10 | Netapp, Inc. | Systems and methods for allocating data compression activities in a storage system |
US10719462B2 (en) * | 2018-09-25 | 2020-07-21 | Intel Corporation | Technologies for computational storage via offload kernel extensions |
US11537440B2 (en) * | 2019-12-19 | 2022-12-27 | Hewlett Packard Enterprise Development Lp | Infrastructure adaptive consistency level mechanism |
US11360669B2 (en) * | 2020-04-01 | 2022-06-14 | Hitachi, Ltd. | Storage device accelerator providing aggregation of divided plaintext data |
JP7197541B2 (ja) * | 2020-04-01 | 2022-12-27 | 株式会社日立製作所 | ストレージ装置 |
CN111651396B (zh) * | 2020-04-26 | 2021-08-10 | 尧云科技(西安)有限公司 | 一种优化的pcie完成包乱序管理电路实现方法 |
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-
2014
- 2014-05-12 US US14/275,468 patent/US9990298B2/en active Active
-
2015
- 2015-05-01 GB GB1507569.0A patent/GB2528534B/en active Active
- 2015-05-06 DE DE102015005817.7A patent/DE102015005817B4/de active Active
- 2015-05-07 FR FR1554092A patent/FR3020885B1/fr active Active
Also Published As
Publication number | Publication date |
---|---|
GB201507569D0 (en) | 2015-06-17 |
FR3020885A1 (fr) | 2015-11-13 |
DE102015005817A1 (de) | 2015-11-12 |
GB2528534A (en) | 2016-01-27 |
US9990298B2 (en) | 2018-06-05 |
US20150324134A1 (en) | 2015-11-12 |
GB2528534B (en) | 2017-02-15 |
DE102015005817B4 (de) | 2020-10-29 |
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