FR2969814A1 - Method of directly bonding semiconductor structures e.g. dies, involves directly bonding surface of copper metal feature on upper semiconductor structure to surface of copper metal feature on lower semiconductor structure - Google Patents

Abstract

The method involves forming a cap layer (118) that comprises a metal and silicon at a surface of a metal feature that comprises copper on a lower semiconductor structure (100). A surface of the metal feature is defined by the surface of the cap layer. Another bonding surface (220) of copper metal feature on the upper semiconductor structure (200) is directly bonded to the bonding surface (120) of the copper metal feature on the lower semiconductor structure. An independent claim is included for bonded semiconductor structure.

Description

The present invention relates to methods for directly bonding semiconductor structures, and semi structures, to each other directly to one another, and to semiconductor structures thereof, and to bonded semi-conductive structures formed therefrom. -conductors linked using these methods.

Background Three-dimensional (3D) integration of two or more semiconductor structures can bring a number of benefits to microelectronics applications. For example, three-dimensional integration of microelectronic components can result in improved electrical performance and power consumption while reducing the footprint area of the device.

See, for example, P. Garrou, and others, "The Handbook of 3D Integration," Wiley-VCH (2008). Three-dimensional integration of semiconductor structures can take place by attaching a semiconductor chip to one or more additional semiconductor chips (i.e., OV chip (D2D)), a semiconductor chip having one or more semiconductor wafers (i.e., semiconductor wafer chip (D2W)), as well as a semi-conductor wafer with one or more semiconductor wafers; additional conductors (i.e., semiconductor wafer semiconductor wafer (W2W)), or a combination thereof. The bonding techniques used to bond a semiconductor structure to another semiconductor structure can be classified in different ways, the first being the case where a layer of intermediate material is provided between the two semiconductor structures to bond them to each other. one to the other, and the second being the case where the link interface allows electrons (i.e., an electric current) to pass through the interface. "Direct binding methods" are processes in which a direct solid-solid chemical bond is established between two semiconductor structures to bond them to one another without using an intermediate bonding material between the two semi-conductive structures. -conductors to link them to each other. Metal-to-metal bonding methods have been developed for bonding a metallic material at a surface of a first semiconductor structure to a metallic material at a surface of a second semiconductor structure. Direct metal-to-metal bonding processes can also be classified according to the temperature range in which each is implemented. For example, some direct metal-metal bonding processes are carried out at relatively high temperatures, resulting in at least partial melting of the metallic material at the bonding interface. These direct bonding processes may be undesirable for use in bonding treated semiconductor structures that include one or more device structures, since relatively high temperatures may negatively affect device structures formed earlier. "Thermocompression bonding" processes are direct bonding processes in which pressure is applied between the bonding surfaces at high temperatures between two hundred degrees Celsius (200 ° C) and about five hundred degrees Celsius (500 ° C). and often between about three hundred degrees Celsius (300 ° C) and about four hundred degrees Celsius (400 ° C).

Additional direct link methods have been developed that can be operated at temperatures of 200 degrees Celsius (200 ° C) or less. These direct bonding processes carried out at temperatures of 200 degrees Celsius (200 ° C) or less are referred to herein as "ultra-low temperature" direct bonding processes. Ultra-low temperature direct bonding processes can be carried out by careful removal of surface impurities and surface compounds (eg, native oxides), and increasing the area of close contact between the two surfaces to the surface. atomic scale. The zone of close contact between the two surfaces is generally achieved by polishing the bonding surfaces to reduce the surface roughness to values close to the atomic scale, applying a pressure between the bonding surfaces, resulting in plastic deformation, or both polishing the bonding surfaces and applying pressure to obtain this plastic deformation.

Some ultra low temperature direct bonding methods can be implemented without applying pressure between the bonding surfaces at the bonding interface, although pressure can be applied between bonding surfaces at the bonding interface. link interface in other ultra-low temperature forward link methods to obtain an appropriate link resistance at the link interface. Ultra-low temperature direct bonding processes in which pressure is applied between the bonding surfaces are often referred to in the art as "power assisted bonding" or "BSA" processes. Thus, as used herein, the terms "surface assisted bonding" and "SAB" refer to and include any direct bonding process in which a first material is directly bonded to a second material by affixing the first material to the material. second material and applying pressure between the bonding surfaces at the bonding interface at a temperature of two hundred degrees Celsius (200 ° C) or less. Direct metal-to-metal bonds between active conductive characteristics in semiconductor structures may, in some cases, be subject to mechanical failure or electrical failure after a period of time even if an acceptable direct metal-to-metal bond can be established initially between the conductive characteristics of the semiconductor structures. Although not fully understood, it is believed that this failure may be at least partially caused by one or more of three associated mechanisms. The three associated mechanisms are stress localization, which can be favored by coarse grains, grain growth associated with deformation, and mass transfer at the bonding interface. This mass transfer at the link interface may be at least partly due to electromigration, phase separation, etc. Electromigration is the migration of metal atoms in a conductive material due to an electric current. Various methods for improving the lifetime of electromigration interconnections have been discussed in the art. For example, methods for improving the electromagnetic life of copper interconnects are discussed in J. Gambino et al., "Copper Interconnect Technology for the 32nm Node and Beyond," IEEE 2009 Custom Integrated Circuits Conference. CICC), pages 141 to 148.

Brief Summary This summary is provided to present a selection of concepts in a simplified form, which concepts are further described in the following detailed description of certain exemplary embodiments of the invention. This summary is not intended to identify the main characteristics or essential characteristics of the subject claimed, nor is it intended to be used to limit the scope of the subject claimed. In some embodiments, the present invention includes methods of directly connecting a first semiconductor structure to a second semiconductor structure. An encapsulation layer may be formed that includes a metal and silicon at a surface of a first metal feature on the first semiconductor structure. A surface of the encapsulation layer may define a first bonding surface of the first metal feature. A second bonding surface of a second metal feature on the second semiconductor structure may be bonded directly to the first bonding surface of the first metal feature on the first semiconductor structure.

In further embodiments, the present invention further includes methods of directly connecting a first semiconductor structure to a second semiconductor structure. A metal encapsulation layer may be formed at a surface of a first metal feature on the first semiconductor structure. A surface of the metal encapsulation layer defines a first bonding surface of the first metal feature. A second bonding surface of a second metal feature on the second semiconductor structure may be bonded directly to the first bonding surface of the first metal feature on the first semiconductor structure.

In yet other embodiments of methods of the invention, a first semiconductor structure may be directly bonded to a second semiconductor structure using methods in which a first metal feature on the first semiconductor structure is doped with impurities, and a second metal feature on the second semiconductor structure is directly bonded to the first metal feature on the first semiconductor structure. In further embodiments, the present invention includes linked semiconductor structures that can be formed using methods as described herein. For example, a bonded semiconductor structure may comprise a first semiconductor structure comprising a first metal feature, and a second semiconductor structure comprising a second metal feature. The second metallic characteristic of the second semiconductor structure can be directly related to the first metal characteristic of the first semiconductor structure. Impurities may be present at a bonding interface between the first metal feature and the second metal feature. In other embodiments, the bonded semiconductor structures may comprise a first semiconductor structure including a first metal feature having a first major surface, and a second semiconductor structure including a second metal feature at least partially surrounded by a dielectric material. The second metal feature of the second semiconductor structure may have a second major surface bonded directly to a portion of the first major surface of the first metal feature of the first semiconductor structure. An encapsulating material may be disposed directly between one surface of the dielectric material and another portion of the first major surface of the first metallic feature of the first semiconductor structure. Brief Description of the Drawings The present invention may be more fully understood with reference to the following detailed description of exemplary embodiments of the present invention, which are illustrated in the accompanying figures, in which: Figs. 1A to 1G are simplified cross-sectional views illustrating exemplary embodiments of methods of forming bound semiconductor structures of the invention; Figs. 2A to 2F are simplified cross-sectional views illustrating additional exemplary embodiments of linked semiconductor structure forming methods of the invention; and Figures 3A-3G are simplified cross-sectional views illustrating additional exemplary embodiments of linked semiconductor structure forming methods of the invention.

Detailed Description The illustrations presented herein do not represent actual views of any particular material, device, system, or process, but are merely idealized representations that are used to describe embodiments of the invention. The items used in this document should not be construed as limiting the scope of the embodiments of the invention as defined by the claims below and their legal equivalents. The concepts described in any specific topic are generally applicable to other sections throughout the entire description. As used herein, the term "semiconductor structure" refers to and includes any structure that is used in the formation of a semiconductor device. Semiconductor structures include, for example, chips and semiconductor wafers (for example, support substrates and device substrates), as well as composite assemblies or structures that include two chips and / or semi-wafers. -conductors or more integrated three-dimensionally with each other. Semiconductor structures also include fully fabricated semiconductor devices, as well as intermediate structures formed during the fabrication of semiconductor devices. As used herein, the term "treated semiconductor structure" means and includes any semiconductor structure that includes one or more at least partially formed device structures. The processed semiconductor structures are a subset of semiconductor structures, and all semiconductor structures treated are semiconductor structures. As used herein, the term "bonded semiconductor structure" refers to and includes any structure that includes two or more semiconductor structures that are bonded to each other. The linked semiconductor structures are a subset of semiconductor structures, and all related semiconductor structures are semiconductor structures. In addition, the bonded semiconductor structures that include one or more processed semiconductor structures are also treated semiconductor structures. As used herein, the term "device structure" means and includes any portion of a treated semiconductor structure, i.e., includes, or defines at least a portion of a active or passive component of a semiconductor device to be formed on or in the semiconductor structure. For example, the device structures comprise active and passive integrated circuit components such as transistors, transducers, capacitors, resistors, conductive lines, conductive vias, and conductive contact pads.

As used herein, the term "through-wafer interconnection" or "TWI" means and includes any conductive via which extends through at least a portion of a first semiconductor structure which is used to provide a structural and / or electrical interconnection between the first semiconductor structure and a second semiconductor structure through an interface between the first semiconductor structure and the second semiconductor structure. Interconnections across the semiconductor wafer are also referred to in the art by other expressions, such as "vias through silicon", "vias through the substrate", "vias" interconnection across the semiconductor wafer ", or abbreviations of such expressions, such as" TSV "or" TWV ". The TWIs generally extend through a semiconductor structure in a direction generally perpendicular to the generally flat major surfaces of the semiconductor structure (i.e., in a direction parallel to the "Z" axis) . As used herein, the term " active surface ", when used in connection with a treated semiconductor structure, means and includes an exposed major surface of the treated semiconductor structure that has been, or will be, treated to form one or more device structures in and / or on the exposed major surface of the treated semiconductor structure. As used herein, the term "back surface", when used in connection with a treated semiconductor structure, means and includes an exposed major surface of the semiconductor structure treated on one side of the structure. treated semiconductor opposite an active surface of the semiconductor structure. In some embodiments, the present invention includes improved methods of directly connecting a first semiconductor structure to a second semiconductor structure to form a bonded semiconductor structure. In particular, embodiments of the invention may include methods of forming direct metal-metal bonds between metal features of a first semiconductor structure and metal characteristics of a second semiconductor structure, so that the lifetime of the electromigration of the bound metal characteristics is prolonged compared to previously known methods. In some embodiments, the direct metal-to-metal bonding methods of the invention may include non-thermocompression bonding methods. A first set of exemplary embodiments of the invention is described below with reference to Figs. 1A-1G. Referring to Figure 1A, a first semiconductor structure 100 may be formed. The first semiconductor structure 100 may include one or more active device features, such as, for example, one or more of a plurality of transistors 102 (which are schematically represented in the figures), a plurality of vias. vertically extending conductors 104, a plurality of horizontally extending conductive tracks 106, and a plurality of bond pads 108. One or more conductive vias 104, one or more conductive tracks 106, and / or one or more Bond pads 108 may be exposed at an active surface 110 of the first semiconductor structure 100. The active device features may include electrically conductive materials and / or semiconductor materials that are surrounded by a material. non-conductive dielectric 112. By way of example and not limitation, one or more of the viasxi On conductors 104, conductive tracks 106 and bond pads 108 may comprise a metal or a conductive metal alloy such as, for example, copper, aluminum, or an alloy or a mixture thereof. According to some embodiments of the invention, an encapsulation layer comprising a metal and silicon (for example, a metal silicide) may be formed at a surface of at least one metallic feature of the first semi structure. and -conductor 100 before directly bonding this metallic feature to at least one metallic feature of a second semiconductor structure, as described in more detail below. As a non-limiting example, one or more bonding pads 108 may be exposed at the active surface 110 of the first semiconductor structure 100. In formation of the bond pads 108, a material based on The oxide 114 may be disposed at (eg, on or in) the exposed major surface of the bond pads 108. By way of example and not limitation, the bond pads 108 may comprise copper or a copper alloy and the oxide material 114 may comprise a copper oxide (eg, CuxO). The oxide material 114 may result from intentional or involuntary oxidation of the exposed surfaces of the bonding pellets 108, and may result from one or more previously performed processes, such as a chemical-mechanical polishing process ( CMP) performed during the manufacture of the bond pads 108. The oxide material 114 may also simply result from the exposure of the bond pads 108 to a gas comprising oxygen (eg, air). Referring to Fig. 1B, the oxide material 114 may be removed from the bond pads 108. By way of example and not limitation, a wet chemical etching process or a dry plasma etching process may be used to remove the oxide material 114 from the bond pads 108. For example, dry argon plasma etch processes may be used to etch the oxide material 114. As examples inorganic acids such as hydrochloric acid and / or nitric acid, as well as organic acids such as citric acid and / or acetic acid, can be used in wet chemical etching processes to remove the oxide material 114. After removal of any oxide material 114 which may be present on the surface of the bond pads 108, an encapsulation layer 116 comprising silicon may be formed at the (For example, on or in) the exposed major surface of the bond pads 108, as shown in Fig. 1C. As a non-limiting example, in embodiments in which the bond pads 108 comprise copper or a copper alloy, the encapsulation layer 116 comprising silicon may comprise copper silicide (e.g., CuSix ). The copper silicide may be formed at the surface of the bond pads 108 comprising copper or a copper alloy, for example, by exposing the exposed surfaces 115 of the bond pads 108 to a gas comprising SiH4. By way of example and not limitation, the encapsulation layer 116 may comprise what is referred to in the art as a self-aligned barrier (SAB) formed using a plasma enhanced chemical vapor deposition (PECVD) ( which SAB are often referred to in the PSAB art) as presented, for example, in the papers of Chattopadhyay and others, In Situ Formation of a Copper Silicide Cap for TDDB and Electromigration Improvement, IEEE 06CH37728, 44th Annual International Reliability Physics Symposium , San Jose, 2006; L. L. Gosset and others, Advanced Metallization Conference, 2003; and S. Chhun and others, Microelectronic Engineering 76, 2004, page 106. The PSAB process has high selectivity, low cost of implementation and interconnectivity reliability benefits. The high selectivity of the PSAB process can occur through the natural differences in reactivity and reaction products of the gaseous constituents in the CVD process with the copper and dielectric surfaces. In Si-based PSAB, SiH4 exhibits a thermally activated reaction with copper, but the reaction on the dielectric surface results in the formation of an insulating film on the dielectric material 112. In other words, the PSAB process, in addition to forming a copper silicide encapsulation layer 116 on the bond pads 108, can form an SiC layer (not shown) on the exposed major surface of the dielectric material 112. The presence of copper silicide on the surface of the copper bond pads 108 protects the copper from oxidation.

In some embodiments, the encapsulation layer 116 may be formed to have an initial average thickness of about forty nanometers (40 nm) or less, about twenty nanometers (20 nm) or less, or even about ten nanometers (10 nm) or less (i.e., prior to binding and / or subsequent treatment). In some embodiments, the encapsulation layer 116 comprising silicon may further be processed to modify a composition of the encapsulation layer 116. By way of example and not limitation, the encapsulation layer 116 comprising silicon may be exposed to a gas or plasma comprising nitrogen (NH3) to form an encapsulation layer 118 which comprises both silicon and nitrogen atoms. As a non-limiting example, in embodiments in which the encapsulation layer 116 comprises copper silicide (eg, CuSix), the copper silicide may be exposed to an NH 3 plasma to form nitride of silicon-copper (CuSiN). By way of example and not limitation, an encapsulation layer 116 of silicon-copper nitride may be formed as disclosed in US Patent Application Publication No. 2008/0 213 997 A1, published September 4, 2008, at US Pat. name of Lee and others. For example, the bonding pellets 108 may be exposed to a first plasma obtained from helium, after which the bonding pellets 108 may be exposed to a second plasma obtained from a reducing gas to remove the oxide of copper from the copper surface. The bonding pellets can then be exposed to a silane, which reacts with the copper surface of bond pellets 108 to selectively form copper silicide. After formation of the copper silicide on the surfaces of the bond pads 108, the bond pads 108 may be exposed to a third plasma obtained from ammonia and molecular nitrogen to form the silicon-copper nitride on the surfaces. bond pads 108.

After formation of the encapsulation layer 118 which comprises atoms of a metal, silicon and nitrogen (eg, CuSiN), the bond pads 108 may be directly related to the metal characteristics of a second structure semiconductor. Referring to Figure 1E, the first semiconductor structure 100 may be aligned with the second semiconductor structure 200 so that the bond pads 108 of the first semiconductor structure 100 are aligned with the bond pads 208. conductive metal of the second semiconductor structure 200. As shown in FIG. 1E, the second semiconductor structure 200 may comprise additional active device structures, such as, for example, conductive vias 204 extending vertically, conductive tracks 206 extending laterally. Although not shown in the figures, the second semiconductor structure 200 may also comprise transistors. The surfaces of the encapsulation layers 118 on the bond pads 108 may define one or more bonding surfaces 120 of the bond pads 108, and the exposed surfaces outside the bond pads 208 may define the bonding surfaces 220 of the bonding pads 108. The second semiconductor structure 200. With reference to FIG. 1F, after the alignment, the first semiconductor structure 100 may be aligned with the second semiconductor structure 200 so that the bonding pads 108 of the first semiconductor structure 100 are aligned with the conductive metal bond pads 208 of the second semiconductor structure 200, the first semiconductor structure 100 can be abutted against the second semiconductor structure 200 so that that the connecting surfaces 120 of the bonding pads 108 of the first semiconductor structure 100 are intended e directly against the connecting surfaces 220 of the bonding pads 208 of the second semiconductor structure 200. With reference to FIG. 1G, the bonding surfaces 120 of the bonding pads 108 of the first semiconductor structure 100 can then be be directly connected to the bonding surfaces 220 of the bond pads 208 of the second semiconductor structure 200 to form a bonded semiconductor structure 300. For example, the bonding surfaces 220 of the bond pads 208 of the second semiconductor structure 200 may be directly bonded to the bonding surfaces 120 of the bond pads 108 of the first semiconductor structure 100 in a non-direct metal-metal thermocompression bonding process (eg, copper-copper), which in some cases Embodiments may be performed at temperatures of four hundred degrees Celsius (400 ° C) or less. In additional embodiments, the non-thermocompression bonding process may include an ultra low temperature direct bonding process performed at temperatures of two hundred degrees Celsius (200 ° C) or less. As shown in FIG. 1G, in some embodiments, during direct bonding of the bond pads 108 of the first semiconductor structure 100 to the bond pads 208 of the second semiconductor structure 200, one or more elements of the encapsulation layer 118 at the interface between the bond pads 108 and the bond pads 208 may diffuse into the bond pads 108 and / or the bond pads 208, so that the encapsulation layer 118 is no longer present as a separate phase at the bonded interface between bond pads 108 and bond pads 208. At least a portion of encapsulation layer 118 can remain on at least a portion of bond pads 108, as shown in Figure 1G. The presence of at least a portion of the encapsulation layer 118 on the bonding pellets 108 as a result of the bonding process may be beneficial for reasons discussed in more detail below. Prior to bonding the first semiconductor structure 100 to the second semiconductor structure 200, the first semiconductor structure 100 and the second semiconductor structure 200 may be treated to remove surface impurities and undesired surface compounds. 10 and can be flattened to increase the narrow contact area at the atomic scale between the bonding surfaces 120 of the bond pads 108 and the bonding surfaces 220 of the bond pads 208. The area of close contact between the bonding surfaces 120 and the bonding surfaces 220 can be obtained by polishing the bonding surfaces 120 and bonding surfaces 220 to reduce the surface roughness thereof to values near the atomic scale, applying pressure between the connecting surfaces 120 and the connecting surfaces 220, which results in plastic deformation, or both polishing the connecting faces 120, 220 and applying a pressure between the first semiconductor structure 100 and the second semiconductor structure 200 to obtain this plastic deformation. In some embodiments, the first semiconductor structure 100 may be directly bonded to the second semiconductor structure 200 without applying pressure between the bonding surfaces 120, 220 at the bonding interface therebetween, although that pressure can be applied between the bonding surfaces 120, 220 at the bonding interface in some ultra-low temperature forward link methods in order to obtain an appropriate bond strength at the bonding interface. link. In other words, the direct bonding methods used to bond the bond pads 108 of the first semiconductor structure 100 to the bond pads 208 of the second semiconductor structure 200 may include power assisted bonding methods of surfaces (SAS). ) in some embodiments of the invention.

In some embodiments, the bond pads 108 and the bond pads 208 may differ in at least one of a size and shape. More particularly, the bond pads 108 may have a first cross-section in a plane parallel to the bonded interface between the bond pads 108 and the bond pads 208, and the bond pads 208 may have a second cross-section in a parallel plane to the bonded interface between the bond pads 108 and the bond pads 208 which differs from the first cross section of the bond pads 108. The bond pads 108 may have a first sectional shape in a plane parallel to the linked interface between the bond pads 108 and the bond pads 208, and the bond pads 208 may have a second sectional shape in a plane parallel to the bonded interface between the bond pads 108 and the bond pads 208 which differs from the first sectional form of the bond pads 108. In the embodiments in which the liai pellets are its 108 and the bond pads 208 have different shapes, they can have the same or different sizes. In further embodiments, the bond pads 108 and the bond pads 298 may have at least substantially the same size and shape in cross-section at the bonding interface therebetween. However, in these embodiments, the bond pads 108 and the bond pads 208 may be intentionally or unintentionally misaligned with respect to one another. In embodiments in which the bond pads 108 and bond pads 208 differ in at least one of the size and shape and / or are misaligned relative to each other, at least one part of the encapsulation layer 118 on one or more of the bond pads 108 may not be abutted against, and may not be directly bonded to any portion of a bond pad 208. These portions of the layer encapsulation 118 may abut against a dielectric material 212 surrounding the bond pads 208, for example. These portions of the encapsulation layer 118 may or may not be bonded to the dielectric material 212 abutting, and may not fully dissolve in the bond pads 108 when bonding pads 108 are bonded to the bonding pellets. In these embodiments, the presence of at least a portion of the encapsulation layer 118 at the interface between the bond pads 108 and the dielectric material 212 after the bonding process may improve the bonding. useful life and / or improve the performance of the conductive structures formed by the connecting pads 108 and contiguous bond pads 208. For example, the presence of the encapsulation layer 118 at the interface between the bond pads 108 and the dielectric material 212 may impede or prevent mass transfer at the interface between the bond pads 108. and the dielectric material 212, which can occur due to, for example, electromigration. The presence of the encapsulation layer 118 may also suppress the occurrence of undesirable thermomechanical phenomena, such as, for example, undesirable changes in the microstructure that may result from temperature fluctuations at which the structures may be subjected during treatment and / or or subsequent operation. In further embodiments, the exposed surfaces of one or more active characteristics of the second semiconductor structure 200, such as the exposed surfaces of the bond pads 208, may be treated as discussed above in connection with the connecting pads 108 of the first semiconductor structure, so that the bonding surfaces 220 of the bonding pads 108 comprise an encapsulation layer (similar to the encapsulation layer 116 and / or the encapsulation layer 118) which may comprise a compound or mixture (e.g., solid solution) which comprises one or both of silicon and nitrogen (e.g., CuSix or CuSiN). In the embodiments described above in relation to FIGS. 1A to 1G, the encapsulation layers 116, 118 are not metallic in nature (that is, the atomic bonds between the atoms are not substantially metallic bonds, but rather of ionic and / or covalent nature), but are rather dielectric materials, although they include metal atoms such as copper (in addition to non-metallic elements such as silicon and / or or nitrogen). Additional embodiments of the invention include methods similar to those described above in connection with Figs. 1A to 1G, but wherein the encapsulation layer comprises a metal encapsulation layer. Examples of these embodiments are described below with reference to FIGS. 2A-2F. FIG. 2A illustrates a first semiconductor structure 400 which is substantially identical to the first semiconductor structure 100 of FIG. 1A, and comprises active devices comprising transistors 102, conductive vias 104 extending vertically, conductive tracks 106 extending horizontally and bond pads 108. At least some of the active devices may be surrounded by a dielectric material 112. The first semiconductor structure 400, during the formation thereof, may comprise an oxide material 114 at an exposed surface of the bond pads 108, as discussed previously in connection with the semiconductor structure 100 of FIG. 1A. For example, the bond pads 108 may comprise a metal or metal alloy (eg, copper, copper alloy, CoSnP, PD, etc.), and the oxide material 114 may comprise a oxide of this metal (for example, a copper oxide). As shown in Fig. 2B, the oxide material 114 may be removed from the bond pads 108 using, for example, a wet chemical etching process or a dry plasma etching process, as previously described with reference in Figure 1B. Referring to FIG. 2C, a metal encapsulation layer 416 may be formed on and / or in the exposed surfaces 115 of the bond pads 108 after removal of the oxide material (FIG. The metal encapsulation layer 416 may have a composition different from a composition of the bonding pellets 108, and may have a composition selected to impede or prevent undesirable atomic diffusion and / or thermomechanical phenomena which could occur at the link interface formed during a subsequent link process. As a non-limiting example, the metal encapsulation layer may comprise a metal alloy that comprises cobalt, tungsten and phosphorus (CoWP) atoms. A metal encapsulation layer comprising CoWP can be formed using electroless deposition processes with dimethylaminoborane (DMAB) as a reducing agent, as is known in the art. For further details, see, for example, the Gambino and other documents, YEEE Interconnect Technology Conference, 2006 International, June 5 to 7, 2006, pages 30 to 32; and Yokogawa et al., Tradeoff Characteristics Between Resistivity and Reliability for Scaled-Down Cu-Based Interconnects, IEEE Transactions On Electron Devices, Vol. 55, No. 1, pages 350 to 357 (January 2008). In some embodiments, the metal encapsulation layer 416 may have an average thickness of about forty nanometers (40 nm) or less, about twenty nanometers (20 nm) or less, or even about ten nanometers ( 10 nm) or less before the linking process. The metal encapsulation layer 416 may be formed on and / or in the exposed surfaces 115 (Fig. 2B) using, for example, one or more of an electroless plating process, an electroless plating process, a physical deposition process, a physical vapor deposition (PVD) process and a chemical vapor deposition (CVD) process. After forming the metal encapsulation layer 416, the bond pads 108 may be directly related to the metal characteristics of a second semiconductor structure. Referring to Fig. 2D, the first semiconductor structure 400 may be aligned with a second semiconductor structure 200. As previously described with reference to Fig. 1E, the second semiconductor structure 200 may include a plurality of features. active device devices, which may include, for example, one or more bond pads 208, vertically extending conductive vias 204 and horizontally extending conductive tracks 206. The active device characteristics of the second semiconductor structure 200 may be surrounded by a dielectric material 212. The first semiconductor structure 400 may be aligned with the second semiconductor structure 200 so that the bond pads 108 of the first semiconductor structure 400 is aligned with the conductive metal bond pads 208 of the second semiconductor structure 200. The surfaces of the metal encapsulation layers 416 on the bond pads 108 may define one or more bonding surfaces 420 connecting pads 108, and the exposed outer surfaces of the bond pads 208 may define bonding surfaces 220 of the bond pads 208 of the second semiconductor structure 200. Referring to FIG. alignment of the first semiconductor structure 400 and the second semiconductor structure e 200 so that the bond pads 108 of the first semiconductor structure 400 are aligned with the conductive metal bond pads 208 of the second semiconductor structure 200, the first semiconductor structure 400 can be abutted against the second semiconductor structure 200 so that the connecting surfaces 420 of the bonding pads 108 of the first semiconductor structure 400 are directly abutting against the bonding surfaces 220 of the bonding pads 208 of the second semiconductor structure 200. Referring to FIG. 2F, the bonding surfaces 420 of the bond pads 108 of the first semiconductor structure 400 can then be directly bonded to the bonding surfaces 220 of the bond pads 208 of the second semiconductor structure. 200 to form the bonded semiconductor structure 500 shown in FIG. 2F. The bonding surfaces 220 of the bonding pads 208 of the second semiconductor structure 200 may be directly bonded to the bonding surfaces 420 of the bonding pads 108 of the first semiconductor structure 400 as previously described with reference to FIGS. 1F and 1G. in relation to the first semiconductor structure 100 and the second semiconductor structure 200. As shown in Fig. 2F, in some embodiments, at the direct bonding of the bond pads 108 of the first semiconductor structure 400 at the bond pads 208 of the second semiconductor structure 200, one or more elements of the metal encapsulation layer 416 at the interface between the bond pads 108 and the bond pads 208 may diffuse into the pellets of link 108 and / or the bonding pads 208, so that the metal encapsulation layer 418 is no longer present in tan t that distinct phase at the interface bound between the bond pads 108 and the bond pads 208. At least a portion of the metal encapsulation layer 416 can remain on at least a portion of the bond pads 108, as shown in Figure 2F. The presence of at least a portion of the metal encapsulation layer 416 on the bond pads 108 as a result of the bonding process may be beneficial for the reasons discussed earlier herein with reference to Figure 1G.

In the embodiments described above, metal and / or non-metal encapsulation layers are used to enhance the features of the directly bonded metal features. In further embodiments of the invention, the metal features may be selectively doped with one or more doping elements to reduce electromigration or otherwise improve the performance and / or service life of the directly bonded metal features. Examples of these embodiments are described below with reference to FIGS. 3A-3G. FIG. 3A illustrates a first semiconductor structure 600 which is generally similar to the first semiconductor structure 100 of FIG. 1A in that the semiconductor structure 600 comprises transistors 102, conductive vias 104 '. extending vertically and conductive tracks 106 extending horizontally. The first semiconductor structure 600 of Figure 3A is shown prior to the formation of bond pads 608 doped thereon, which are shown in Figure 3C. In some embodiments, the bond pads 608 (Fig. 3C) may be doped during manufacture of the bond pads 608, as described with reference to Figs. 3A-3C. In other embodiments, however, the bond pads 608 may be doped after formation of the bond pads 608.

As shown in Fig. 3A, recesses 630 may be formed in the first semiconductor structure 600 at locations at which bond pads 608 are desired to be formed (Fig. 3C). For example, standard masking and etching processes may be used to form these recesses 630 in the first semiconductor structure 600. A coating material 632 may be provided above (eg, on) at least exposed surfaces. of the semiconductor structure 600 in the recesses 630, although the coating material 632 can be deposited in conformity on at least the substantially entire active surface 610 of the first semiconductor structure 600, as shown in FIG. 3A. The coating material 632 may comprise, for example, a barrier material having a composition selected to impede or prevent the diffusion of one or more atomic species through the coating material 632. By way of example and not limitation the coating material 632 may comprise a material such as, for example, TaN or TiN. The coating material 632 may be provided on the semiconductor structure 600 using one or more of, for example, a chemical vapor deposition (CVD) process, a physical deposition process (e.g. sputtering), a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and an electroless deposition process.

Continuing to refer to FIG. 3A, a doped metal seed material 634 may be deposited on the coating material 632. The doped metal seed material 634 may be used to facilitate the deposition of additional solid metal material on the as discussed in more detail below with reference to Figure 3B. By way of example and not limitation, the doped metal seed material 634 may be substantially composed of a metal or a metal alloy. As a non-limiting example, the doped metal seed material 634 may be substantially composed of copper or copper alloy. The doped metal seed material 634 may further comprise one or more doping elements. As non-limiting examples, the doping elements may comprise one or more of aluminum, silver and manganese. The doping elements can be introduced into the metal seed material 634 during the deposition of the metal seed material 634 on the coating material 632, or the doping elements can be introduced into the metal seed material 634 after formation of the seed material. metallic material 634 on the coating material 632. The doped metal seed material 634 may be provided on the semiconductor structure 600 using one or more of, for example, a chemical vapor deposition (CVD) process, a physical deposition process (eg, sputtering), a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process and an electroless deposition process. Referring to FIG. 3B, after the formation of the doped metal seed material 634 on the coating material 632, the metal seed material 634 can be used to facilitate deposition of a solid metal material 636 thereon, for example, in an electrolytic deposition process. For example, the doped metal seed material 634 may be substantially composed of doped copper or a doped copper alloy, and the solid metal material 636 may comprise solid copper, which may be deposited on the doped metal seed material 634 using an electrolytic deposition process. After deposition of the solid metal material 636 on the doped metal seed material 634, the first semiconductor structure 600 may be subjected to an annealing process to bring the doping elements (eg, Al, Ag, Mn, etc.) to diffuse into the bulk metal material 636. The presence of the doping elements in the bulk metal material 636 may be beneficial for the reasons discussed in more detail below. The concentration of the doping elements in the bulk metal material 636 can be selectively controlled by selectively controlling the thickness at which the doped metal seed material 634 is deposited on the coating material 632, as presented in the Yokogawa document. and others, Analysis of Al Doping Effects on Resistivity and Electromigration of Copper Interconnects, IEEE Transactions on Device and Materials Reliability, Volume 8, Publication 1, pp. 216-221 (March 2008). In further embodiments of the invention, the solid metal material 636 may be deposited on the coating material 632 using one or more processes other than an electrolytic process. For example, solid metal material 636 can be deposited using one or more of a chemical vapor deposition (CVD) process, a physical deposition process (eg, sputtering), a physical vapor deposition (PVD), an atomic layer deposition (ALD) process and an electroless deposition process, and can be doped with the doping elements as it is deposited. In some embodiments, the solid metal material 636 may be deposited at an average thickness which is sufficient to at least substantially fill the recesses 630 (Fig. 3A), and excess bulk metal material 636 may be present on the active surface 610. of the first semiconductor structure 600. Thus, with reference to FIG. 3C, after the deposition of the solid metal material 636, the massive metallic material 636 in excess can be removed using, for example, an etching process, a polishing process, or a chemical-mechanical polishing process (CMP). As a non-limiting example, the active surface 610 of the first semiconductor structure 600 may be subjected to a chemical-mechanical polishing process to remove the bulk metal material 636 in excess of the active surface 610, but leaving the solid metal material 636 in the recesses 630, thereby defining electrically conductive bond pads 608 in the active surface 610 which include the volumes of the doped solid metal material 636 disposed in the recesses 630 (Fig. 3A). As shown in FIG. 3D, an encapsulation layer 618 can be deposited at least on the exposed surfaces of the bond pads 608, and can be deposited at least substantially entirely on the active surface of the first semiconductor structure 600. By way of example and not limitation, the encapsulation layer 618 may comprise a layer of a material, such as a carbide (for example, silicon carbide), a nitride (for example, silicon nitride) , an oxide (for example, silicon oxide), etc. In further embodiments, the encapsulation layer 618 may comprise a material as previously described herein in connection with the encapsulation layer 116, the encapsulation layer 118, or the encapsulation layer 418, and may be formed as previously described in connection therewith. By way of example and not limitation, the encapsulation layer 116 may be formed to have an initial average thickness of about forty nanometers (40 nm) or less, of about twenty nanometers (20 nm) or less, or even about ten nanometers (10 nm) or less (i.e., before bonding and / or other subsequent treatment). The encapsulation layer 618 may be one or more of a vapor phase (PVD), a vapor phase (CVD), a etc. 618, formed in process process process After using, for example, physical deposition of atomic layer deposition chemical deposition (ALD), formation of the encapsulation layer bonding pads 608 can be directly related to the metal characteristics of a second semiconductor structure. Referring to Fig. 3E, the first semiconductor structure 600 may be aligned with a second semiconductor structure 200. As described previously with reference to Fig. 1E, the second semiconductor structure 200 may include a plurality of features. active device devices, which may include, for example, one or more bond pads 208, vertically extending conductive vias 204 and horizontally extending conductive tracks 206. The active device characteristics of the second semiconductor structure 200 may be surrounded by a dielectric material 212. The first semiconductor structure 600 may be aligned with the second semiconductor structure 200 so that the bonding pads 608 of the the first semiconductor structure 600 is aligned with the conductive metal bond pads 208 of the second semiconductor structure 200. The surfaces of the encapsulation layer 618 on the bond pads 608 may define one or more bonding surfaces 640 connecting pads 608, and the exposed outer surfaces of the bond pads 208 may define the bonding surfaces 220 of the bond pads 208 of the second semiconductor structure 200.

Referring to Fig. 3F, after alignment of the first semiconductor structure 600 and the second semiconductor structure 200 so that the bond pads 608 of the first semiconductor structure 600 are aligned with the pellets conductive metal bond 208 of the second semiconductor structure 200, the first semiconductor structure 600 may be abutted against the second semiconductor structure 200 so that the bonding surfaces 640 (Fig. 3E) of the bond pads 608 of the first semiconductor structure 600 abut directly against the connecting surfaces 220 (Figure 3E) of the bond pads 208 of the second semiconductor structure 200.

With reference to FIG. 3G, the connecting surfaces 640 (FIG. 3E) of the bonding pads 608 of the first semiconductor structure 600 can then be directly connected to the bonding surfaces 220 (FIG. 3E) of the bonding pads 208 of FIG. the second semiconductor structure 200 for forming the bonded semiconductor structure 700 shown in Figure 3G. The connecting surfaces 220 (FIG. 3E) of the bonding pads 208 of the second semiconductor structure 200 can be directly connected to the bonding surfaces 640 (FIG. 3E) of the bonding pads 608 of the first semiconductor structure 600 as described. previously with reference to FIGS. 1F and 1G in relation to the first semiconductor structure 100 and the second semiconductor structure 200. As shown in FIG. 3G, in some embodiments, during the direct bonding of the bonding pads 608 from the first semiconductor structure 600 to the bond pads 208 of the second semiconductor structure 200, one or more elements of the encapsulation layer 618 at the interface between the bond pads 608 and the bond pads 208 may diffuse in the bonding pads 608 and / or the bonding pads 208, so that the encapsulation layer 618 is no longer present in tan t that distinct phase at the interface bound between the bond pads 608 and the bond pads 208. At least a portion of the encapsulation layer 618 can remain on at least a portion of the bond pads 608, as shown in Figure 3G. The presence of at least a portion of the encapsulation layer 618 on the bonding pads 608 as a result of the bonding process may be beneficial for the reasons discussed earlier herein with reference to Figure 1G. As mentioned above, the presence of the doping elements in the bonding pellets 608 may be beneficial in at least one aspect. For example, the doping elements can separate at the boundaries of the grains and the interfaces, including at the interface between the bonding pads 608 and the encapsulation layer 618. The separate doping elements can interfere with the diffusion of the metal atoms (for example, copper) and, thus, can improve the electromigration lifetime of the conductive structures defined by the bonding pads 608 of the first semiconductor structure 600 and the bonding pads 208 of the second structure The presence of these doping elements in the bonding pads 608 can increase the resistivity of the bonding pads 608. Thus, the concentration of the dopants in the bonding pads 608 can be selected so that the resistivity remains at a constant value. acceptable level, but so that the diffusion of metal atoms due to electromigration is reduced. Although embodiments of the invention have been described above with reference to treating the bonding pellets of the first semiconductor structures by providing encapsulation layers thereon and / or doping the pellets of the semiconductor structures. bonding with selected doping elements, it is envisaged that other metallic features of the first semiconductor structures, such as one or more conductive vias 104 and / or one or more conductive tracks 106, may be exposed at the of an active surface and can be treated as discussed above in connection with the bonding pads, and can be directly related to the metal characteristics of a second semiconductor structure in a manner similar to that described in connection with the binding pellets. In addition, it is envisaged that the conductive characteristics of the second semiconductor structure, such as one or more of the bond pads 208, conductive vias 204 and conductive tracks 206, can be treated as described in FIG. present in connection with the bonding pads of the first semiconductor structures by providing encapsulation layers thereon and / or by doping the bonding pads with selected doping elements, in addition to, or as an alternative to processing the conductive characteristics of the first semiconductor structure, before directly bonding said one or more conductive characteristics of the second semiconductor structure to one or more conductive characteristics of a first semiconductor. Additional nonlimiting exemplary embodiments of the invention are described below: Embodiment 1: A method of directly connecting a first semiconductor structure to a second semiconductor structure, comprising the steps of forming an encapsulation layer comprising a metal and silicon at a surface of a first metal feature on the first semiconductor structure, a surface of the encapsulation layer defining a first bonding surface of the first metallic characteristic; and directly bonding a second bonding surface of a second metal feature on the second semiconductor structure to the first bonding surface of the first metal feature on the first semiconductor structure. Embodiment 2: The method of Embodiment 1, further comprising the step of forming the first metallic feature to include copper.

Embodiment 3: The method of Embodiment 1 or Embodiment 2, wherein forming the encapsulating layer comprising a metal and silicon comprises the step of forming a cuprous compound comprising silicon at level of the surface of the first metallic feature. Embodiment 4: The method of any one of embodiments 1 to 3, wherein forming the encapsulation layer comprising a metal and silicon comprises the step of forming a metal silicide. Embodiment 5: The method of any one of embodiments 1 to 3, wherein forming the encapsulation layer comprising a metal and silicon comprises the step of forming an encapsulation layer comprising a metal and silicon and nitrogen. Embodiment 6: The method of any one of embodiments 1 to 5, further comprising the steps of: forming the first bonding surface to have a first size; and forming the second bonding surface to have a second size different from the first size of the first bonding surface.

Embodiment 7: The method of any one of embodiments 1 to 6, further comprising the steps of: forming the first bonding surface to have a first shape; and forming the second bonding surface to have a second shape different from the first shape of the first bonding surface. Embodiment 8: The method of any one of embodiments 1 to 7, wherein the direct bonding of the second bonding surface to the first bonding surface comprises an ultra-low temperature direct bonding process. Embodiment 9: The method of any one of embodiments 1 to 8, wherein the direct connection of the second bonding surface to the first bonding surface comprises a surface assisted bonding process. Embodiment 10: The method of any one of embodiments 1 to 9, wherein the direct connection of the second bonding surface to the first bonding surface comprises the step of abutting the first surface directly bonding against the second bonding surface in an environment at a temperature of less than about four hundred degrees Celsius (400 ° C).

Embodiment 11: The method of Embodiment 10, further comprising the step of applying pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C). Embodiment 12: The method of embodiment 11, wherein applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C) comprises the step of applying pressure between the first bonding surface and the second bonding surface in an environment at a temperature of less than about one hundred degrees Celsius (100 ° C). Embodiment 13: The method of embodiment 12, wherein the application of a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about one hundred degrees Celsius (100 ° C). C) comprises the step of applying pressure between the first bonding surface and the second bonding surface in an environment at about room temperature. Embodiment 14: The method of any one of Embodiments 1 to 13, further comprising the step of doping the first metal feature on the first semiconductor structure with impurities prior to the direct bonding of the second semiconductor structure. bonding surface at the first bonding surface. Embodiment 15: The method of any one of embodiments 1 to 14, further comprising the step of forming an encapsulation layer comprising a metal and silicon at a surface of the second feature on the second semiconductor structure before the direct bonding of the second bonding surface to the first bonding surface, a surface of the encapsulation layer at the surface of the second metal characteristic defining the second bonding surface of the second metallic characteristic.

Embodiment 16: A method of directly connecting a first semiconductor structure to a second semiconductor structure, further comprising the steps of: forming a metal encapsulation layer at a surface of a first metal feature on the first semiconductor structure, a surface of the metal encapsulation layer defining a first bonding surface of the first metal feature; and directly bonding a second bonding surface of a second metal feature on the second semiconductor structure to the first bonding surface of the first metal feature on the first semiconductor structure.

Embodiment 17: The method of Embodiment 16, further comprising the step of forming the metal encapsulation layer to include a metal alloy. Embodiment 18: The method of Embodiment 16 or Embodiment 17, further comprising the step of forming the first metallic feature to include copper. Embodiment 19: The method of any one of Embodiments 16 to 18, further comprising the step of forming the metal encapsulation layer to include CoWP. Embodiment 20: The method of any one of Embodiments 16 to 19, further comprising the step of forming the metal encapsulation layer to have an average thickness of about ten nanometers (10 nm). nm) or less.

Embodiment 21: The method of any one of embodiments 16 to 20, further comprising the steps of: forming the first bonding surface to have a first size; and forming the second bonding surface to have a second size different from the first size of the first bonding surface. Embodiment 22: the method of any of embodiments 16 to 21, further comprising the steps of: forming the first bonding surface to have a first shape; and forming the second bonding surface to have a second shape different from the first shape of the first bonding surface. Embodiment 23: The method of any one of embodiments 16 to 22, wherein the direct connection of the second bonding surface to the first bonding surface comprises an ultra-low temperature direct bonding process.

Embodiment 24: The method of any one of embodiments 16 to 23, wherein the direct connection of the second bonding surface to the first bonding surface comprises a surface-assisted bonding process.

Embodiment 25: The method of any one of embodiments 16 to 24, wherein the direct connection of the second bonding surface to the first bonding surface comprises the step of abutting the first surface binding directly to the second bonding surface in an environment at a temperature of less than about two hundred degrees Celsius (200 ° C).

Embodiment 26: The method of Embodiment 25, further comprising the step of applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C). Embodiment 27: The method of Embodiment 26, wherein applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C) comprises the step of applying pressure between the first bonding surface and the second bonding surface in an environment at a temperature of less than about one hundred degrees Celsius (100 ° C). Embodiment 28: The method of embodiment 27, wherein applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about one hundred degrees Celsius (100 ° C). C) comprises the step of applying pressure between the first bonding surface and the second bonding surface in an environment at about room temperature.

Embodiment 29: The method of any of embodiments 16 to 28, further comprising the step of doping the first metal feature on the first semiconductor structure with impurities prior to directly bonding the second surface connecting to the first bonding surface. Embodiment 30: The method of any one of embodiments 16 to 29, further comprising the step of forming another metallic encapsulation layer at a surface of the second metal feature on the second semiconductor structure before directly bonding the second bonding surface to the first bonding surface, a surface of the other metal encapsulation layer at the surface of the second metal characteristic defining the second bonding surface of the second metallic characteristic.

Embodiment 31: A method of directly connecting a first semiconductor structure to a second semiconductor structure, comprising the steps of: doping a first metal feature on the first semiconductor structure with impurities; and directly bonding a second metal feature on the second semiconductor structure to the first metal feature on the first semiconductor structure.

Embodiment 32: The method of embodiment 31, further comprising the step of selecting impurities to include at least one of aluminum, silver and manganese.

Embodiment 33: the method of Embodiment 31 or Embodiment 32, wherein doping the first metallic feature comprising the steps of: forming a metal seed layer comprising the impurities; and forming the first metal feature on the seed layer and diffusing the impurities of the seed layer into the first metal feature.

Embodiment 34: The method of any one of embodiments 31 to 33, further comprising the step of forming the first metallic feature to include copper.

Embodiment 35: The method of any one of embodiments 31 to 34, further comprising the steps of: forming the first bonding surface to have a first size; and forming the second bonding surface to have a second size different from the first size of the first bonding surface. Embodiment 36: The method of any one of embodiments 31 to 35, further comprising the steps of: forming the first bonding surface to have a first form; and forming the second bonding surface to have a second shape different from the first shape of the first bonding surface. Embodiment 37: The method of any one of embodiments 31-36, wherein the direct bonding of the second bonding surface to the first bonding surface comprises an ultra-low temperature direct bonding process.

Any embodiment of the embodiment link 38: the method of one of embodiments 31 to 37, in direct connection of the second surface of the first bonding surface comprises a surface assisted bonding process. Any mode in which the embodiment link 39: the method of one of embodiments 31 to 38, in direct connection of the second surface of the first bonding surface comprises the step of abutting the first surface of bonding directly against the second bonding surface in an environment at a temperature of less than about two hundred degrees Celsius (200 ° C).

Embodiment 40: The method of Embodiment 39, further comprising the step of applying pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C). Embodiment 41: a bonded semiconductor structure, comprising: a first semiconductor structure including a first metal feature; and a second semiconductor structure comprising a second metal feature, the second metal feature of the second semiconductor structure being directly bonded to the first metal feature of the first semiconductor structure; and impurities at a bonding interface between the first metal feature and the second metal feature. Embodiment 42: The linked semiconductor structure of Embodiment 41, wherein the impurities comprise at least one of aluminum, silver and manganese. Embodiment 43: The linked semiconductor structure of Embodiment 41 or Embodiment 42, wherein the impurities comprise at least one of silicon and nitrogen. Embodiment 44: The linked semiconductor structure of any one of embodiments 41 to 43, wherein the impurities 10 comprise at least one of cobalt, tungsten and phosphorus. Embodiment 45: The bonded semiconductor structure of any one of embodiments 41 to 44, wherein at least one of the first metallic characteristic and the second metallic characteristic comprises copper. Embodiment 46: The bonded semiconductor structure of any one of embodiments 41 to 45, wherein: the first metal feature has a first cross section in a plane parallel to a bonded interface between the first metal feature and the second metallic characteristic; and the second metal feature has a second cross section in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second cross section being different from the first cross section. Embodiment 47: The bonded semiconductor structure of any one of embodiments 41 to 46, wherein: the first metal feature has a first sectional shape in a plane parallel to a bonded interface between the first feature metallic and the second metallic characteristic; and the second metal feature has a second sectional shape in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second sectional shape being different from the first sectional shape. Embodiment 48: A bonded semiconductor structure, comprising: a first semiconductor structure comprising a first metallic feature including a first major surface; a second semiconductor structure comprising a second metal feature at least partially surrounded by a dielectric material, the second metal feature of the second semiconductor structure having a second major surface directly bonded to a portion of the first major surface of the first metallic characteristic of the first semiconductor structure; and an encapsulating material disposed directly between a surface of the dielectric material and another portion of the first major surface of the first metal characteristic of the first semiconductor structure.

Embodiment 49: The linked semiconductor structure of Embodiment 48, wherein the encapsulating material comprises a dielectric material. Embodiment 50: The linked semiconductor structure of Embodiment 49, wherein the encapsulating material comprises at least one of CuSiN, SiC and SiN. Embodiment 51: The linked semiconductor structure of Embodiment 48, wherein the encapsulating material comprises a conductive material. Embodiment 52: The linked semiconductor structure of Embodiment 51, wherein the encapsulating material comprises CoWP. Embodiment 53: The bonded semiconductor structure of any one of embodiments 48 to 52, wherein at least one of the first metallic characteristic and the second metallic characteristic comprises copper. Embodiment 54: The bonded semiconductor structure of any of embodiments 48 to 53, wherein: the first metal feature has a first cross section in a plane parallel to a bonded interface between the first metal feature and the second metallic characteristic; and the second metal feature has a second cross section in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second cross section being different from the first cross section. Embodiment 55: The bonded semiconductor structure of any one of Embodiments 48 to 54, wherein: the first metal feature has a first sectional shape in a plane parallel to a bonded interface between the first metallic feature and the second metallic characteristic; and the second metal feature has a second sectional shape in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second sectional shape being different from the first sectional shape.

Claims (34)

REVENDICATIONS1. Direct binding method of a first structure CLAIMS1. A method of directly connecting a first semiconductor structure to a second semiconductor structure, comprising the steps of: forming an encapsulation layer comprising a metal and silicon at a surface of a first metallic feature on the first semiconductor structure, a surface of the encapsulation layer defining a first bonding surface of the first metal characteristic; and directly bonding a second bonding surface of a second metal feature on the second semiconductor structure to the first bonding surface of the first metal feature on the first semiconductor structure. The method of claim 1, further comprising the step of forming the first metallic feature to include copper. The method of claim 2, wherein forming the encapsulation layer comprising a metal and silicon comprises the step of forming a cuprous compound comprising silicon at the surface of the first metallic feature. The method of claim 1, wherein forming the encapsulating layer comprising a metal and silicon comprises the step of forming a metal silicide. The method of claim 1, wherein forming the encapsulating layer comprising a metal and silicon comprises the step of forming an encapsulation layer comprising a metal and silicon and nitrogen. The method of claim 1, further comprising the steps of: forming the first bonding surface to a first size; and forming the second bonding surface to have a second size different from the first size of the first bonding surface. The method of claim 1, further comprising the steps of: forming the first bonding surface to have a first shape; and forming the second bonding surface to have a second shape different from the first shape of the first bonding surface. The method of claim 1, wherein the direct bonding of the second bonding surface to the first bonding surface comprises an ultra-low temperature direct bonding process. The method of claim 1, wherein the direct connection of the second bonding surface to the first bonding surface comprises a surface bonding process. The method of claim 1, wherein the direct bonding of the second bonding surface to the first bonding surface comprises the step of, 52, abutting the first bonding surface directly against the second bonding surface. binding in an environment at a temperature below about two hundred degrees Celsius (200 ° C). The method of claim 10, further comprising the step of applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C) . The method of claim 11, wherein applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about two hundred degrees Celsius (200 ° C) comprises a step of applying pressure between the first bonding surface and the second bonding surface in an environment at a temperature of less than about one hundred degrees Celsius (100 ° C). The method of claim 12, wherein applying a pressure between the first bonding surface and the second bonding surface in the environment at a temperature of less than about one hundred degrees Celsius (100 ° C) comprises the a step of applying pressure between the first bonding surface and the second bonding surface in an environment at about room temperature. The method of claim 1, further comprising the step of doping the first metal feature on the first semiconductor structure with impurities prior to direct bonding of the second bonding surface to the first bonding surface. The method of claim 1, further comprising the step of forming an encapsulation layer comprising a metal and silicon at a surface of the second metal feature on the second semiconductor structure prior to the direct link. from the second bonding surface to the first bonding surface, a surface of the encapsulation layer at the surface of the second metal characteristic defining the second bonding surface of the second metal characteristic. The method of claim 1, further comprising the step of forming the metal encapsulation layer to include CoWP. The method of claim 1, further comprising the step of forming the metal encapsulation layer to have an average thickness of about ten nanometers (10 nm) or less. The method of claim 14, further comprising the step of selecting the impurities to include at least one of aluminum, silver and manganese. 2969814 54, 19. The method of claim 14, wherein the doping of the first metallic feature comprises the steps of: forming a metal seed layer comprising the impurities; and forming the first metal feature on the seed layer and diffusing the impurities of the seed layer into the first metal feature. 10 A bonded semiconductor structure comprising: a first metallic feature; and a second semiconductor structure comprising a second metal feature, the second metal feature of the second semiconductor structure being directly bonded to the first metal feature of the first semiconductor structure; and impurities at a bonding interface 20 between the first metal feature and the second metal feature. The bonded semiconductor structure of claim 20, wherein the impurities comprise at least one of aluminum, silver and manganese. The bonded semiconductor structure of claim 20, wherein the impurities comprise at least one of silicon and nitrogen. The bonded semiconductor structure of claim 20, wherein the impurities comprise at least one of cobalt, tungsten and phosphorus. The bonded semiconductor structure of claim 20, wherein at least one of the first metallic characteristic and the second metallic characteristic comprises copper. The bonded semiconductor structure of claim 20, wherein: the first metal feature has a first cross section in a plane parallel to an interface bonded between the first metal feature and the second metal feature; and the second metal feature has a second cross section in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second cross section being different from the first cross section. The bonded semiconductor structure of claim 20, wherein: the first metal feature has a first sectional shape in a plane parallel to a bonded interface between the first metal feature and the second metal feature; and the second metal feature has a second sectional shape in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second sectional shape being different from the first sectional shape. A bonded semiconductor structure, comprising: 2969814, 56 a first semiconductor structure comprising a first metallic feature including a first major surface; a second semiconductor structure comprising a second metal feature at least partially surrounded by a dielectric material, the second metal feature of the second semiconductor structure having a second major surface directly bonded to a portion of the first major surface of the first metallic characteristic of the first semiconductor structure; and encapsulating material disposed directly between a surface of the dielectric material and another portion of the first major surface of the first metal characteristic of the first semiconductor structure. The bonded semiconductor structure of claim 27, wherein the encapsulating material comprises a dielectric material. The bonded semiconductor structure of claim 28, wherein the encapsulating material comprises at least one of CuSiN, SiC and SiN. The bonded semiconductor structure of claim 27, wherein the encapsulating material comprises a conductive material. The bonded semiconductor structure of claim 30, wherein the encapsulating material comprises CoWP 2969814, 57 The bonded semiconductor structure of claim 27, wherein at least one of the first metallic characteristic and the second metallic characteristic comprises copper. 5 33. Semiconductor structure. Binder according to claim 27, wherein: the first metal feature has a first cross section in a plane parallel to an interface bonded between the first metal feature and the second metal feature; and the second metal feature has a second cross section in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second cross section being different from the first cross section. 20 The bonded semiconductor structure of claim 27, wherein: the first metal feature has a first sectional shape in a plane parallel to a bonded interface between the first metal feature and the second metal feature and the second metal feature. a second sectional shape in a plane parallel to the bonded interface between the first metal feature and the second metal feature, the second sectional shape being different from the first sectional shape.