FR2946815B1 - Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat - Google Patents

Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat

Info

Publication number
FR2946815B1
FR2946815B1 FR0902872A FR0902872A FR2946815B1 FR 2946815 B1 FR2946815 B1 FR 2946815B1 FR 0902872 A FR0902872 A FR 0902872A FR 0902872 A FR0902872 A FR 0902872A FR 2946815 B1 FR2946815 B1 FR 2946815B1
Authority
FR
France
Prior art keywords
confirmation
acquiring
logic signals
state validity
validity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0902872A
Other languages
English (en)
Other versions
FR2946815A1 (fr
Inventor
Patrick Dervin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thales SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales SA filed Critical Thales SA
Priority to FR0902872A priority Critical patent/FR2946815B1/fr
Priority to US12/815,378 priority patent/US8095843B2/en
Publication of FR2946815A1 publication Critical patent/FR2946815A1/fr
Application granted granted Critical
Publication of FR2946815B1 publication Critical patent/FR2946815B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
FR0902872A 2009-06-12 2009-06-12 Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat Active FR2946815B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0902872A FR2946815B1 (fr) 2009-06-12 2009-06-12 Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat
US12/815,378 US8095843B2 (en) 2009-06-12 2010-06-14 Method of acquiring a plurality of logic signals, with confirmation of state validity

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0902872A FR2946815B1 (fr) 2009-06-12 2009-06-12 Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat

Publications (2)

Publication Number Publication Date
FR2946815A1 FR2946815A1 (fr) 2010-12-17
FR2946815B1 true FR2946815B1 (fr) 2011-06-17

Family

ID=41682299

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0902872A Active FR2946815B1 (fr) 2009-06-12 2009-06-12 Procede d'acquisition d'une pluralite de signaux logiques, avec confirmation de validite d'etat

Country Status (2)

Country Link
US (1) US8095843B2 (fr)
FR (1) FR2946815B1 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57101955A (en) * 1980-12-16 1982-06-24 Nec Corp Status history storage system
JPS59173848A (ja) * 1983-03-23 1984-10-02 Fuji Electric Co Ltd トレ−ス方式
US5905858A (en) * 1996-11-01 1999-05-18 Micron Electronics, Inc. System for method memory error handling
DE19919974A1 (de) * 1999-04-30 2000-11-02 Univ Dresden Tech Verfahren zur Ereignissteuerung von Bewegungsabläufen
US8650470B2 (en) * 2003-03-20 2014-02-11 Arm Limited Error recovery within integrated circuit
KR100905712B1 (ko) * 2006-09-29 2009-07-01 삼성전자주식회사 에러 정정 코드를 이용한 병렬 비트 테스트 장치
FR2919401B1 (fr) 2007-07-24 2016-01-15 Thales Sa Procede de test des chemins de donnees dans un circuit electronique

Also Published As

Publication number Publication date
US8095843B2 (en) 2012-01-10
US20100315117A1 (en) 2010-12-16
FR2946815A1 (fr) 2010-12-17

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