FR2911414B1 - Dispositif et procede pour lire un mot de donnees et dispositif et procede pour memoriser un bloc de donnees - Google Patents

Dispositif et procede pour lire un mot de donnees et dispositif et procede pour memoriser un bloc de donnees

Info

Publication number
FR2911414B1
FR2911414B1 FR0700400A FR0700400A FR2911414B1 FR 2911414 B1 FR2911414 B1 FR 2911414B1 FR 0700400 A FR0700400 A FR 0700400A FR 0700400 A FR0700400 A FR 0700400A FR 2911414 B1 FR2911414 B1 FR 2911414B1
Authority
FR
France
Prior art keywords
reading
storing
data
data block
data word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0700400A
Other languages
English (en)
Other versions
FR2911414A1 (fr
Inventor
Steffen Sonnekalb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of FR2911414A1 publication Critical patent/FR2911414A1/fr
Application granted granted Critical
Publication of FR2911414B1 publication Critical patent/FR2911414B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H03M13/293—Decoding strategies with erasure setting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2909—Product codes
    • H03M13/2915—Product codes with an error detection code in one dimension
FR0700400A 2006-01-23 2007-01-22 Dispositif et procede pour lire un mot de donnees et dispositif et procede pour memoriser un bloc de donnees Expired - Fee Related FR2911414B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102006003146.6A DE102006003146B4 (de) 2006-01-23 2006-01-23 Vorrichtung und Verfahren zum Auslesen eines Datenwortes und Vorrichtung und Verfahren zum Speichern eines Datenblocks

Publications (2)

Publication Number Publication Date
FR2911414A1 FR2911414A1 (fr) 2008-07-18
FR2911414B1 true FR2911414B1 (fr) 2013-03-29

Family

ID=38268071

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0700400A Expired - Fee Related FR2911414B1 (fr) 2006-01-23 2007-01-22 Dispositif et procede pour lire un mot de donnees et dispositif et procede pour memoriser un bloc de donnees

Country Status (4)

Country Link
US (1) US7937639B2 (fr)
KR (1) KR100870196B1 (fr)
DE (1) DE102006003146B4 (fr)
FR (1) FR2911414B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20090014828A (ko) * 2007-08-07 2009-02-11 삼성전자주식회사 에러 정정 코드를 암호화하는 플래시 메모리 시스템 및플래시 메모리 시스템의 암호화 방법
US8832518B2 (en) * 2008-02-21 2014-09-09 Ramot At Tel Aviv University Ltd. Method and device for multi phase error-correction
US8458562B1 (en) 2008-12-30 2013-06-04 Micron Technology, Inc. Secondary memory element for non-volatile memory
US8504893B1 (en) * 2010-09-30 2013-08-06 Micron Technology, Inc. Error detection or correction of a portion of a codeword in a memory device
US8533557B2 (en) 2011-01-28 2013-09-10 Infineon Technologies Ag Device and method for error correction and protection against data corruption
DE102012020442B4 (de) * 2012-10-18 2020-03-05 Robert Bosch Gmbh Verfahren zum Überprüfen von Daten mittels wenigstens zweier Prüfsummen
US20140215174A1 (en) 2013-01-25 2014-07-31 Infineon Technologies Ag Accessing Memory with Security Functionality
US10930650B2 (en) * 2018-06-28 2021-02-23 Stmicroelectronics International N.V. Latch-up immunization techniques for integrated circuits
US11475170B2 (en) 2019-05-28 2022-10-18 Nuvoton Technology Corporation System and method for correction of memory errors
US11342044B2 (en) 2019-05-28 2022-05-24 Nuvoton Technology Corporation System and method for prioritization of bit error correction attempts
US11694761B2 (en) * 2021-09-17 2023-07-04 Nxp B.V. Method to increase the usable word width of a memory providing an error correction scheme

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4236247A (en) * 1979-01-15 1980-11-25 Organisation Europeene De Recherches Spatiales Apparatus for correcting multiple errors in data words read from a memory
US4319357A (en) * 1979-12-14 1982-03-09 International Business Machines Corp. Double error correction using single error correcting code
US4561095A (en) * 1982-07-19 1985-12-24 Fairchild Camera & Instrument Corporation High-speed error correcting random access memory system
FR2659460B1 (fr) * 1990-03-08 1992-05-22 Bull Sa Sous-systeme peripherique de memoire de masse.
US5164944A (en) 1990-06-08 1992-11-17 Unisys Corporation Method and apparatus for effecting multiple error correction in a computer memory
KR970071492A (ko) * 1996-04-15 1997-11-07 김광호 씨디-롬 드라이브 테스트 방법
JP3527873B2 (ja) * 1999-09-03 2004-05-17 松下電器産業株式会社 誤り訂正装置
DE19983990T1 (de) * 1999-11-25 2002-12-19 Fujitsu Ltd Verfahren zur Leseverarbeitung eines Speichermediums, Speichervorrichtung, Datenreproduktionsverfahren, Datenreproduktionssystem und Speichermedium dafür
US7231585B2 (en) * 2002-12-11 2007-06-12 Nvidia Corporation Error correction for flash memory

Also Published As

Publication number Publication date
KR20070077466A (ko) 2007-07-26
DE102006003146A1 (de) 2007-08-02
FR2911414A1 (fr) 2008-07-18
DE102006003146B4 (de) 2016-05-12
KR100870196B1 (ko) 2008-11-24
US7937639B2 (en) 2011-05-03
US20070174753A1 (en) 2007-07-26

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