FR2881574A1 - Interconnection network formation method for integrated circuit, involves performing deposit not conforming to insulating layer above structure, formed by etching another insulating layer, to form air gaps between conducting tracks - Google Patents

Abstract

The method involves etching an insulating layer (50) to form trenches between conducting tracks (51-53) by using sacrificial layers as etching mask such that walls of the tracks remain covered with fine portions of the layer (50). The sacrificial layers are eliminated to uncover barrier portions. A deposit not conforming to another insulating layer is carried out above previously formed structure to form air gaps between the tracks. An independent claim is also included for an equipment intended for a method of forming an interconnection network.

Description

METHOD FOR FORMING AN INTERCONNECTION NETWORK COMPRISING

  FIELD OF THE INVENTION The present invention relates to a method of forming an integrated circuit of an interconnection network comprising air pockets known as "Air Gap".

  DESCRIPTION OF THE PRIOR ART FIGS. 1A to 1D are sectional views of structures obtained after successive steps of a known formation process of an interconnection network comprising air pockets.

  In an initial step, shown in FIG. 1A, trenches are formed in an insulating layer 1. A conformal deposition is then carried out with a thin protective layer 2, for example tantalum nitride, and then the trenches are filled with conductive material 3 such as copper to form conductive tracks 4, 5, 6. Next, the copper and tantalum nitride are mechanochemically polished so as to expose the insulating layer 1 between the tracks 4, 5, 6. then forms, by selective deposition, metal portions 7, 8, 9 at the surface of the tracks 4, 5, 6. The thin protective layer 2 and the metal portions 7, 8, 9 are intended to prevent copper from diffusing into the insulating layer 1 to the rest of the circuit and electromigration phenomena of the track occur on the surface thereof.

  In a next step, illustrated in FIG. 1B, the insulating layer 1 is etched so as to form trenches T 5 between the conductive tracks 4, 5, 6.

  In a next step, illustrated in FIG. 1C, a non-conformal deposition of an insulating layer 10 is carried out on the previously obtained structure. Since the deposit is not in conformity, air pockets P are formed between tracks 4, 5, 6. The air pockets P and tracks 4, 5, 6 are nevertheless separated by a thin insulating layer covering the vertical walls of the tracks 4, 5, 6. The insulating layers 1 and 10 are formed in this example of the same material such as silicon oxide.

  In a next step, illustrated in FIG. 1D, the insulating layer 10 is etched to form openings V intended to house conductive vias.

  Each level of tracks and vias is obtained by a photolithography method using a mask for the definition of tracks or vias. The mask defining a level of tracks and the mask defining a level of vias placed immediately above can be slightly misaligned. As can be seen in FIG. 1D, the opening of via V can be shifted with respect to the track 5 placed below so that, during the etching of the via aperture, the air pocket placed next to the Track 5 was "breakthrough". Therefore, when filling the via V opening with a conductive material, the air pocket will also be filled with a conductive material. This can cause problems of reliability of the integrated circuit.

  A known method of manufacturing an interconnection network comprising air pockets and to avoid the problem of "drilling" described above is as follows.

  In an initial step, illustrated in FIG. 2A, trenches are formed in an insulating layer in which conductive tracks 21, 22, 23 are formed. Metal portions 24, 25, 26 are then formed above the tracks. 21, 22, 23 according to a selective deposition process.

  In a next step, illustrated in FIG. 2B, the insulating layer 20 is etched so as to form trenches T between the tracks 21, 22, 23. As previously, the etching time is provided so as to obtain a trench depth substantially equal to the height of the tracks 21, 22, 23. The etching process is provided as anisotropic as possible so as to keep fine portions 30, 31 of the insulating layer 1 on the vertical walls of the tracks 21, 22, 23 under the lateral extensions of the metal portions 24, 25, 26.

  In a next step, illustrated in FIG. 2C, the metal portions 24, 25, 26 are mechanochemically polished so as to reduce their thickness.

  In a next step, illustrated in FIG. 2D, a non-conformal deposition of an insulating layer 35 on the previously obtained structure is carried out. Pairs of air P between the tracks 21, 22, 23 are squeaked previously. During this deposition of an insulating material, a thin insulating layer is formed on the bottom of the trenches and against the thin insulating portions 30. 31 already covering the walls of the trenches T. At the upper surface of the metal tracks 21, 22, 23, the lateral thickness of the insulating layer covering the wall of each track is greater than in the case of the previously described method. As a result, when etching vias V openings above the metal tracks 21, 22, 23, even if there is a large difference between the level of tracks and vias definition masks, the pockets of air P are not pierced.

  A disadvantage of this method is that the lateral extensions of the metal portions 24, 25, 26 increase the parasitic coupling capacitances between the conductive tracks, even if the polishing of the metal portions makes it possible to limit this increase in capacity.

  In addition, in the two processes previously described, the metal portions covering the conductive tracks are used as a mask for protecting the tracks during the etching of the trenches T. This adversely affects the integrity of the metal portions that fulfill their role of portions less well. "barrier" for avoiding electromigration and diffusion phenomena tracks 21, 22, 23.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming an interconnection network comprising air pockets between the tracks which makes it possible to avoid problems of "piercing" the air pockets. when burning via apertures.

  Another object of the present invention is to provide a method of forming such an interconnection network which makes it possible to preserve the integrity of the "barrier" portions placed above the conductive tracks of the interconnection network.

  Another object of the present invention is to provide a method of forming such an interconnection network having parasitic coupling capabilities between the lowest possible conductive paths.

  To achieve this object, the present invention provides a method of forming an interconnection network consisting of a stack of insulating layers in which are alternately conductive tracks and conductive vias, comprising the following steps: forming conductive tracks in a first insulating layer; forming sacrificial portions covering the conductive tracks and projecting laterally beyond them for a predefined distance; etching the first insulating layer to form trenches between the metal tracks, using as said etching mask said sacrificial layers, whereby the walls of the conductive tracks remain covered with thin portions of said first insulating layer; eliminate the sacrificial portions; and improperly depositing a second insulating layer above the previously formed structure, whereby air pockets are formed between the tracks.

  According to a variant of the process previously described, the method further comprises, prior to the deposition of the sacrificial portions, a step of forming barrier portions above the conductive tracks.

  According to a variant of the method previously described, the method further comprises following the elimination of sacrificial portions, a step of forming barrier portions above the conductive tracks.

  According to a variant of the process previously described, the method further comprises, after the formation of barrier portions, the formation of stop portions covering the barrier portions. In addition, the sacrificial portions are etched during etching of the first insulating layer to form trenches, the etching step continuing until the stop portions are discovered.

  According to a variant of the method previously described, during the nonconform deposition of said second insulating layer, thin insulating layers are formed in the trenches against said thin portions of said first insulating layer covering said conductive tracks, and said predefined distance is greater than or equal to the difference between the maximum possible offset between the definition mask of said conductive tracks and the definition mask of conductive vias placed above the tracks, and the thickness of said thin insulating layers.

  According to a variant of the method previously described, said barrier, sacrificial and / or stop portions are formed by selective deposition methods.

  According to a variant of the method described above, the conductive tracks comprise copper.

  According to a variant of the process previously described, said barrier portions consist of a metal material such as cobalttungsten-phosphorus.

  According to a variant of the method described above, the conductive tracks have a width substantially equal to 100 nm and a minimum spacing equal to 100 nm, and said predefined distance is substantially equal to 25 nm.

  The present invention also provides equipment for carrying out the previously described method. BRIEF DESCRIPTION OF THE DRAWINGS These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments in a non-limitative manner with reference to the accompanying figures, in which: FIGS. 1A to 1D are sectional views, previously described, of structures obtained at the end of successive steps of a known method of forming an interconnection network comprising air pockets; FIGS. 2A to 2D are sectional views, previously described, of structures obtained at the end of successive steps of another known method of forming an interconnection network comprising air pockets; FIGS. 3A to 3E are sectional views of structures obtained at the end of successive steps of a method of manufacturing an interconnection network according to an embodiment of the present invention; FIGS. 4A to 4E are sectional views of structures obtained at the end of successive steps of a method of manufacturing an interconnection network according to another embodiment of the present invention; and FIGS. 5A to 5E are sectional views of structure obtained at the end of successive steps of a method of manufacturing an interconnection network according to another embodiment of the method of the present invention. . DETAILED DESCRIPTION For the sake of clarity, the same elements have been designated by the same references in the various figures and, moreover, as is customary in the representation of the integrated circuits, the various figures are not drawn to scale.

  The method of the present invention aims to form an interconnection network of an integrated circuit. This network of interconnections comprises a stack of insulating layers in which conductor tracks and conducting vias are alternately placed. The present invention is more particularly concerned with the method of forming an interconnection network known as the "damascene" process of forming openings in an insulating layer and filling them with a conductive material so as to form conductive vias and conductive tracks. Specifically, generally forms a first series of "deep" openings for receiving conductive vias and a second series of "thin" openings for receiving conductive tracks. In the remainder of the description, reference will be made to the finalization of a level of conductive tracks and to the formation of the insulating layer placed above this level of conductive tracks, this insulating layer being intended to house a level of vias. and a higher level of tracks.

  An embodiment of the present invention is described below in relation to FIGS. 3A to 3E.

  In a preliminary step, illustrated in FIG. 3A, conducting tracks 51, 52, 53 are formed in the upper part of an insulating layer 50, which can be obtained according to the following method. Trenches are etched on the surface of the insulating layer 50. A conformal deposition of a thin conductive layer, for example tantalum nitride, is carried out against the walls and the bottom of the trenches thus formed. The trenches are filled with a conductive material such as copper, and the conductive material and the thin conductive layer are mechanochemically polished so as to expose the insulating layer 50.

  In this example, each conductive track consists of a conductive portion, for example copper, covered with a thin conductive layer, for example tantalum nitride. The thin conductive layer is intended to prevent diffusion phenomena and electromigration of the conductive portion. It will be noted that this thin conductive protective layer may be replaced by a thin layer of another material, for example an insulating material, which is capable of avoiding diffusion and electromigration phenomena. In the case where the thin protective layer is conductive, it is considered in the present description that it is part of the conductive track.

  Then, "barrier" portions 54, 55, 56 are formed by selective deposition above the conductive tracks 51, 52, 53. The barrier portions may consist of various materials deposited by various selective deposition methods. For example, tungsten barrier portions W may be formed by a vapor deposition process, portions of CuSiN by a plasma assisted copper silicide process, Cobalt-tungsten-phosphorus CoWP portions by a self-dipping process. -catalytic or portions of polymers according to a grafting process described below.

  The plasma-assisted copper siliciding process consists, for example, in placing the structure obtained before formation of the barrier layers in an enclosure containing SiH.sub.4 silane in order to diffuse silicon in the tracks 51, 52, 53 constituted in this case of copper. SiC'r copper silicide is formed on the surface of the tracks. This structure is then placed in an NH 3 ammonia plasma so as to transform the copper silicide layer into a CUSiN layer which is more stable over time. Note that in the case of the formation of a CuSiN layer, this layer is not formed above the tracks as shown in Figure 3A but in the upper part of the tracks.

  The self-catalytic quenching process of CoWP, or NiMoP or CoWB, consists in placing the upper surface of the structure obtained before formation of the barrier layers in a bath containing precursors of cobalt, tungsten and phosphorus. In order to facilitate the formation of the CoWP on the tracks 51, 52, 53, it will be possible beforehand to form a bonding layer on the tracks, for example an atomic layer of palladium, by placing the structure in contact with precursors of palladium, by example in a chemical bath.

  The method for grafting polymers consists in forming a thin layer of "hooking" polymers on the tracks 51, 52, 53 according to a selective deposition process such as a dipping in a bath containing molecules capable of reacting only with the tracks and not with the insulating layer 50, then to grow a layer of polymers or organic molecules on the bonding layer. Note that it is possible to change the nature of the polymer layer, for example to make it more conductive, by diffusing elements in this layer and possibly reacting with it.

  In the next step, illustrated in FIG. 3B, a selective deposition of sacrificial portions 57, 58, 59 over each of the barrier portions 54, 55, 56 is performed. The sacrificial portions 57, 58, 59 cover the barrier portions. and extend slightly laterally The lateral extension distance of the sacrificial portions is determined according to several parameters described below.

  As for the barrier portions, the sacrificial portions may consist of various materials. The sacrificial portions must be selectively removable relative to the barrier portions, without degrading them. CoWP can be easily removed by soaking. Similarly, a germanium-containing polymer can be easily removed by placing this polymer in a heated enclosure containing oxygen. Examples of barrier portion / sacrificial portion pairs that can be used are W / polymer, CuSiN / CoWP and CoWP / polymer.

  In a next step, illustrated in FIG. 3C, the insulating layer 50 is etched so as to form trenches T between the conductive tracks 51, 52, 53. The sacrificial portions 57, 58, 59 are used as an etching mask. that is, areas of the insulating layer not covered by a sacrificial portion are etched. The etching process is provided as anisotropic as possible so as to keep fine portions 60, 61 of the insulating layer 50 against the walls of the tracks 51, 52, 53. The etching time is in this example provided so that the depth of the trenches is substantially identical to the height of the tracks 51, 52, 53. It should be noted, however, that the depth of the trenches may be lower or greater depending on the type of damascene process used for the production of the network. interconnections. In addition, it will be understood that according to the etching method used, the sacrificial portions 57, 58, 59 may be partially etched as can be seen in FIG. 3C.

  In a next step, illustrated in FIG. 3D, the sacrificial portions 57, 58, 59 are eliminated so as to discover the barrier portions 54, 55, 56.

  In a next step, illustrated in FIG. 3E, a non-conformal deposition of an insulating layer 65 is performed above the previously obtained structure. A thin insulating layer 66, 67 is then deposited in each of the trenches T and in particular against the thin insulating portions 60, 61 covering the walls of the tracks 51, 52, 53. Air pockets P are closed between the conductive tracks 51, 52, 53.

  The presence against the walls of the tracks 51, 52, 53 of thin insulating portions 60, 61 and thin insulating layers 66, 67 must ultimately provide a thickness of insulating material against the walls of the conductive tracks 51, 52, 53 which is sufficient to prevent drilling of the air pockets P during the etching of vias apertures V above the tracks 51, 52, 53. The lateral extension distance L of the sacrificial portions 57, 58, 59 is therefore provided greater than or equal to the difference between on the one hand the maximum possible offset d between the defining mask tracks 51, 52, 53 and the definition mask vias placed above these tracks, and secondly the thickness e of the thin insulating layers 66, 67 (L (de)). As an indication, and not limiting, the dimensions 15 of the elements of the structure as shown in Figure 3E are as follows: thickness of the tracks 51, 52, 53: 220 nm; gap between the masks: => 25 nm; thickness e of the thin insulating layers 66, 67: 0-5 20 nm; distance of lateral extension of the sacrificial portions 57, 58, 50: between 20 and 25 nm.

  minimum width of the tracks 51, 52, 53: 100 nm; minimum spacing of the tracks 51, 52, 53: 100 nm.

  An advantage of the method according to the present invention is that it makes it possible to avoid piercing the air pockets P of the interconnection network.

  Another advantage of the method according to the present invention is that it makes it possible to obtain an interconnection network having low coupling capacitors between two neighboring tracks.

  In the method described above, the sacrificial portions 57, 58, 59 protect the barrier portions 54, 55, 56 during the etching of the trenches T which can be relatively long and "aggressive". Without the presence of such sacrificial portions, this step of etching the trenches T would lead to deteriorations in the structure of the barrier portions 54, 55, 56 and possibly to their partial etching.

  An advantage of the above described process is that it allows to preserve the integrity of the barrier portions.

  However, when the sacrificial portions 57, 58, 59 and the barrier portions 54, 55, 56 are made of materials which can not be easily etched selectively relative to one another, the elimination of the sacrificial portions may partially deteriorate. the barrier portions. In order to overcome this drawback, a variant of the method previously described can be implemented. This variant is described below in relation to FIGS. 4A to 4E.

  In a prior step, illustrated in FIG. 4A, in the upper part of an insulating layer 70 conductive tracks 71, 72, 73 and barrier portions 74, 75, 76 are formed above each of the tracks 71, 72, 73.

  In a next step, illustrated in FIG. 4B, a selective deposition of "stop" portions 80, 81, 82 is carried out above each of the barrier portions 74, 75, 76. The stop portions 74, 75 , 76 cover the barrier portions 74, 75, 76 so that a portion of the stop portions is in contact with the insulating layer 70 on the edge of the barrier portions 74, 75, 76. Selective portion deposition is then carried out. sacrificial portions 83, 84, 85 above the stop portions 80, 81, 82. The sacrificial portions 83, 84, 85 cover the stop portions 80, 81, 82, so that a portion of the sacrificial portions is in contact with the insulating layer on the edge of the stop portions 80, 81, 82. The stop portions 80, 81, 82 consist of a selectively etchable material with respect to the barrier portions 74, 75, 76 without damaging them. The stop portions 80, 81, 82 consist, for example, of CoWP or of a germanium-based material such as germanium oxide or a polymer comprising germanium, and the sacrificial portions 83, 84, 85 consisting of of a polymeric material. Examples of three barrier portions / stop portion / sacrificial portion that may be used are: CuSiN / CoWP / polymer, CoWP / polymer / polymer2 or W / polymer / polymer2.

  In the next step, illustrated in FIG. 4C, the insulating layer 70 is etched so as to form trenches T between the conductive tracks 71, 72, 73 by using the sacrificial portions as an etching mask. The etching is provided as anisotropic as possible so as to keep fine portions 90, 91 of the insulating layer 70 against the vertical walls of the tracks 71, 72, 73. In this example of implementation of the present invention, during the engraving trenches, the sacrificial portions 83, 84, 85 are gradually engraved.

  The thickness of the sacrificial portions 83, 84, 85 is provided so that the etching time of the sacrificial portions substantially corresponds to the etching time required to obtain trenches T having a depth substantially equal to the height of the tracks 71, 72, 73 Thus, it is advantageous to stop the etching of the trenches when it is detected that the stop portions 80, 81, 82 are discovered.

  In the next step, illustrated in FIG. 4D, the stop portions 80, 81, 82 are eliminated. The upper surfaces of the tracks 71, 72, 73 are then only covered with the barrier portions 74, 75, 76. The vertical walls tracks 71, 72, 73 are covered with the thin insulating portions 90, 91.

  In the next step, illustrated in FIG. 4E, a nonconforming deposition of an insulating layer 95 is carried out above the previously obtained structure. A thin insulating layer 96, 97 is deposited in each of the trenches T and in particular against the fine portions; insulating 90, 91. Air pockets P are formed between the tracks 71, 72, 73.

  In this embodiment, the cumulative extension distance L of the stop portions and the sacrificial portions with respect to the upper surface of the conductive tracks 70 is defined as above according to the maximum offset d between the track definition mask. 71, 72, 73 and the definition mask vias placed above and according to the thickness e of the thin insulating layers 96, 97: L> _ (de). The thickness of the thin insulating layers 96, 97 is itself a function of the type of non-conformal deposition performed and the insulating material deposited to form the insulating layer 95.

  An advantage of the method described above is that it preserves the integrity of the barrier portions and in particular their ability to avoid diffusion phenomena and electromigration tracks.

  Figs. 5A-5E illustrate another embodiment of the present invention.

  In a preliminary step, illustrated in FIG. 5A, as in the upper part of an insulating layer 100, conductive tracks 101, 102, 103 are formed.

  In this embodiment, sacrificial portions 105, 106, 107 are formed by selective deposition directly on the tracks 101, 102, 103. The sacrificial portions 105, 106, 107 cover the pisses 101, 102, 103 and extend slightly. laterally beyond these tracks. The sacrificial portions must be removable without damaging the tracks 101, 102, 103. The sacrificial portions consist for example of tungsten W, CoWP or polymers.

  In a next step, illustrated in FIG. 5B, the insulating layer 100 is etched so as to form trenches T between the tracks 101, 102, 103. Etching is also provided as much anisotropic as possible so as to preserve fine portions 110 , 111 of the insulating layer 100 against the walls of the tracks 101, 102, 103.

  In the next step, illustrated in FIG. 5C, the sacrificial portions 105, 106, 107 are eliminated.

  In a next step, illustrated in FIG. 5D, barrier portions 120, 121, 122 are formed by selective deposition over the conductive tracks 101, 102, 103. The barrier portions may consist of various materials obtained according to various methods. previously described in connection with FIG. 3A.

  In a next step, illustrated in FIG. 5E, a non-conformal deposition of an insulating layer 130 is carried out above the previously obtained structure. As before, air pockets P are obtained between the tracks 101, 102, 103 and thin insulating layers 131, 132 in each of the trenches and in particular against the insulating portions 110, 111.

  Of course, the present invention is susceptible to various variations and modifications that will be apparent to those skilled in the art. In particular, those skilled in the art can provide other ways to cover the conductive tracks to keep thin insulating portions against the walls of these tracks during the etching of the trenches T. In addition, it will be noted that the portions barrier placed above the conductive tracks may be made of various types of materials. The thickness and the nature of the barrier portions are chosen for their ability to avoid any phenomena of diffusion and electromigration of the underlying conductive tracks.

Claims (10)

  1. A method of forming an interconnection network consisting of a stack of insulating layers in which conductor tracks and conductive vias are alternately arranged, comprising the following steps: forming conductive tracks (51-53; 71-73 101-103) in a first insulating layer (50; 70; 100); forming sacrificial portions (57-59; 83-85; 105-107) covering the conductive tracks and projecting laterally beyond them over a predefined distance (L); etching the first insulating layer to form trenches (T) between the metal tracks, using as said etching mask said sacrificial layers, whereby the walls of the conductive tracks remain covered with fine portions (60, 61; 91, 110, 111) of said first insulating layer; eliminate the sacrificial portions; and improperly depositing a second insulating layer (65; 95; 130) above the previously formed structure, whereby air pockets (P) are formed between the tracks.   The method of claim 1, further comprising prior to depositing the sacrificial portions (57-59; 83-85), a step of forming barrier portions (54-56; 74-76) over the conductive tracks. (51-53, 71-73).   The method of claim 1, further comprising following removal of the sacrificial portions (105-107), a step of forming barrier portions (120-122) over the conductive tracks (101-103) .   The method of claim 2, further comprising after forming barrier portions (74-76), forming stop portions (80-82) overlaying the barrier portions, and wherein the sacrificial portions (83-85) ) are etched during etching of the first insulating layer (70) to form trenches (T), the etching step continuing until the stop portions are discovered.   5. The method according to claim 1, wherein during non-conforming deposition of said second insulating layer, thin insulating layers (66, 67; 96, 97; 131, 132) are formed in the trenches (T) against said fine portions ( 60, 61; 90, 91; 110, 111) of said first insulating layer overlying said conductive tracks (51-53; 71-73; 101103), and wherein said predefined distance (L) is greater than or equal to the difference between the maximum possible offset (d) between the definition mask of said conductive tracks (51-53; 71-73; 101-103) and the definition mask of conductive vias placed above the tracks, and the thickness (e) said thin insulating layers.   The method according to any one of the preceding claims, wherein said barrier, sacrificial and / or stopping portions are formed by selective deposition methods.   The method of claim 1, wherein the conductive tracks (51-53; 71-73; 101-103) comprise copper.   The method of claim 2 or 3, wherein said barrier portions (54-56; 74-76; 120-122) are made of a metallic material such as cobaltungsten-phosphorus.   9. The method of claim 1, wherein the conductive tracks have a width substantially equal to 100 nm and a minimum spacing equal to 100 nm, and said predefined distance (L) is substantially equal to 25 nm.   10. Equipment for carrying out the process according to claim 1.