FR2880981B1 - Memoire a semiconducteur a mode mixte - Google Patents
Memoire a semiconducteur a mode mixteInfo
- Publication number
- FR2880981B1 FR2880981B1 FR0512520A FR0512520A FR2880981B1 FR 2880981 B1 FR2880981 B1 FR 2880981B1 FR 0512520 A FR0512520 A FR 0512520A FR 0512520 A FR0512520 A FR 0512520A FR 2880981 B1 FR2880981 B1 FR 2880981B1
- Authority
- FR
- France
- Prior art keywords
- semiconductor memory
- mixed mode
- mode semiconductor
- mixed
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Analogue/Digital Conversion (AREA)
- Read Only Memory (AREA)
- Memory System (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020040118123A KR100736224B1 (ko) | 2004-12-31 | 2004-12-31 | 혼합모드 반도체 메모리 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2880981A1 FR2880981A1 (fr) | 2006-07-21 |
| FR2880981B1 true FR2880981B1 (fr) | 2011-11-18 |
Family
ID=36636859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0512520A Expired - Fee Related FR2880981B1 (fr) | 2004-12-31 | 2005-12-09 | Memoire a semiconducteur a mode mixte |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US7315267B2 (fr) |
| JP (1) | JP2006190439A (fr) |
| KR (1) | KR100736224B1 (fr) |
| FR (1) | FR2880981B1 (fr) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100764749B1 (ko) | 2006-10-03 | 2007-10-08 | 삼성전자주식회사 | 멀티-칩 패키지 플래시 메모리 장치 및 그것의 카피 백방법 |
| US20080309532A1 (en) * | 2007-06-12 | 2008-12-18 | Silicon Optronics, Inc. | Solid-state imaging device and method of manufacturing thereof |
| JP5193635B2 (ja) * | 2008-03-17 | 2013-05-08 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US8004887B2 (en) | 2008-11-07 | 2011-08-23 | Micron Technology, Inc. | Configurable digital and analog input/output interface in a memory device |
| US9147438B2 (en) * | 2013-10-23 | 2015-09-29 | Qualcomm Incorporated | Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745409A (en) * | 1995-09-28 | 1998-04-28 | Invox Technology | Non-volatile memory with analog and digital interface and storage |
| US6144327A (en) * | 1996-08-15 | 2000-11-07 | Intellectual Property Development Associates Of Connecticut, Inc. | Programmably interconnected programmable devices |
| US5842034A (en) * | 1996-12-20 | 1998-11-24 | Raytheon Company | Two dimensional crossbar mesh for multi-processor interconnect |
| US6208542B1 (en) | 1998-06-30 | 2001-03-27 | Sandisk Corporation | Techniques for storing digital data in an analog or multilevel memory |
| US6044004A (en) | 1998-12-22 | 2000-03-28 | Stmicroelectronics, Inc. | Memory integrated circuit for storing digital and analog data and method |
| US6865186B1 (en) * | 2000-02-10 | 2005-03-08 | Windbond Electronics Corporation | Multiple message multilevel analog signal recording and playback system having memory array configurable for analog and digital storage and serial communication |
| US6563733B2 (en) * | 2001-05-24 | 2003-05-13 | Winbond Electronics Corporation | Memory array architectures based on a triple-polysilicon source-side injection non-volatile memory cell |
-
2004
- 2004-12-31 KR KR1020040118123A patent/KR100736224B1/ko not_active IP Right Cessation
-
2005
- 2005-09-01 JP JP2005253273A patent/JP2006190439A/ja active Pending
- 2005-11-17 US US11/282,239 patent/US7315267B2/en not_active Expired - Fee Related
- 2005-12-09 FR FR0512520A patent/FR2880981B1/fr not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| FR2880981A1 (fr) | 2006-07-21 |
| KR100736224B1 (ko) | 2007-07-06 |
| KR20060078787A (ko) | 2006-07-05 |
| US20060146201A1 (en) | 2006-07-06 |
| JP2006190439A (ja) | 2006-07-20 |
| US7315267B2 (en) | 2008-01-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |
Effective date: 20160831 |