FR2869486A1 - Procede de traitement de donnees securise et dispositif associe - Google Patents

Procede de traitement de donnees securise et dispositif associe

Info

Publication number
FR2869486A1
FR2869486A1 FR0404824A FR0404824A FR2869486A1 FR 2869486 A1 FR2869486 A1 FR 2869486A1 FR 0404824 A FR0404824 A FR 0404824A FR 0404824 A FR0404824 A FR 0404824A FR 2869486 A1 FR2869486 A1 FR 2869486A1
Authority
FR
France
Prior art keywords
processing method
data processing
secure data
device therefor
mac
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR0404824A
Other languages
English (en)
Other versions
FR2869486B1 (fr
Inventor
Hugues Thiebeauld
Christophe Giraud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Idemia France SAS
Original Assignee
Oberthur Card Systems SA France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0404225A external-priority patent/FR2869485B1/fr
Application filed by Oberthur Card Systems SA France filed Critical Oberthur Card Systems SA France
Priority to FR0404824A priority Critical patent/FR2869486B1/fr
Priority to PCT/FR2005/000905 priority patent/WO2005109742A1/fr
Priority to US11/578,670 priority patent/US8788847B2/en
Publication of FR2869486A1 publication Critical patent/FR2869486A1/fr
Application granted granted Critical
Publication of FR2869486B1 publication Critical patent/FR2869486B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/51—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/64—Protecting data integrity, e.g. using checksums, certificates or signatures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
    • G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • Storage Device Security (AREA)
  • Communication Control (AREA)
  • Image Generation (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

L'invention concerne un procédé de traitement de données sécurisé, caractérisé en ce qu'il comprend les étapes suivantes :- remplissage (E206) d'une zone (MAC') de mémoire par une valeur de remplissage (A) ;- écriture (E208) d'une première donnée dans cette zone (MAC') ;- lecture dans cette zone (E210) d'une seconde donnée reprenant au moins une partie de la première donnée telle qu'elle a été écrite dans cette zone mémoire (MAC') ;- exécution d'une opération (E210) utilisant la seconde donnée.
FR0404824A 2004-04-21 2004-05-05 Procede de traitement de donnees securise et dispositif associe Expired - Fee Related FR2869486B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR0404824A FR2869486B1 (fr) 2004-04-21 2004-05-05 Procede de traitement de donnees securise et dispositif associe
PCT/FR2005/000905 WO2005109742A1 (fr) 2004-04-21 2005-04-14 Procédé de traitement de données sécurisé et dispositif associé
US11/578,670 US8788847B2 (en) 2004-04-21 2005-04-14 Secure data processing method and associated device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0404225A FR2869485B1 (fr) 2004-04-21 2004-04-21 Procede de traitement de donnees securise et dispositif associe
FR0404824A FR2869486B1 (fr) 2004-04-21 2004-05-05 Procede de traitement de donnees securise et dispositif associe

Publications (2)

Publication Number Publication Date
FR2869486A1 true FR2869486A1 (fr) 2005-10-28
FR2869486B1 FR2869486B1 (fr) 2007-08-31

Family

ID=34971815

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0404824A Expired - Fee Related FR2869486B1 (fr) 2004-04-21 2004-05-05 Procede de traitement de donnees securise et dispositif associe

Country Status (3)

Country Link
US (1) US8788847B2 (fr)
FR (1) FR2869486B1 (fr)
WO (1) WO2005109742A1 (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8738926B2 (en) * 2008-01-10 2014-05-27 Intel Mobile Communications GmbH Data processing system, method for executing a cryptographic algorithm and method for preparing execution of a cryptographic algorithm
US9118627B2 (en) * 2009-04-09 2015-08-25 Nokia Solutions And Networks Oy Method, apparatus and computer program product for improving resource reservation in session initiation
JP5824849B2 (ja) * 2011-04-22 2015-12-02 ソニー株式会社 情報処理装置および情報処理方法
US8261085B1 (en) 2011-06-22 2012-09-04 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US8181035B1 (en) 2011-06-22 2012-05-15 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US20120331308A1 (en) * 2011-06-22 2012-12-27 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
US8595510B2 (en) 2011-06-22 2013-11-26 Media Patents, S.L. Methods, apparatus and systems to improve security in computer systems
FR2984553B1 (fr) 2011-12-15 2015-11-06 Proton World Int Nv Procede et dispositif de detection de fautes
US20150052616A1 (en) * 2013-08-14 2015-02-19 L-3 Communications Corporation Protected mode for securing computing devices
FR3051935A1 (fr) * 2016-05-31 2017-12-01 Proton World Int Nv Execution securisee d'un algorithme

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000010283A1 (fr) * 1998-08-14 2000-02-24 Intel Corporation Protection de contenu numerique par mise en oeuvre d'un procede et dispositif d'amorçage securise

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
KR100213188B1 (ko) * 1996-10-05 1999-08-02 윤종용 사용자 인증 장치 및 방법
EP2280502B1 (fr) * 1998-06-03 2018-05-02 Cryptography Research, Inc. Utilisation d'informations imprévisibles pour résister à la découverte de secrets par surveillance externe
DE19856237C2 (de) * 1998-12-07 2002-03-07 Ibm Dynamische Schlüsselgenerierung und vertrauliche Synchronisation von Verschlüsselungskomponenten
FR2849226B1 (fr) * 2002-12-20 2005-12-02 Oberthur Card Syst Sa Procede et dispositif de securisation de l'execution d'un programme informatique.
FR2857473B1 (fr) * 2003-07-11 2005-09-16 Oberthur Card Syst Sa Procede de securisation de l'execution d'un programme informatique, notamment dans une carte a microcircuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000010283A1 (fr) * 1998-08-14 2000-02-24 Intel Corporation Protection de contenu numerique par mise en oeuvre d'un procede et dispositif d'amorçage securise

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
ANONYMOUS: "Conference Programme", INTERNET ARTICLE, XP002303177, Retrieved from the Internet <URL:http://web.archive.org/web/20030313034714/http://www.ruhr-uni-bochum.de/hgi/opening/workshop/programme.html> [retrieved on 20041029] *
DAVID FLANAGAN: "Example from Java Examples in a Nutshell", INTERNET ARTICLE, 22 November 2001 (2001-11-22), XP002303173, Retrieved from the Internet <URL:http://web.archive.org/web/20011223080453/http://examples.oreilly.com/jenut/Randomizer.java> [retrieved on 20041028] *
HELMUT SCHERZER: "SmartCard Operating Systems - Potential risks and security countermeasures", INTERNET ARTICLE, 31 January 2003 (2003-01-31), XP002303174, Retrieved from the Internet <URL:http://ca.itsc.ruhr-uni-bochum.de/hgi/smaca/scherzer.pdf> [retrieved on 20041021] *

Also Published As

Publication number Publication date
WO2005109742A1 (fr) 2005-11-17
US8788847B2 (en) 2014-07-22
FR2869486B1 (fr) 2007-08-31
US20090254761A1 (en) 2009-10-08

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