FR2854729A1 - Element comprenant une region poreuse et procede pour sa fabrication - Google Patents
Element comprenant une region poreuse et procede pour sa fabricationInfo
- Publication number
- FR2854729A1 FR2854729A1 FR0404753A FR0404753A FR2854729A1 FR 2854729 A1 FR2854729 A1 FR 2854729A1 FR 0404753 A FR0404753 A FR 0404753A FR 0404753 A FR0404753 A FR 0404753A FR 2854729 A1 FR2854729 A1 FR 2854729A1
- Authority
- FR
- France
- Prior art keywords
- porous
- layer
- production
- porous region
- nanometers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 230000007547 defect Effects 0.000 abstract 2
- 229910021426 porous silicon Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 239000011148 porous material Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C11/00—Receptacles for purposes not provided for in groups A45C1/00-A45C9/00
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C11/00—Receptacles for purposes not provided for in groups A45C1/00-A45C9/00
- A45C11/18—Ticket-holders or the like
- A45C11/182—Credit card holders
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C13/00—Details; Accessories
- A45C13/30—Straps; Bands
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C15/00—Purses, bags, luggage or other receptacles covered by groups A45C1/00 - A45C11/00, combined with other objects or articles
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C11/00—Receptacles for purposes not provided for in groups A45C1/00-A45C9/00
- A45C2011/002—Receptacles for purposes not provided for in groups A45C1/00-A45C9/00 for portable handheld communication devices, e.g. mobile phone, pager, beeper, PDA, smart phone
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45C—PURSES; LUGGAGE; HAND CARRIED BAGS
- A45C2200/00—Details not otherwise provided for in A45C
-
- A—HUMAN NECESSITIES
- A45—HAND OR TRAVELLING ARTICLES
- A45F—TRAVELLING OR CAMP EQUIPMENT: SACKS OR PACKS CARRIED ON THE BODY
- A45F2200/00—Details not otherwise provided for in A45F
- A45F2200/05—Holder or carrier for specific articles
- A45F2200/0516—Portable handheld communication devices, e.g. mobile phone, pager, beeper, PDA, smart phone
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Porous Artificial Stone Or Porous Ceramic Products (AREA)
- Silicon Compounds (AREA)
Abstract
Il est proposé une structure poreuse à haute uniformité même lorsqu'elle est évaluée à une résolution élevée, de plusieurs nanomètres ou plusieurs dizaines de nanomètres ou moins. En appliquant cette structure poreuse (12) à la fabrication d'un substrat de type SOI, on réduit le nombre de défauts d'un tel substrat. Des paramètres tels que la porosité et la densité de pores sont uniformisés dans une région à une profondeur de 5 à 10 nm de la surface de la couche (12) de Si poreux. L'utilisation de cette couche (12) de Si poreux permet de réduire le nombre de défauts en creux dans une couche SOI.Domaine d'application :Biosubstrats, dispositifs MEMS, etc.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003128229A JP2004335662A (ja) | 2003-05-06 | 2003-05-06 | 部材及び部材の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2854729A1 true FR2854729A1 (fr) | 2004-11-12 |
Family
ID=33308224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0404753A Withdrawn FR2854729A1 (fr) | 2003-05-06 | 2004-05-04 | Element comprenant une region poreuse et procede pour sa fabrication |
Country Status (6)
Country | Link |
---|---|
US (1) | US7049624B2 (fr) |
JP (1) | JP2004335662A (fr) |
KR (1) | KR20040095178A (fr) |
DE (1) | DE102004022161A1 (fr) |
FR (1) | FR2854729A1 (fr) |
TW (1) | TWI237296B (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005333090A (ja) * | 2004-05-21 | 2005-12-02 | Sumco Corp | P型シリコンウェーハおよびその熱処理方法 |
KR100677374B1 (ko) | 2005-11-14 | 2007-02-02 | 준 신 이 | 박판 실리콘 기판을 이용한 다공성 실리콘 태양전지 및 그제조방법 |
US7843982B2 (en) * | 2005-12-15 | 2010-11-30 | Palo Alto Research Center Incorporated | High power semiconductor device to output light with low-absorbtive facet window |
FR2957456B1 (fr) * | 2010-03-10 | 2013-01-04 | Commissariat Energie Atomique | Procede de fabrication d'un substrat comprenant une etape d'amincissement avec arret a detection d'une zone poreuse |
CN114166881B (zh) * | 2021-12-06 | 2024-06-25 | 南方电网科学研究院有限责任公司 | 一种基于微观结构评价的悬式复合绝缘子设计方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05335624A (ja) * | 1992-05-29 | 1993-12-17 | Hitachi Ltd | Si発光装置およびその作製方法 |
US5358600A (en) * | 1989-12-07 | 1994-10-25 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Method of making silicon quantum wires |
EP0843345A2 (fr) * | 1996-11-15 | 1998-05-20 | Canon Kabushiki Kaisha | Procédé de fabrication d'un objet semiconducteur |
EP0975012A2 (fr) * | 1998-07-23 | 2000-01-26 | Canon Kabushiki Kaisha | Silicium poreux avec une distribution uniforme des dimensions de pores |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69133359T2 (de) * | 1990-08-03 | 2004-12-16 | Canon K.K. | Verfahren zur Herstellung eines SOI-Substrats |
JP3257580B2 (ja) * | 1994-03-10 | 2002-02-18 | キヤノン株式会社 | 半導体基板の作製方法 |
CN1132223C (zh) * | 1995-10-06 | 2003-12-24 | 佳能株式会社 | 半导体衬底及其制造方法 |
IT1318284B1 (it) * | 2000-07-31 | 2003-07-28 | Cit Alcatel | Metodo e dispositivo per la configurazione ed il monitoraggio remotodi elementi di rete di telecomunicazioni. |
-
2003
- 2003-05-06 JP JP2003128229A patent/JP2004335662A/ja not_active Withdrawn
-
2004
- 2004-05-04 FR FR0404753A patent/FR2854729A1/fr not_active Withdrawn
- 2004-05-04 TW TW093112517A patent/TWI237296B/zh active
- 2004-05-05 DE DE102004022161A patent/DE102004022161A1/de not_active Withdrawn
- 2004-05-05 US US10/838,269 patent/US7049624B2/en not_active Expired - Fee Related
- 2004-05-06 KR KR1020040031645A patent/KR20040095178A/ko not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5358600A (en) * | 1989-12-07 | 1994-10-25 | The Secretary Of State For Defence In Her Britannic Majesty's Government Of The United Kingdom Of Great Britain And Northern Ireland | Method of making silicon quantum wires |
JPH05335624A (ja) * | 1992-05-29 | 1993-12-17 | Hitachi Ltd | Si発光装置およびその作製方法 |
EP0843345A2 (fr) * | 1996-11-15 | 1998-05-20 | Canon Kabushiki Kaisha | Procédé de fabrication d'un objet semiconducteur |
EP0975012A2 (fr) * | 1998-07-23 | 2000-01-26 | Canon Kabushiki Kaisha | Silicium poreux avec une distribution uniforme des dimensions de pores |
Non-Patent Citations (2)
Title |
---|
ASAI D ET AL: "MECHANISM OF VISIBILE PHOTOLUMINESCENCE IN POROUS SILICON", MEMOIRS OF THE FACULTY OF ENGINEERING, MIYAZAKI UNIVERSITY, FACULTY OF ENGINEERING, MIYAZAKI UNIVERSITY, MIYAZAKI, JP, no. 26, 1997, pages 31 - 38, XP008068379, ISSN: 0540-4924 * |
PATENT ABSTRACTS OF JAPAN vol. 018, no. 161 (E - 1526) 17 March 1994 (1994-03-17) * |
Also Published As
Publication number | Publication date |
---|---|
JP2004335662A (ja) | 2004-11-25 |
KR20040095178A (ko) | 2004-11-12 |
DE102004022161A1 (de) | 2005-01-05 |
TWI237296B (en) | 2005-08-01 |
TW200426902A (en) | 2004-12-01 |
US7049624B2 (en) | 2006-05-23 |
US20040224489A1 (en) | 2004-11-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20070131 |