FR2850179B1 - Dispositif d'antememoire pour un processeur de signal numerique et procede de commande - Google Patents
Dispositif d'antememoire pour un processeur de signal numerique et procede de commandeInfo
- Publication number
- FR2850179B1 FR2850179B1 FR0400490A FR0400490A FR2850179B1 FR 2850179 B1 FR2850179 B1 FR 2850179B1 FR 0400490 A FR0400490 A FR 0400490A FR 0400490 A FR0400490 A FR 0400490A FR 2850179 B1 FR2850179 B1 FR 2850179B1
- Authority
- FR
- France
- Prior art keywords
- anemematory
- control method
- digital signal
- signal processor
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
- G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
- G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2003-0004024A KR100532417B1 (ko) | 2003-01-21 | 2003-01-21 | 디지털 신호 처리장치의 저전력 소비형 캐시 메모리 장치및 이에 대한 제어방법 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2850179A1 FR2850179A1 (fr) | 2004-07-23 |
| FR2850179B1 true FR2850179B1 (fr) | 2006-12-08 |
Family
ID=33487758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0400490A Expired - Fee Related FR2850179B1 (fr) | 2003-01-21 | 2004-01-20 | Dispositif d'antememoire pour un processeur de signal numerique et procede de commande |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US20040148464A1 (fr) |
| KR (1) | KR100532417B1 (fr) |
| DE (1) | DE102004004248A1 (fr) |
| FR (1) | FR2850179B1 (fr) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI258078B (en) * | 2003-10-07 | 2006-07-11 | Via Tech Inc | Pre-fetch controller and method thereof |
| KR100735552B1 (ko) * | 2005-09-23 | 2007-07-04 | 삼성전자주식회사 | 코드 메모리 상의 프로그램의 코드 크기를 줄이는 방법 |
| US8010814B2 (en) | 2006-12-04 | 2011-08-30 | Electronics And Telecommunications Research Institute | Apparatus for controlling power management of digital signal processor and power management system and method using the same |
| KR100825816B1 (ko) | 2007-01-25 | 2008-04-29 | 삼성전자주식회사 | 핸드쉐이크 인터페이스 방식을 이용한 디지털 신호프로세서 및 그 구동방법 |
| US9244837B2 (en) * | 2012-10-11 | 2016-01-26 | Texas Instruments Incorporated | Zero cycle clock invalidate operation |
| US10402337B2 (en) | 2017-08-03 | 2019-09-03 | Micron Technology, Inc. | Cache filter |
| US11210246B2 (en) * | 2018-08-24 | 2021-12-28 | Advanced Micro Devices, Inc. | Probe interrupt delivery |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5948093A (en) * | 1996-02-09 | 1999-09-07 | Advanced Micro Devices, Inc. | Microprocessor including an interrupt polling unit configured to poll external devices for interrupts when said microprocessor is in a task switch state |
| US6378023B1 (en) * | 1996-02-14 | 2002-04-23 | Advanced Micro Devices, Inc. | Interrupt descriptor cache for a microprocessor |
| US6505253B1 (en) * | 1998-06-30 | 2003-01-07 | Sun Microsystems | Multiple ACK windows providing congestion control in reliable multicast protocol |
| JP2001249846A (ja) * | 2000-03-03 | 2001-09-14 | Hitachi Ltd | キャッシュメモリ装置及びデータ処理システム |
| US6748501B2 (en) * | 2000-12-30 | 2004-06-08 | International Business Machines Corporation | Microprocessor reservation mechanism for a hashed address system |
| US7047395B2 (en) * | 2001-11-13 | 2006-05-16 | Intel Corporation | Reordering serial data in a system with parallel processing flows |
-
2003
- 2003-01-21 KR KR10-2003-0004024A patent/KR100532417B1/ko not_active IP Right Cessation
-
2004
- 2004-01-20 FR FR0400490A patent/FR2850179B1/fr not_active Expired - Fee Related
- 2004-01-20 US US10/759,270 patent/US20040148464A1/en not_active Abandoned
- 2004-01-21 DE DE102004004248A patent/DE102004004248A1/de not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| FR2850179A1 (fr) | 2004-07-23 |
| KR100532417B1 (ko) | 2005-11-30 |
| DE102004004248A1 (de) | 2004-09-09 |
| KR20040067063A (ko) | 2004-07-30 |
| US20040148464A1 (en) | 2004-07-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |
Effective date: 20100930 |