FR2839829B1 - Buffer pour circuit a contact - Google Patents

Buffer pour circuit a contact

Info

Publication number
FR2839829B1
FR2839829B1 FR0205879A FR0205879A FR2839829B1 FR 2839829 B1 FR2839829 B1 FR 2839829B1 FR 0205879 A FR0205879 A FR 0205879A FR 0205879 A FR0205879 A FR 0205879A FR 2839829 B1 FR2839829 B1 FR 2839829B1
Authority
FR
France
Prior art keywords
buffer
contact circuit
circuit
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0205879A
Other languages
English (en)
Other versions
FR2839829A1 (fr
Inventor
Olivier Tardieu
Christophe Moreaux
Ahmed Kari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0205879A priority Critical patent/FR2839829B1/fr
Priority to US10/436,881 priority patent/US6806735B2/en
Publication of FR2839829A1 publication Critical patent/FR2839829A1/fr
Application granted granted Critical
Publication of FR2839829B1 publication Critical patent/FR2839829B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
FR0205879A 2002-05-14 2002-05-14 Buffer pour circuit a contact Expired - Fee Related FR2839829B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0205879A FR2839829B1 (fr) 2002-05-14 2002-05-14 Buffer pour circuit a contact
US10/436,881 US6806735B2 (en) 2002-05-14 2003-05-13 Buffer for contact circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0205879A FR2839829B1 (fr) 2002-05-14 2002-05-14 Buffer pour circuit a contact

Publications (2)

Publication Number Publication Date
FR2839829A1 FR2839829A1 (fr) 2003-11-21
FR2839829B1 true FR2839829B1 (fr) 2005-07-08

Family

ID=29286448

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0205879A Expired - Fee Related FR2839829B1 (fr) 2002-05-14 2002-05-14 Buffer pour circuit a contact

Country Status (2)

Country Link
US (1) US6806735B2 (fr)
FR (1) FR2839829B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107771A (ja) * 2012-11-29 2014-06-09 Toshiba Corp トライステート制御回路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62154917A (ja) * 1985-12-27 1987-07-09 Hitachi Ltd デジタル回路
JPH02166826A (ja) * 1988-12-20 1990-06-27 Nec Ic Microcomput Syst Ltd 半導体集積回路
JP3217224B2 (ja) * 1995-02-22 2001-10-09 富士通株式会社 レベル変換回路
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US5804998A (en) * 1996-12-26 1998-09-08 International Business Machines Corporation Voltage upwardly compliant CMOS off-chip driver
CN1254456A (zh) * 1997-05-01 2000-05-24 三菱电机株式会社 输出缓冲电路
US6087852A (en) * 1997-12-19 2000-07-11 Texas Instruments Incorporated Multiplexing a single output node with multiple output circuits with varying output voltages
US6118301A (en) * 1998-05-26 2000-09-12 Analog Devices, Inc. High voltage tolerant and compliant driver circuit
US6239617B1 (en) * 1999-11-04 2001-05-29 International Business Machines Corporation Mixed voltage output driver with automatic impedance adjustment

Also Published As

Publication number Publication date
US20030216088A1 (en) 2003-11-20
FR2839829A1 (fr) 2003-11-21
US6806735B2 (en) 2004-10-19

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130131