FR2823597A1 - MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material - Google Patents
MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material Download PDFInfo
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- FR2823597A1 FR2823597A1 FR0105013A FR0105013A FR2823597A1 FR 2823597 A1 FR2823597 A1 FR 2823597A1 FR 0105013 A FR0105013 A FR 0105013A FR 0105013 A FR0105013 A FR 0105013A FR 2823597 A1 FR2823597 A1 FR 2823597A1
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- 230000008021 deposition Effects 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000206 photolithography Methods 0.000 title abstract description 12
- 125000006850 spacer group Chemical group 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims description 19
- 230000000284 resting effect Effects 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000002019 doping agent Substances 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 description 7
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
Description
caractérisé en ce que la couche est en silicium.characterized in that the layer is made of silicon.
t Procédé de fabrication d'un transistor MOS à longueur de grille t Method for manufacturing a gate length MOS transistor
très réduite, et transistor MOS correspondant. very small, and corresponding MOS transistor.
L'invention concerne les circuits intégrés, plus particulièrement la fabrication des transistors MOS (transistors à effet de champ à grille isolée). Actuellement, la longueur de grille, c'est-à-dire sensiblement la longueur du canal d'un transistor MOS, est fixce par les limites de la résolution des étapes de photolithographie. En d'autres termes, la longueur de grille est fixce par la finesse minimale de la fenêtre de gravure définie par l'étape de photolithographie et par conséquent par la finesse The invention relates to integrated circuits, more particularly the manufacture of MOS transistors (insulated gate field effect transistors). Currently, the gate length, that is to say substantially the length of the channel of an MOS transistor, is fixed by the limits of the resolution of the photolithography steps. In other words, the gate length is fixed by the minimum fineness of the etching window defined by the photolithography step and consequently by the fineness
minimale de l'opération de gravure qui suit l'étape de photolithographie. minimum of the etching operation following the photolithography step.
Cette finesse caractérise généralement la technologie utilisce. Ainsi, lorsqu'on parle d'une technologie de 0,18,um par exemple, on ne pourra This finesse generally characterizes the technology used. So when we talk about a technology of 0.18, um for example, we cannot
pas réaliser des longueurs de grille inférieures à 0,18 m. not achieve grid lengths less than 0.18 m.
Or, l'invention permet de franchir cette limite technologique imposce par la photolithographie et de réaliser des transistors MOS dont la longueur de grille est inférieure aux limites de la photolithographie, c'est-àdire inférieure à la finesse minimale imposce par la technologie employée. L'invention propose donc un procédé de fabrication d'un transistor MOS, comprenant: - la formation sur un substrat semiconducteur ayant un premier type de conductivité, par exemple le type P. d'un empilement formé d'une première couche semiconductrice ayant un deuxième type de conductivité différent du premier, par exemple le type N. et d'une deuxième couche isolante, - la définition par photolithographie d'une fenêtre de gravore sur la surface supérieure de la deuxième couche isolante, - une gravure de l'empilement dans la fenêtre de gravure de façon à ménager une cavité, la formation dans la cavité d'une région isolante (espaceurs) s'appuyant sur les flancs de la cavité et sur le substrat et possédant une ouverture traversante débouchant sur la surface supérieure du substrat, - la formation sur la surface supérieure du substrat à travers ladite ouverture traversante d'une couche d'oxyde de grille, - le dépôt sur l'empilement et dans ladite ouverture traversante d'une couche d'un matériau de grille, et - une gravure de ladite couche de matériau de grille et dudit empilement de part et d'autre et à distance des bords de la région isolante, However, the invention makes it possible to overcome this technological limit imposed by photolithography and to produce MOS transistors whose gate length is less than the limits of photolithography, that is to say less than the minimum fineness imposed by the technology used. The invention therefore proposes a method for manufacturing a MOS transistor, comprising: - the formation on a semiconductor substrate having a first type of conductivity, for example the P type, of a stack formed of a first semiconductor layer having a second type of conductivity different from the first, for example type N. and of a second insulating layer, - the definition by photolithography of a gravore window on the upper surface of the second insulating layer, - an etching of the stack in the etching window so as to provide a cavity, the formation in the cavity of an insulating region (spacers) resting on the sides of the cavity and on the substrate and having a through opening opening onto the upper surface of the substrate , - the formation on the upper surface of the substrate through said through opening of a gate oxide layer, - the deposition on the stack and in said opening cross health of a layer of grid material, and - an etching of said layer of grid material and of said stack on either side and at a distance from the edges of the insulating region,
de façon à former un bloc sur la surface supérieure du substrat. so as to form a block on the upper surface of the substrate.
En d'autres termes, l'invention permet de réduire la longueur de grille (et par conséquent la longueur de canal) en-deçà des limites de la In other words, the invention makes it possible to reduce the gate length (and consequently the channel length) below the limits of the
photolithographie par réalisation d'espaceurs internes. photolithography by making internal spacers.
La formation de la région isolante peut s'effectuer par un dépôt conforme d'une couche d'un matériau isolant, par exemple du nitrure de silicium, sur l'empilement et dans la cavité, puis par une gravure plasma The insulating region can be formed by a conformal deposition of a layer of an insulating material, for example silicon nitride, on the stack and in the cavity, then by plasma etching.
anisotrope de ladite couche de matériau isolant. anisotropic of said layer of insulating material.
La réalisation des zones d'extension de source et de drain s'effectue avantageusement par un recuit de diffusion de l'empilement gravé. A cet égard, la première couche semiconductrice de l'empilement Advantageously, the source and drain extension zones are produced by diffusion annealing of the etched stack. In this regard, the first semiconductor layer of the stack
sert de source de dopants.serves as a source of dopants.
La gravure de la couche de matériau de grille et de l'empilement de façon à réaliser ledit bloc, peut conduire à une logère surgravure du substrat et par conséquent à une réduction de l'épaisseur des zones d'extension de source et de drain implantées, ce qui peut conduire alors à augmenter la résistance d'accès de ces zones. Aussi, est-il particulièrement avantageux de procéder à une implantation de dopants dans le substrat de part et d'autre du bloc, de façon à réaliser des régions de The etching of the layer of grid material and of the stack so as to produce said block, can lead to an over-etching of the substrate and consequently to a reduction in the thickness of the implanted source and drain extension zones. , which can then lead to increasing the access resistance of these areas. It is therefore particularly advantageous to implant dopants in the substrate on either side of the block, so as to produce regions of
source et de drain plus fortement dopées et plus profondes. more heavily doped and deeper source and drain.
L'invention a également pour objet un transistor MOS, comprenant: - un bloc s'appuyant sur un substrat semiconducteur ayant un premier type de conductivité, ce bloc comportant un empilement formé d'une première couche semi conductrice ay ant un deuxième type de conductivité différent du premier et d'une deuxième couche isolante, cet empilement possédant une cavité, une région isolante s'appuyant sur les flancs de la cavité et sur la surface supérieure du substrat et possédant une ouverture traversante déLouchant sur la surface supérieure du substrat, une couche d'oxyde de grille s'appuyant sur la surface supérieure du substrat, une région semiconductrice de grille s'étendant dans ladite ouverture traversante et s'appuyant sur la surface supérieure de l'empilement et sur ladite couche d'oxyde de grille, et des régions de source et de drain s'étendant dans le substrat sous la première couche semiconductrice de l'empilement et sous The invention also relates to a MOS transistor, comprising: - a block resting on a semiconductor substrate having a first type of conductivity, this block comprising a stack formed of a first semiconductor layer having a second type of conductivity different from the first and from a second insulating layer, this stack having a cavity, an insulating region resting on the sides of the cavity and on the upper surface of the substrate and having a through opening opening onto the upper surface of the substrate, a gate oxide layer resting on the upper surface of the substrate, a gate semiconductor region extending in said through opening and resting on the upper surface of the stack and on said gate oxide layer, and source and drain regions extending in the substrate under the first semiconductor layer of the stack and under
la région isolante.the insulating region.
L'invention a également pour objet un circuit intogré comportant The invention also relates to an integrated circuit comprising
au moins un transistor MOS tel que défini ci-avant. at least one MOS transistor as defined above.
D'autres avantages et caractéristiques de l'invention Other advantages and characteristics of the invention
appara^tront à l'examen de la description détaillée de modes de mise en will appear on examination of the detailed description of the modes of implementation.
oeuvre et de réalisation, nullement limitatifs, et des dessins annexés, sur lesquels: - les figures 1 à 4 illustrent schématiquement les principales étapes d'un mode de mise en oeuvre du procédé selon l'invention, permettant d'aboutir à un mode de réalisation d'un transistor selon l'invention. On va maintenant décrire la réalisation d'un transistor NMOS selon l'invention, étant bien entendu que l'invention s'applique également à la réalisation d'un transistor PMOS moyennant des modifications du type de conductivité de certaines couches à la portée de l'homme du métier. Sur la figure 1, la référence SB désigne un substrat semi conducteur, par exemple de type de conductivité P. Ce substrat peut être par exemple en fait un caisson ménagé dans une plaquette semi conductrice. On dépose de façon classique et connue en soi sur la surface supérieure du substrat une première couche semiconductrice 1, par exemple du polysilicium dopé N+. L'épaisseur de cette couche 1 est par exemple de l'ordre de 1500 . La concentration de dopants est supérieure work and embodiment, in no way limiting, and attached drawings, in which: - Figures 1 to 4 schematically illustrate the main steps of an embodiment of the method according to the invention, allowing to achieve a mode of realization of a transistor according to the invention. We will now describe the production of an NMOS transistor according to the invention, it being understood that the invention also applies to the production of a PMOS transistor with modifications of the type of conductivity of certain layers within the range of the skilled in the art. In FIG. 1, the reference SB denotes a semiconductor substrate, for example of conductivity type P. This substrate can for example be in fact a box formed in a semiconductor wafer. Is deposited in a conventional manner and known per se on the upper surface of the substrate a first semiconductor layer 1, for example N + doped polysilicon. The thickness of this layer 1 is for example of the order of 1500. The dopant concentration is higher
par exemple à quelques 1019 at/cm3. for example at some 1019 at / cm3.
Puis, on forme sur cette première couche semiconductrice 1 une deuxième couche isolante 2. A titre d'exemple, ceci peut être effectué par Then, a second insulating layer 2 is formed on this first semiconductor layer 1. As an example, this can be done by
un dépôt d'un oxyde de silicium TEOS bien connu de l'homme du métier. a deposition of a TEOS silicon oxide well known to those skilled in the art.
L'épaisseur de cette couche isolante peut être également de l'ordre de 1500 o A. On définit ensuite sur la surface supérieure de l'empilement de couches ainsi formé, une fenêtre de gravure par une étape classique de photolithographie (dépôt d'une couche de masque (résine), définition de la fenêtre de gravure, insolation de la résine, retrait de la résine dans la fenêtre de gravure). La longueur L de cette fenêtre de gravure est égale à The thickness of this insulating layer can also be of the order of 1500 o A. Next, an etching window is defined on the upper surface of the stack of layers thus formed by a conventional photolithography step (depositing a mask layer (resin), definition of the etching window, exposure of the resin, removal of the resin in the etching window). The length L of this etching window is equal to
0,18,um dans une technologie 0,18,um. 0.18, um in 0.18, um technology.
Puis, on effectue une gravure classique pleine plaque de façon à Then, a conventional full plate etching is carried out so as to
ménager une cavité 3 à l'emplacement de la fenêtre de gravure. provide a cavity 3 at the location of the etching window.
L'étape suivante, non illustrce sur la figure 1 à des fins de simplification, consiste à faire cro^tre par oxydation therrnique une fine couche d'oxyde dans le fond de la cavité 3 afin de limiter les problèmes de contrainte lors du dépôt de la couche de nitrure de siliclum conduisant à la formation de la région isolante 4 illustrce sur la figure 2 et que l'on va The next step, not illustrated in FIG. 1 for simplification purposes, consists in growing by thermal oxidation a thin layer of oxide in the bottom of the cavity 3 in order to limit the stress problems during the deposition of the layer of silicon nitride leading to the formation of the insulating region 4 illustrated in FIG. 2 and which is
maintenant décrire plus en détail. now describe in more detail.
On réalise un dépôt conforme d'une couche de nitrure de silicium Si3N4 ayant une épaisseur choisie, par exemple 400 A, sur la surface A conformal deposition of a layer of silicon nitride Si3N4 having a chosen thickness, for example 400 A, is carried out on the surface.
supérieure de la couche 2 et dans la cavité 3. layer 2 and in the cavity 3.
Puis, on procède à une gravure plasma anisotrope classique de façon à réaliser une région isolante 4 (espaceurs internes) s'appuyant sur les flancs de la cavité 3 et possédant une ouverture traversante débouchant sur la surface supérieure du substrat SB. La longueur de cette ouverture traversante au niveau du substrat, référencce L1 sur la figure 2, qui va définir la longueur de grille (et par conséquent sensiblement la longueur du futur canal) du transistor, est de ce fait bien inférieure à 0,18,um, par Then, a conventional anisotropic plasma etching is carried out so as to produce an insulating region 4 (internal spacers) resting on the sides of the cavity 3 and having a through opening opening onto the upper surface of the substrate SB. The length of this through opening at the level of the substrate, reference L1 in FIG. 2, which will define the gate length (and consequently substantially the length of the future channel) of the transistor, is therefore much less than 0.18, um, by
exemple égale à 0,1 m.example equal to 0.1 m.
On procède ensuite à un recuit thermique, par exemple à une température de 1000 C pendant un temps de 15 minutes, de façon à faire diffuser dans le substrat SB les dopants contenus dans la première couche semiconductrice 1. Ces zones de diffusion 5 vont former les futures zones Thermal annealing is then carried out, for example at a temperature of 1000 ° C. for a period of 15 minutes, so as to cause the dopants contained in the first semiconductor layer 1 to diffuse into the substrate SB. These diffusion zones 5 will form the future areas
d'extension des régions de source et de drain. extension of the source and drain regions.
s On procède ensuite à un nettoyage du fond de la cavité pour retirer les résidus de la couche d'oxyde formoe avant le dépôt de nitrure de silicium, et partiellement entamoe à la suite de l'opération de gravure anisatrope. Puis, on fait croître par oxydation thermique classique une couche d'oxyde de grille 6 sur le substrat SB dans le fond de la cavité entre s The bottom of the cavity is then cleaned to remove the residues from the oxide layer formoe before the deposition of silicon nitride, and partially started following the anisatropic etching operation. Then, by conventional thermal oxidation, a layer of gate oxide 6 is grown on the substrate SB in the bottom of the cavity between
les régions isolantes internes 4.internal insulating regions 4.
On peut également, à ce stade, procéder éventuellement à des implantations choisies dans le substrat entre les zones d'extension de source et de drain, de façon à effectuer un ajustement de la tension de seuil It is also possible, at this stage, to optionally carry out selected implantations in the substrate between the source and drain extension zones, so as to effect an adjustment of the threshold voltage.
Vt du transistor.Vt of the transistor.
Ensuite, on effectue de façon classique sur la structure illustrce à la figure 2, un dépôt d'une couche d'un matériau de grille, par exemple du polysilicium que l'on peut par exemple doper in situ N+. Puis, on effectue après avoir défini la taille et la géométrie de la partie supérieure de la grille par une opération de photolithographie, une gravure du matériau de grille, de la couche isolante 2 et de la couche semiconductrice 1 de façon à Then, conventionally on the structure illustrated in FIG. 2, a layer of a grid material, for example polysilicon, which can for example be doped in situ N +, is deposited. Then, after having defined the size and the geometry of the upper part of the grid, by photolithography, the grid material, the insulating layer 2 and the semiconductor layer 1 are etched so as to
obtenir, comme illustré sur la figure 3, un bloc BL reposant sur le substrat. obtain, as illustrated in FIG. 3, a block BL resting on the substrate.
L' op érati on de gravure du bl oc p eut engendrer une l ogère surgravure du substrat et par conséquent entamer les zones d'extension 5 de source et de drain, conduisant alors à augmenter la résistance d'accès de la source et du drain. Aussi, est-il particulièrement intéressant de compléter ici le procédé par une implantation 8 de dopants, de façon à The bl oc etching operation could cause a slight over-etching of the substrate and consequently initiate the source and drain extension zones 5, thus leading to increasing the access resistance of the source and the drain. . Also, is it particularly interesting to complete the process here with an implantation 8 of dopants, so as to
générer des zones diffusées 9 plus profondes. generate deeper diffused zones 9.
L'étape suivante du procédé, qui n'est absolument pas indispensable, peut consister à réaliser sur les flancs du bloc BL des espaceurs externes 14 (figure 4). Puis, on procède à une siliciuration classique de façon à réaliser des contacts de source 12, de drain 11 et de grille 13. La présence des espaceurs 14 évite un court-circuit entre les contacts source/drain et de grille lors de l'étape de silicluration, car le siliciure ne se forme pas sur une région isolante. Cependant, ces espaceurs 14 peuvent être omis sans risque de court-circuit lors de l'étape de The next step in the process, which is absolutely not essential, may consist in making external spacers 14 (FIG. 4) on the sides of the block BL. Then, a conventional siliciding is carried out so as to produce source 12, drain 11 and gate 13 contacts. The presence of the spacers 14 avoids a short circuit between the source / drain and gate contacts during the step siliciding, because the silicide does not form on an insulating region. However, these spacers 14 can be omitted without risk of short circuit during the step of
siliciuration en raison de la présence de la couche isolante 2. siliciding due to the presence of the insulating layer 2.
On obtient finalement, comme illustré sur la figure 4, un transistor TR dont le canal CH a une longueur bien inférieure aux limites technologiques imposces par la photolithographie. A cet égard, le transistor TR comporte notamment des espaceurs internes 4 conduisant à l'obtention d'une grille évasce avec une partie basse plus étroite que la Finally, as illustrated in FIG. 4, a transistor TR is obtained, the channel CH of which has a length much less than the technological limits imposed by photolithography. In this regard, the transistor TR includes in particular internal spacers 4 leading to the production of a flared gate with a lower part narrower than the
partie supérieure.the top part.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0105013A FR2823597A1 (en) | 2001-04-12 | 2001-04-12 | MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR0105013A FR2823597A1 (en) | 2001-04-12 | 2001-04-12 | MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| FR2823597A1 true FR2823597A1 (en) | 2002-10-18 |
Family
ID=8862263
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR0105013A Pending FR2823597A1 (en) | 2001-04-12 | 2001-04-12 | MOS transistor production with gate length less than that imposed by photolithography comprises forming internal spacers in cavity arranged in pile before deposition of gate material |
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| Country | Link |
|---|---|
| FR (1) | FR2823597A1 (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4488162A (en) * | 1980-07-08 | 1984-12-11 | International Business Machines Corporation | Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes |
| US4978629A (en) * | 1988-10-03 | 1990-12-18 | Mitsubishi Denki Kabushiki Kaisha | Method of making a metal-oxide-semiconductor device having shallow source and drain diffused regions |
| US5275960A (en) * | 1990-04-03 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
| US6008097A (en) * | 1996-12-14 | 1999-12-28 | Electronics And Telecommunications Research Institute | MOS transistor of semiconductor device and method of manufacturing the same |
| US6025635A (en) * | 1997-07-09 | 2000-02-15 | Advanced Micro Devices, Inc. | Short channel transistor having resistive gate extensions |
-
2001
- 2001-04-12 FR FR0105013A patent/FR2823597A1/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4488162A (en) * | 1980-07-08 | 1984-12-11 | International Business Machines Corporation | Self-aligned metal field effect transistor integrated circuits using polycrystalline silicon gate electrodes |
| US4978629A (en) * | 1988-10-03 | 1990-12-18 | Mitsubishi Denki Kabushiki Kaisha | Method of making a metal-oxide-semiconductor device having shallow source and drain diffused regions |
| US5275960A (en) * | 1990-04-03 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing MIS type FET semiconductor device with gate insulating layer having a high dielectric breakdown strength |
| US6008097A (en) * | 1996-12-14 | 1999-12-28 | Electronics And Telecommunications Research Institute | MOS transistor of semiconductor device and method of manufacturing the same |
| US6025635A (en) * | 1997-07-09 | 2000-02-15 | Advanced Micro Devices, Inc. | Short channel transistor having resistive gate extensions |
| US5960270A (en) * | 1997-08-11 | 1999-09-28 | Motorola, Inc. | Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions |
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