FR2816075B1 - Generateur ameliore pour la production de signaux d'horloge - Google Patents
Generateur ameliore pour la production de signaux d'horlogeInfo
- Publication number
- FR2816075B1 FR2816075B1 FR0013903A FR0013903A FR2816075B1 FR 2816075 B1 FR2816075 B1 FR 2816075B1 FR 0013903 A FR0013903 A FR 0013903A FR 0013903 A FR0013903 A FR 0013903A FR 2816075 B1 FR2816075 B1 FR 2816075B1
- Authority
- FR
- France
- Prior art keywords
- production
- clock signals
- improved generator
- generator
- improved
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0997—Controlling the number of delay elements connected in series in the ring oscillator
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S331/00—Oscillators
- Y10S331/02—Phase locked loop having lock indicating or detecting means
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0013903A FR2816075B1 (fr) | 2000-10-30 | 2000-10-30 | Generateur ameliore pour la production de signaux d'horloge |
US10/013,343 US6703880B1 (en) | 2000-10-30 | 2001-10-30 | Generator for the production of clock signals |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0013903A FR2816075B1 (fr) | 2000-10-30 | 2000-10-30 | Generateur ameliore pour la production de signaux d'horloge |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2816075A1 FR2816075A1 (fr) | 2002-05-03 |
FR2816075B1 true FR2816075B1 (fr) | 2004-05-28 |
Family
ID=8855885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0013903A Expired - Fee Related FR2816075B1 (fr) | 2000-10-30 | 2000-10-30 | Generateur ameliore pour la production de signaux d'horloge |
Country Status (2)
Country | Link |
---|---|
US (1) | US6703880B1 (fr) |
FR (1) | FR2816075B1 (fr) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7263151B2 (en) * | 2002-03-04 | 2007-08-28 | Broadcom Corporation | High frequency loss of signal detector |
ES2320992T3 (es) * | 2004-02-16 | 2009-06-01 | Alstom Belgium S.A. | Metodo para medir un voltaje o tension monofasica. |
US8189729B2 (en) * | 2005-08-03 | 2012-05-29 | Altera Corporation | Wide range and dynamically reconfigurable clock data recovery architecture |
US7423492B2 (en) * | 2005-10-20 | 2008-09-09 | Honeywell International Inc. | Circuit to reset a phase locked loop after a loss of lock |
KR100986611B1 (ko) * | 2008-06-13 | 2010-10-08 | 김영식 | 저전력 주파수분할기 및 상기 주파수분할기를 구비하는저전력 위상고정루프 |
US11936436B2 (en) | 2021-12-10 | 2024-03-19 | Rohde & Schwarz Gmbh & Co. Kg | External frontend device and frontend system |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2856211A1 (de) * | 1978-12-27 | 1980-07-03 | Licentia Gmbh | Digitale phasenregelschaltung mit einer hilfsschaltung |
US4380742A (en) * | 1980-08-04 | 1983-04-19 | Texas Instruments Incorporated | Frequency/phase locked loop circuit using digitally controlled oscillator |
CH670020A5 (en) * | 1986-01-20 | 1989-04-28 | Studer Willi Ag | Signal synchronising phase-lock circuit - has frequency divider for output signal reset in synchronism with signal flanks of input signal |
US4817199A (en) * | 1987-07-17 | 1989-03-28 | Rockwell International Corporation | Phase locked loop having reduced response time |
GB2236922B (en) * | 1989-08-31 | 1993-02-24 | Multitone Electronics Plc | Frequency synthesisers |
JPH1168559A (ja) * | 1997-08-20 | 1999-03-09 | Nec Corp | 位相同期ループ回路 |
JP2000196448A (ja) * | 1998-12-25 | 2000-07-14 | Nippon Precision Circuits Inc | 位相同期回路 |
JP2001028542A (ja) * | 1999-07-13 | 2001-01-30 | Oki Micro Design Co Ltd | Pll回路 |
-
2000
- 2000-10-30 FR FR0013903A patent/FR2816075B1/fr not_active Expired - Fee Related
-
2001
- 2001-10-30 US US10/013,343 patent/US6703880B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6703880B1 (en) | 2004-03-09 |
FR2816075A1 (fr) | 2002-05-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20090630 |