FR2814611B1 - Circuit tampon pour la reception d'un signal logique - Google Patents

Circuit tampon pour la reception d'un signal logique

Info

Publication number
FR2814611B1
FR2814611B1 FR0012182A FR0012182A FR2814611B1 FR 2814611 B1 FR2814611 B1 FR 2814611B1 FR 0012182 A FR0012182 A FR 0012182A FR 0012182 A FR0012182 A FR 0012182A FR 2814611 B1 FR2814611 B1 FR 2814611B1
Authority
FR
France
Prior art keywords
receiving
buffer circuit
logic signal
logic
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0012182A
Other languages
English (en)
Other versions
FR2814611A1 (fr
Inventor
Hugues Creusy
Christophe Mani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0012182A priority Critical patent/FR2814611B1/fr
Publication of FR2814611A1 publication Critical patent/FR2814611A1/fr
Application granted granted Critical
Publication of FR2814611B1 publication Critical patent/FR2814611B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
FR0012182A 2000-09-26 2000-09-26 Circuit tampon pour la reception d'un signal logique Expired - Fee Related FR2814611B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR0012182A FR2814611B1 (fr) 2000-09-26 2000-09-26 Circuit tampon pour la reception d'un signal logique

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0012182A FR2814611B1 (fr) 2000-09-26 2000-09-26 Circuit tampon pour la reception d'un signal logique

Publications (2)

Publication Number Publication Date
FR2814611A1 FR2814611A1 (fr) 2002-03-29
FR2814611B1 true FR2814611B1 (fr) 2005-04-15

Family

ID=8854652

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0012182A Expired - Fee Related FR2814611B1 (fr) 2000-09-26 2000-09-26 Circuit tampon pour la reception d'un signal logique

Country Status (1)

Country Link
FR (1) FR2814611B1 (fr)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4039858A (en) * 1976-04-05 1977-08-02 Rca Corporation Transition detector
JPS59128822A (ja) * 1983-01-14 1984-07-25 Nec Corp 半導体回路
DE4215423A1 (de) * 1992-05-11 1993-11-18 Sgs Thomson Microelectronics Schmitt-Trigger
JP2571020B2 (ja) * 1994-07-29 1997-01-16 日本電気株式会社 発振回路
KR100253273B1 (ko) * 1996-10-29 2000-04-15 김영환 입력 버퍼 회로
US5910730A (en) * 1996-12-13 1999-06-08 International Business Machines Corporation Digital circuit noise margin improvement

Also Published As

Publication number Publication date
FR2814611A1 (fr) 2002-03-29

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20080531