FR2811464A1 - Memory circuit comprising redundant cells placed outside memory blocks and connected to blocks as required by control, for use in information technology - Google Patents

Abstract

The memory circuit comprises a number of blocks (4), e.g. 8 of which 3 are represented, of memory cells organized in rows and columns, and at least one redundant row (16') formed by redundant memory cells and placed outside the blocks of memory circuit. The memory circuit also comprises a control block (18') for invalidating the writing/reading of a defective memory cell of any block of the memory circuit and for allowing after replacement the writing/reading of a memory cell of the redundant row. Each block (4) is adjoined by a rows decoder (8), and the control block (18') is connected to the rows decoder of each block for invalidating the writing/ reading of defective memory cell. The memory cells of rows of blocks and the redundant row form words, and a word of a row of any block containing a defective cell is replaced by a word of the redundant row. A row of any block containing defective memory cell is replaced by one of the redundant rows. Each redundant memory cell is of a static memory type.

Description

-1 2811464

  MEMORY CIRCUIT COEPORTING BACKUP CEMS

  The present invention relates to memory circuits, and in particular memory circuits comprising backup cells.

  The memory cells of a memory circuit are classified

  distributed in blocks with their own address decoders. In a memory circuit, certain memory cells may prove to be defective after the circuit has been manufactured. For this, we add to each block of the memory circuit additional memory cells, or memory cells of

  backup, intended to replace defective memory cells.

  FIG. 1 represents a dynamic memory circuit (DRAM) 2 comprising eight (of which only three are shown) blocks 4 of memory cells organized in rows and in columns (not shown). Each block 4 is associated with a row decoder 8, arranged to selectively activate one of the rows of the block. Each row decoder 8 is connected to an address bus

  to receive a block address and a row address.

  Each block 4 is connected to an input / output bus 12 via the

  medium of read / write amplifiers 14. In addition, each block 4 comprises a spare row 16 identical to the other rows of the block. Each block 4 is associated with a control means 18 suitable for activating or deactivating the emergency row 16. Each control means 18 is also connected to the address bus 10, and

  to the decoder 8 of the block with which it is associated.

  At the end of the manufacturing of the memory circuit 2, the

  circuit is tested to determine whether or not it has

  The faulty memory cells. If a row of a block 4 has at least one defective cell, the address of this block and the address of the "defective" row are stored in the control means

18 of the block.

  Thereafter, when it is desired to read or write a row of a block of circuit 2, each decoder 8 and each control circuit 18 receive the address of the block and

  the address of the row via bus 10.

  If the row does not have a defective memory cell

  killer, the addresses on the bus 10 do not coincide with any address stored in the control means 18, and these remain inactive. The decoder 8 of the block designated by the block address present on the bus 10 is activated. The row of the block which corresponds to the row address present on the bus 10 is then activated by the decoder 8 of the block and it is accessible by

  read / write via bus 12.

  If, on the other hand, the row is defective, the addresses present on the bus 10 coincide with the block and row addresses stored in a control means 18. This control means 18 deactivates the decoder 8 and activates the backup row

  16 of this block. In this way, any access to the defected row

  a block killer is replaced by an access to the emergency row

16 of the block.

  In Figure 1, each block 4 has a single backup row and, if the circuit 2 has only one defective row, it can be replaced with certainty. If circuit 2 has two defective rows, the second defective row has a seven in eight chance (for an eight-block circuit) of being in a block 4 different from that in which the first defective row is located. Consequently, the probability that circuit 2 will be repairable in this case is 7/8. More generally, if circuit 2 has a number n of defective rows (n being between one and eight), the probability that the circuit is repairable is equal to: Pn = (8!) / [(8-n) .8n ] This probability decreases very quickly when the number of defective rows increases. Thus, for n = 3, we have Pn = 0.656; for n = 4, Pn 0.410 and, for n = 8, Pn drops to 0.002, which means that it is practically impossible to repair eight faulty rows in the memory circuit of the

  figure 1. To guarantee a hundred percent repair of the

  cooked 2 if it has eight defective rows, each block 4 must be provided with eight spare rows 16, which brings the total number of spare rows to 64. However, each row of

  additional rescue increases the size and cost of the circuit.

  It will also be noted that, the greater the number of blocks of the memory circuit, the more the number of emergency rows

required must be large.

  Another drawback of circuit 2 is that the emergency rows are deeply embedded in the structure of each block. As a result, it is very difficult, if necessary, to remove or add spare rows of a block without complex and costly modifications. However, we may want to delete excess spare rows. Indeed, when the circuit manufacturing process is well controlled, the number of defective rows decreases, and a high number of rows of

relief is no longer justified.

  An object of the present invention is to provide a

  memory circuit organized in blocks of memory cells, which use

  reads a reduced number of backup memory cells.

  Another object of the present invention is to provide such a memory circuit in which it is easy to delete

  excess backup memory cells.

  According to the present invention, the backup memory cells are arranged outside the memory cell blocks, so that the backup memory cells can replace defective memory cells of any of the memory blocks.

memory cells.

  More particularly, the present invention provides a memory circuit comprising several blocks of memory cells organized in rows and columns, and at least one spare row formed of backup memory cells, in which the

  emergency row is placed outside the blocks of the memory circuit.

  According to an embodiment of the present invention, the memory circuit comprises means for invalidating the writing, respectively the reading, of a defective memory cell of a row of any block of the memory circuit and to allow in replacement the 'writing, respectively reading,

  a backup row memory cell.

  According to an embodiment of the present invention, each block comprises an address decoder and said means is connected to the address decoder of each block and is at least invalid

  the address decoder of the block containing the defective memory cell

  killer to invalidate the writing, respectively the reading, of

the defective memory cell.

  According to an embodiment of the present invention, the memory cells of the rows of the blocks of the memory circuit and of the spare row form words, a word of a row of any block containing a defective memory cell

  being replaced by a word from the emergency row.

  According to an embodiment of the present invention, a row of any block of the memory circuit containing a defective memory cell is replaced by one or more of the

emergency rows.

  According to an embodiment of the present invention, each backup memory cell is a static memory cell. These and other objects, features and advantages of the present invention will be discussed in detail in

  the following description of particular embodiments

  made without limitation in relation to the attached figures among which: FIG. 1, previously described, represents under

  blocks form a classic memory circuit with cells

  backup memory; FIG. 2 represents in the form of blocks a memory circuit according to an embodiment of the present invention; and Figure 3, shows in the form of blocks a circuit

  memory according to a variant of the present invention.

  In the figures, the same references represent the same elements; for reasons of clarity, only the elements

  necessary for understanding the invention have been shown

sented.

  FIG. 2 represents a memory circuit according to the pre-

  invention. In the embodiment shown, the circuit, here a dynamic memory circuit (DRAM), comprises eight (three of which are shown) blocks 4 of memory cells organized in rows and columns (not shown). It will be assumed that all the rows of the circuit are identical because this simplifies the description of the present invention, even if in practice there are two types of rows in a DRAM memory, due to the interleaving of the memory cells. Each block 4 is connected to a row decoder 8. Each decoder 8 is connected to an address bus 10 to receive a block address and a row address therefrom. Each block 4 is connected to an input / output bus

  12 via read / write amplifiers 14.

  The circuit also includes a backup row 16 '. The emergency row 16 'is located outside the blocks 4 of memory cells. A control means 18 ′, connected to the address bus 10, makes it possible to activate or inactivate the emergency row 16 ′, as well as the row decoder 8 of each of the blocks 4. Preferably in the example shown , the memory cells of the emergency row 16 ′ are not dynamic memory cells but static memory cells (SRAM), which prevents them from being refreshed and makes it possible to read or write them without reading amplifiers / writing. Preferably, these cells have the same structure as the read / write amplifiers 14 and are connected directly to the input / output bus 12.

  After manufacturing the memory circuit, the circuit

  cooked is tested to determine whether or not it has defective memory cells. If a row in block 4 has at least one defective cell, the address of this block 4 and that of the

  defective row are stored in the control means 18 '.

  Subsequently, when one wants to read or write access to a row of a block of circuit 2, if the row does not have a defective memory cell, the decoder 8 of the block designated by the block address and the row of the block that corresponds to the row address are activated. If the row is faulty, the addresses on bus 10 coincide with the block and row addresses stored in the means of

  18 'command. The control means 18 'then inactivates the deco-

  Deurs of row 8 of the circuit, or at least the decoder corresponding to the block containing the defective row, and active

the emergency row 16 '.

  Thus, a single emergency row 16 'according to the pre-

  sente invention allows to replace a defective row of any block of the memory circuit. More generally, a number n of emergency rows 16 ′ according to the present invention makes it possible to replace n defective rows, whatever the block to which they belong. Of course, if n spare rows are used, the control means 18 ′ will be provided for memorizing the addresses of the n defective rows. By way of example, a circuit according to the present invention provided with eight emergency rows 16 'makes it possible to replace eight defective rows with a probability of repair equal to 100%, to be compared to 0.2%

  obtained with the circuit of figure 1.

  In addition, it is relatively easy to delete

  emergency rows 16 'of the circuit if these prove to be super

  flues. Indeed, the emergency rows 16 ′ are not part of the memory cell blocks 4 and their deletion can be done without modifying the memory blocks, that is to say without modifying

deeply the circuit design.

  FIG. 3 represents in the form of blocks a circuit according to a variant of the present invention. This circuit includes eight (of which only three are shown) blocks 4 of cells

  memory organized in rows and columns (not shown).

  All the rows of the circuit are assumed to be identical. Each block 4 is connected to a row decoder 8. Each decoder 8 is connected to an address bus 10 to receive a block address and a row address therefrom. Each block 4 is connected to an input / output bus 12 via a column decoder and read / write amplifiers 14. Each column decoder 20 is connected to the address bus 10 to receive a

  word address. Each row is divided into a predefined number.

  finished with words of the same size. Each word comprises a predetermined number of bits, for example sixty four, sixteen or eight bits. Each word can also be formed of a single bit. The circuit

  further includes a spare row 16 '.

  An 18 "control means, connected to the address bus 10, makes it possible to activate or deactivate the emergency row 16 'word by word. The 18" control means also makes it possible to activate or

  to deactivate the row decoder 8 of each of the blocks 4.

  After manufacturing the memory circuit, the circuit

  cooked is tested to determine whether or not it has defective memory cells. When a defective cell is identified in a word in a row of block 4, the address of block 4,

  the address of the row and the address of the word "defective", that is

  say with defective memory cell, are stored

in the control means 18 ".

  Subsequently, when accessing read or write

  ture to a word in a row of a circuit block, if the word contains a defective cell, the block, row and word addresses present on bus 10 coincide with the addresses of

  block, row and word stored in the 18 "control means.

  The control means 18 "then inactivates all the decoders of row 8, or at least that which corresponds to the block containing the defective word, and activates the word in row 16 '" of the same rank ", that is to say corresponding to the word address present on the bus 10. In this way, access to the faulty word is replaced by access to the word with the same address in the emergency row 16 ′, and access to the other words in the row which contains the cell

  faulty memory is done normally.

  This embodiment of the present invention allows the replacement of several faulty words with a single spare row, and it allows better use of the

or emergency rows.

  Of course, the present invention is susceptible to various variants and modifications which will appear to a person skilled in the art. As an example, memory circuits have been described which comprise eight blocks of memory cells, but the number of

  memory cell blocks can be any.

  By way of example also, there are shown ran-

  16 'back-up units that use static memory cells. However, the present invention is also suitable for the use of dynamic memory backup cells. In such a case, the emergency rows will be connected to the bus

  input / output via amplifier amplifiers

  writing / writing such as amplifiers 14.

  Also by way of example, the present invention has been described in the context of a DRAM type memory circuit, but

  the present invention is also suitable for meteor circuits

  SRAM type memory, or to other types of memory circuits such as electrically programmable read-only memories (EPROM or

  EEPROM) organized in blocks and provided with emergency cells.

  Also by way of example, particular embodiments of memory circuits have been shown and described in

  which the backup memory cells are arranged in a row

  but the person skilled in the art will easily adapt the present invention to a memory circuit in which the memory cells

  are arranged in columns.

  It will also be noted that the manner of addressing the blocks, the rows and the words in the circuits of FIGS. 2 and 3 has only been described by way of example, and that other modes of addressing can be implemented without leaving the domain of

the present invention.

Claims (6)

  1. Memory circuit comprising several blocks (4) of memory cells organized in rows and columns, and at least one backup row (16 ') formed of backup memory cells, characterized in that the backup row (16') is arranged outside the blocks (4) of the memory circuit. 2. Memory circuit according to claim 1, comprising means (18 ', 18 ") for invalidating the writing, respectively the reading, of a defective memory cell of a row of any block of the memory circuit and for enabling replacing the writing, respectively the reading, of a memory cell of the emergency row.   3. Memory circuit according to claim 2, in the-   which each block (4) comprises an address decoder (8) and wherein said means (18 ', 18 ") is connected to the address decoder of each block and disables at least the address decoder of the block   containing the defective memory cell to invalidate the writing   reads, respectively, the faulty memory cell.   4. Memory circuit according to one of claims 1 to 3,   in which the memory cells of the rows of the blocks of the memory circuit and of the spare row form words and in which a word of a row of any block containing a defective memory cell is replaced by a word of the row rescue.   5. Memory circuit according to one of claims 1 to 3,   in which a row of any block of the memory circuit containing a defective memory cell is replaced by the or one of the emergency rows (16 ').   6. Memory circuit according to any one of the claims.   previous cations, in which each memory cell of   backup is a static memory cell.