FR2801388B1 - Procede de commande de memoire dram rapide et controleur adapte - Google Patents

Procede de commande de memoire dram rapide et controleur adapte

Info

Publication number
FR2801388B1
FR2801388B1 FR9914610A FR9914610A FR2801388B1 FR 2801388 B1 FR2801388 B1 FR 2801388B1 FR 9914610 A FR9914610 A FR 9914610A FR 9914610 A FR9914610 A FR 9914610A FR 2801388 B1 FR2801388 B1 FR 2801388B1
Authority
FR
France
Prior art keywords
control method
memory control
dram memory
suitable controller
fast dram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9914610A
Other languages
English (en)
Other versions
FR2801388A1 (fr
Inventor
Michel Harrand
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR9914610A priority Critical patent/FR2801388B1/fr
Priority to US09/715,904 priority patent/US6675256B1/en
Publication of FR2801388A1 publication Critical patent/FR2801388A1/fr
Application granted granted Critical
Publication of FR2801388B1 publication Critical patent/FR2801388B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
FR9914610A 1999-11-19 1999-11-19 Procede de commande de memoire dram rapide et controleur adapte Expired - Fee Related FR2801388B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9914610A FR2801388B1 (fr) 1999-11-19 1999-11-19 Procede de commande de memoire dram rapide et controleur adapte
US09/715,904 US6675256B1 (en) 1999-11-19 2000-11-17 Fast DRAM control method and adapted controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9914610A FR2801388B1 (fr) 1999-11-19 1999-11-19 Procede de commande de memoire dram rapide et controleur adapte

Publications (2)

Publication Number Publication Date
FR2801388A1 FR2801388A1 (fr) 2001-05-25
FR2801388B1 true FR2801388B1 (fr) 2003-12-12

Family

ID=9552338

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9914610A Expired - Fee Related FR2801388B1 (fr) 1999-11-19 1999-11-19 Procede de commande de memoire dram rapide et controleur adapte

Country Status (2)

Country Link
US (1) US6675256B1 (fr)
FR (1) FR2801388B1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6690606B2 (en) * 2002-03-19 2004-02-10 Micron Technology, Inc. Asynchronous interface circuit and method for a pseudo-static memory device
FR2841680B1 (fr) * 2002-07-01 2006-02-24 St Microelectronics Sa Dispositif de stockage de donnees multiports, en particulier pour une unte arithmetique et logique d'un processeur de traitement numerique du signal
US6920524B2 (en) * 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
FR2864321B1 (fr) * 2003-12-23 2007-01-19 St Microelectronics Sa Memoire dynamique a acces aleatoire ou dram comportant au moins deux registres tampons et procede de commande d'une telle memoire
FR2879337A1 (fr) 2004-12-15 2006-06-16 St Microelectronics Sa Circuit memoire, tel que dram, comportant un mecanisme correcteur d'erreur
US7560956B2 (en) * 2005-08-03 2009-07-14 Micron Technology, Inc. Method and apparatus for selecting an operating mode based on a determination of the availability of internal clock signals
KR101263167B1 (ko) * 2006-02-13 2013-05-09 삼성전자주식회사 메모리 셀에 대한 액세스 정보를 저장하는 반도체 메모리장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5184320A (en) * 1988-02-12 1993-02-02 Texas Instruments Incorporated Cached random access memory device and system
US5214777A (en) 1989-03-27 1993-05-25 Ncr Corporation High speed read/modify/write memory system and method
GB2244157A (en) * 1990-05-15 1991-11-20 Sun Microsystems Inc Apparatus for row caching in random access memory
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
EP0895162A3 (fr) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Dram amélioré avec régistres intégrés
JPH07130166A (ja) * 1993-09-13 1995-05-19 Mitsubishi Electric Corp 半導体記憶装置および同期型半導体記憶装置
US5835442A (en) * 1996-03-22 1998-11-10 Enhanced Memory Systems, Inc. EDRAM with integrated generation and control of write enable and column latch signals and method for making same
US6249840B1 (en) * 1998-10-23 2001-06-19 Enhanced Memory Systems, Inc. Multi-bank ESDRAM with cross-coupled SRAM cache registers

Also Published As

Publication number Publication date
FR2801388A1 (fr) 2001-05-25
US6675256B1 (en) 2004-01-06

Similar Documents

Publication Publication Date Title
EP1226502A4 (fr) Terminateur depla able electroniquement et procede d'utilisation dans un systeme de memoire
IL145531A0 (en) Shared memory apparatus and method for multiprocessor systems
FI971067A (fi) Menetelmä muistin toteuttamiseksi
NO20015498L (no) Injeksjonsanordning og fremgangsmåte for dens virkemåte
FI102424B1 (fi) Menetelmä muistin toteuttamiseksi
DE60045596D1 (de) Speicherungsuntersystem und Speicherungssteuerung
DE69837113D1 (de) Datenspeicheranordnung und Steuerverfahren dafür
FR2755663B1 (fr) Panneau thermique commande de maniere active et procede de commande associe
EP1176492A3 (fr) Méthode de commande d'accès et dispositif de mémorisation utilisant cette méthode
AU4500999A (en) Random access control method and system
DE69842047D1 (de) Datenspeicheranordnung und Steuerverfahren dafür
FR2778012B1 (fr) Dispositif et procede de lecture de cellules de memoire eeprom
FI102425B1 (fi) Menetelmä muistin toteuttamiseksi
DE69935548D1 (de) Zugriffsteuerungsverfahren, Speichergerät und Speichermedium
HK1048373A1 (en) An access control method
DE69932022D1 (de) Datenübertragungssteuerverfahren und dazu verwendete Gerät
DE60113354D1 (de) Zellsteuerungsverfahren und Zellsystem
FI19992808A (fi) Ohjain ja sen ohjausmenetelmä
FR2772508B1 (fr) Dispositif de memoire ferroelectrique et son procede de pilotage
FR2801388B1 (fr) Procede de commande de memoire dram rapide et controleur adapte
DE60042258D1 (de) Halbleiterspeicheranordnung und ihre Steuerungsverfahren
AU3752300A (en) Dependent bank memory controller method and apparatus
IT1318025B1 (it) Procedimento e dispositivo per variare il contenuto di memoria diapparecchi di comando.
EP1237314A4 (fr) Unite de commande de recherche de cellules et procede de commande de recherche de cellules
FR2801419B1 (fr) Procede et dispositif de lecture pour memoire en circuit integre

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090731