FR2798217B1 - Circuit de commande d'une memoire synchrone - Google Patents
Circuit de commande d'une memoire synchroneInfo
- Publication number
- FR2798217B1 FR2798217B1 FR9911220A FR9911220A FR2798217B1 FR 2798217 B1 FR2798217 B1 FR 2798217B1 FR 9911220 A FR9911220 A FR 9911220A FR 9911220 A FR9911220 A FR 9911220A FR 2798217 B1 FR2798217 B1 FR 2798217B1
- Authority
- FR
- France
- Prior art keywords
- control circuit
- synchronous memory
- synchronous
- memory
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9911220A FR2798217B1 (fr) | 1999-09-08 | 1999-09-08 | Circuit de commande d'une memoire synchrone |
PCT/FR2000/002451 WO2001018813A1 (fr) | 1999-09-08 | 2000-09-06 | Circuit de commande d'une memoire synchrone |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9911220A FR2798217B1 (fr) | 1999-09-08 | 1999-09-08 | Circuit de commande d'une memoire synchrone |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2798217A1 FR2798217A1 (fr) | 2001-03-09 |
FR2798217B1 true FR2798217B1 (fr) | 2002-03-29 |
Family
ID=9549630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9911220A Expired - Fee Related FR2798217B1 (fr) | 1999-09-08 | 1999-09-08 | Circuit de commande d'une memoire synchrone |
Country Status (2)
Country | Link |
---|---|
FR (1) | FR2798217B1 (fr) |
WO (1) | WO2001018813A1 (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2316590A1 (fr) * | 2000-08-23 | 2002-02-23 | Celestica International Inc. | Systeme et methode pour utiliser un dispositif synchrone avec une commande de memoire asynchrone |
DE10159956A1 (de) * | 2001-12-06 | 2003-06-18 | Siemens Ag | Speichermodul |
US6957307B2 (en) * | 2002-03-22 | 2005-10-18 | Intel Corporation | Mapping data masks in hardware by controller programming |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5692165A (en) * | 1995-09-12 | 1997-11-25 | Micron Electronics Inc. | Memory controller with low skew control signal |
US6209071B1 (en) * | 1996-05-07 | 2001-03-27 | Rambus Inc. | Asynchronous request/synchronous data dynamic random access memory |
US5926838A (en) * | 1997-03-19 | 1999-07-20 | Micron Electronics | Interface for high speed memory |
-
1999
- 1999-09-08 FR FR9911220A patent/FR2798217B1/fr not_active Expired - Fee Related
-
2000
- 2000-09-06 WO PCT/FR2000/002451 patent/WO2001018813A1/fr active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2001018813A1 (fr) | 2001-03-15 |
FR2798217A1 (fr) | 2001-03-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CD | Change of name or company name | ||
CD | Change of name or company name | ||
CJ | Change in legal form | ||
ST | Notification of lapse |