FR2797538A1 - SIGNAL FOLDING CIRCUIT, AND ANALOG-TO-DIGITAL CONVERTER SERIES INTERPOLATION CELL USING SUCH A CIRCUIT - Google Patents

Abstract

The present invention relates to a signal folding circuit, which can be used in particular to produce a series interpolation cell of an analog-digital interpolation converter. The circuit comprises two pairs of differential branches (Q1, Q2, Q1 b, Q2b) supplied by the same current source (41) connected to a first supply terminal (42), each pair comprising two transistors, the transistors (Q1, Q2b) of one pair being in parallel on the transistors of the other pair ( Q2, Q1b). Each group of two transistors in parallel is connected by a respective common resistor (R, Rb) to a second supply terminal (43), the two outputs of the folding circuit (V11, V11b) being the combined collectors of the two groups of transistors in parallel. The invention applies in particular to converters whose architecture includes a so-called serial interpolation part and which require high precision.

Description

Signal aliasing circuit, and serial interpolation cell of a

  Analog to digital converter using such a circuit The present invention relates to a signal aliasing circuit, usable in particular for producing a serial interpolation cell of an analog to digital interpolation converter. It applies for example to converters whose architecture includes a so-called part

  series interpolation and which require great precision.

  O10 A French patent application 92 14640 describes an analog-digital converter with folding circuit comprising a part

  series interpolation. One of the interests of an analog converter

  folding digital is that it saves comparators in its analog part. In particular, the conversion of the signal does not affect the comparison of the actual amplitude of the latter with a series of analog comparators. The successive weight conversion bits are obtained, by simple analog combinations, as a function of the belonging of the amplitude of the signal at intervals defined by regularly distributed reference voltages, these intervals being progressively smaller as as the conversion bits approach the least significant bit. Thus, a signal Vin is applied to the input of at least two aliasing circuits, the function of which is to supply so-called "folded" signals Vrl, Vrlb, Vr2, Vr2b, having an amplitude which varies with the amplitude of the input signal Vin according to a periodic function, of substantially sinusoidal shape. The functions Vrl and Vrl b are in phase opposition, likewise the functions Vr2 and Vr2b are in phase opposition. The

  Vrl and Vr2 functions are quadrature. The differences (Vrl-

  Vrl1b), (Vr2-Vr2b) cancel each other periodically for input voltage values which are the aforementioned reference voltages. From these differences, an interpolation cell establishes signals with the same general appearance as the differences in folded signals, but which cancel each other out for

  input voltage values intermediate between the reference values.

  Thus, if an interpolation cell has 2n + 1 reference voltages at the input as defined above, it has 2n + 1 + 1 so-called interpolated voltages. A cell therefore makes it possible to create an additional bit of information. From an initial folding circuit, the cascaded interpolation cells therefore make it possible to obtain the different successive bits of conversion of an analog quantity, starting from the most significant bit. The interpolation cells are conventionally cells called "Gilbert multiplier", in particular described in the aforementioned French patent application, but also in the international application WO 92/08288.

  The above brief description of an analog converter

  Digital folding circuit shows the importance of the precision of the reference voltages. However, the latter are obtained in the interpolation circuits comprising signal aliasing circuits, in particular Gilbert cells, the operating principle of which is based on current switches in pairs of differential branches.

  comprising bipolar or MOS type transistors, wired in cascade.

  From this architecture, it follows that the reference voltages depend

  in particular base-emitter voltages Vbe of cascaded transistors.

  This voltage itself depends on the current of the transistors and other external parameters such as for example the temperature. The precision of

  reference voltages, and therefore the result of the analog conversion-

  digital, is therefore therefore affected. Furthermore, for a

  peak voltage given the cascade of voltages Vbe limits the useful voltage, that is

  ie available for conversion.

  An object of the invention is to overcome the aforementioned drawbacks by limiting the number of base-emitter voltages Vbe in cascade in the signal aliasing circuit of an interpolation cell. To this end, the invention relates to a signal folding circuit, characterized in that it comprises two pairs of differential branches supplied by the same current source connected to a first supply terminal, each pair comprising two transistors , the transistors of one pair being in parallel on the transistors of the other pair, each group of two transistors in parallel being connected by a respective common resistor to a second supply terminal, the two outputs of the folding circuit being the collectors

  of two groups of transistors in parallel.

  The invention also relates to a signal folding cell, intended to receive four voltages varying as a function of an analog signal Vin, the functions varying as a function of Vin in phase opposition two to two and in quadrature of phase two to two, this cell providing at least two folded output signals, varying in phase opposition and having more aliasing than the input voltages for the same variation of Vin, the output signal combining the references of the input signals. The cell includes a folding circuit as defined above in which the bases of the four transistors receive the

  four voltages varying according to the analog signal Vin.

  The invention also relates to an interpolation cell for an analog-digital converter with interpolation, using cells

  like the one defined above.

  The main advantage of the invention is that it allows an improvement in the speed of conversion, that it makes it possible to improve the performance in speed, in particular of analog-digital converter without significantly increasing the supply voltages, which '' it simply improves these performance

  speed and that it is simple to implement.

  Other characteristics and advantages of the invention will appear

  with the aid of the description which follows made with reference to the appended drawings which

  represent: - Figure 1, an example of analog-digital converter architecture with interpolation cells using aliasing circuits; - Figures 2a and 2b, an example of folded waveforms, at the input and output of an interpolation cell; - Figure 3, an example of a folding circuit according to the prior art, said Gilbert cell; - Figure 4, a possible embodiment of a folding circuit according to the invention; - Figure 5, an illustration of the operation of a folding circuit according to the invention showing, as a function of an input voltage Vin, the waveforms of the currents passing through the resistors of the collectors and the waveforms output voltages; - Figure 6, a possible embodiment of an interpolation cell according to the invention - Figure 7, an illustration of the operation of a current combination circuit performing a shift of the waveforms at the input a folding circuit according to the invention, having the waveforms of collector current and of voltage in a resistor as a function of the aforementioned input voltage; - Figure 8, another possible embodiment of a circuit for shifting the waveforms at the input of a folding circuit according to the invention; - Figure 9, an illustration of the operation of the circuit of Figure 8 showing a waveform offset according to two other waveforms Figure 1 schematically shows an example

  architecture of analog-digital converter with folding circuit.

  The voltage to be converted Vin is present at the input of a first circuit of

  folding 1. For reasons of clarity of description, circuits not

  not directly related to the subject of the invention have not been shown in FIG. 1, this is for example the case of the blocking sampler generally placed at the input of an analog-digital converter. The outputs of the converter are represented by bits B0, B1, B2 ... BN having the value O or 1, the converter coding the analog quantities on N + 1 bits. As a reminder, the digital conversion approaches for example the analog input quantity Vin according to the following relation, in the case of a natural binary code: Vin = A0 (Bo2- '+ B12-2 + B22-3 + ... ..... BN2- (N + 1)) (1) o A0 represents the maximum possible amplitude of a signal to

convert.

  In other cases, progression can be done in GRAY code. There is

  then decodes the GRAY code into binary code.

  The bits Bo, B1, B2 .... BN come respectively from comparators CMPo, CMP1, CMP2, .... CMPN. It should be noted that at the output of the first folding circuit 1, at the head, it is possible to have several bits of information. It depends in particular on the number of folds, or

the number of references.

  The most significant bit Bo is obtained at the output of a first comparator CMPo which itself is wired at the output of the first folding circuit I mentioned above. The latter realizes, from the analog input voltage Vin, four voltages Vol, VO1b, V02, V02b supplied by its

four outputs.

  FIG. 2a illustrates by four curves the four folded voltages Vo1, Volb, V02, Vo2b mentioned above in a system of axes. More specifically, the curves representative of FIG. 2a illustrate the transfer functions between the input Vin of the folding circuit 1 and each of its four outputs. In other words, the abscissa axis representing the input voltage Vin, the ordinate axis represents the voltage Vo present on each of the four outputs of circuit 1 as a function of the input voltage Vin. Each of the four curves Vol, Volb, V02, Vo2b then respectively represent the variations of the folded voltages Vo01, VOlb, V02, Vo2b as a function of the input voltage Vin, these representative curves having

  same reference as their associated tensions, for reasons of simplicity.

  The variations of the folded voltages V01, Volb, Vo2, Vo2b are periodic and of substantially sinusoidal shape. A period represents the conversion range or the maximum admissible amplitude at the input of the converter, that is to say in particular the value A0 of the preceding relation (1), in the case where the first folding circuit 1 comprises five references, ie two bits of information. This is represented in relative value on the abscissa axis of FIG. 2a by the value 2. The curves V01ol and Volb are in phase opposition, likewise the curves V02 and V02b are in phase opposition. Curves V01 and V02 are quadrature, V02

  being ahead of Vol01 and passing through the origin point 0.

  The curves V02, Vo2b make it possible to determine the most significant bit Bo, the latter being equal to 1 if the input voltage Vin is greater than or equal to Ao / 2, represented by the relative value 1 on the abscissa axis of Figure 2a, or equal to O if it is less than this value. For this purpose, the outputs of the folding circuit 1 which include the voltages V02, V02b are wired to the input of the first logic comparator CMP0 so that the output of the latter is equal to 1 when Vo2 is greater than or equal to Vo2b and

  is equal to O otherwise.

  The Vo1, Vo0b curves alone form an information bit in GRAY code. The four outputs of the first folding circuit 1 are connected to the four inputs of a second folding circuit 2. In known manner, the latter performs an additional folding of the input voltage Vin as illustrated by four representative curves V11, Vllb, V12, V12b in Figure 2b, in the same system of axes as that of Figure 2a. It therefore supplies as output four folded voltages V11, Viîb, V12, V12b intended to be wired to another folding circuit 3 and, for two of them to indicate the value of bits B1 of next weight. The folding circuits 2, 3, 4, which follow the first 1 and which are designed to be cascaded are also called interpolation cells. The curves V1i, Vllb, V12, V12b which represent variations in the output voltages of the interpolation cell 2 as a function of the input voltage Vin are periodic, with a period half that of the previous curves V0ol, VO0b, V02, Vo2b, and substantially sinusoidal. The curves V11 and Vllb are in phase opposition, likewise the curves V12 and V12b are in phase opposition. The curves V.1 and V12 are in quadrature, V12 being ahead of V1l and

passing through the origin point 0.

  The bit B1, which immediately follows the most significant bit Bo, is therefore obtained at the output of a second comparator CMP1. The latter is wired at the output of the second folding circuit 2, so that the bit B, is equal to I when V12 is greater than or equal to V12b and is equal to O in the case

opposite.

  Similarly to obtaining B1, the interpolation circuits according to 3, 4 and the associated comparators CMP1, ... CMPN1 make it possible to obtain the bits according to B2, ... BN. An interpolation circuit 2, 3, 4, connected in cascade, performs an additional folding with respect to the preceding interpolation circuit and thus makes it possible to obtain an additional information bit, as illustrated by the passage of bit B0 to bit Bi as described above. The intersections of the curves V1i, V11b, V12, V12b on the abscissa axis represent what have previously been called reference voltages. These intersections themselves correspond to the intermediate intersections 21 of the curves Vo1, V0lb, V02, V02b, located between the values

  of reference of the latter 0, 0.5, 1, 1.5 and 2.

  Depending on whether the input voltage Vin is lower or higher than a reference voltage, the value of the corresponding weight bit, B1, in the example relating to FIG. 2a, is equal to 0 or 1. The precision of these voltages reference is therefore a very important parameter. In particular, it may therefore be important that these reference values depend as little as possible on parameters that cannot be controlled, such as for example the temperature. These reference values are obtained in lo interpolation circuits comprising signal aliasing circuits, in particular Gilbert cells, the operating principle of which is based on current switches in pairs of differential branches.

  comprising bipolar transistors, wired in cascade.

  FIG. 3 shows a voltage folding circuit according to the prior art, by way of example a Gilbert cell, which can also be produced in MOS technology. Such a circuit makes it possible for example to obtain the voltages V12 and V12b in FIG. 2b from the four voltages Vol, V01b, V02, V02b in FIG. 2a. The circuit of FIG. 3 comprises two differential pairs 31, 32, 33, 34 formed by NPN bipolar transistors. A first pair 31, 32 is connected via a first follower transistor 35, the base of which is controlled by the voltage Vo2, to a current source 36, and the second pair 33, 34 is connected to this same source by means of a second follower transistor 37, the base of which is controlled by the voltage Vo2b. The voltage V01 is connected to the base of a transistor 31, 33 of each pair. Likewise, the voltage V0ob is connected to the base of a transistor 32, 34 of each pair. The collector of transistor 31 of the first pair is connected with the collector of a transistor 34 of the second pair at a stabilized voltage Vcc, via a first resistor 38, the collectors of the other two transistors being connected to this same stabilized voltage Vcc via a second resistor 39. The connection point of the first resistor 38 and the collectors provides, for example, the voltage Vllb and the connection point of the second resistor and of the collectors supplies, for example, the voltage V11. The operating principle of this circuit can be briefly recalled. During the half-period during which the voltage Vol is greater than the voltage Vo01b, the current I of the source 36 can only pass through the transistors 31, 33 whose base is controlled by Vo1. Within this half-period, the current I passes on the one hand in the first resistor 38 and in the first follower transistor 35, and on the other hand in the second resistor 39 and the second follower transistor 37 according to the values relative of V02 and V02b. The voltage V11, or Vllb, therefore varies between Vcc - RI, case where the current passes through the first resistor 38, at Vcc, case where the current I passes through the second resistor 39, R being the value common to the two resistors 38, 39 connected to the stabilized voltage Vcc. During the quarter of period o V02 is greater than V02b, the voltage V12b is established from Vcc to Vcc - RI because the current I passes through the first resistor 38. Then during the second quarter of period o V02b is greater than Vo2, the voltage Vllb is established from Vcc - RI to Vcc, because the current no longer passes through the first resistor 38 but through the second 39. The phenomenon is similar during the half-period when the voltage V01b is greater than the voltage V01, if although the voltage Vllb evolves according to a period two times less than that which governs the variation of V01, Vl01b, V02, Vo2b. The folding of the tension is thus carried out. The voltage V11 changes from

  analogously to the voltage Vllb, but in phase opposition.

  An interpolation cell comprises a second folding circuit similar to that of FIG. 3, but o the voltages Vol01, V01b, V02, Vo2b are connected differently to obtain the voltages in quadrature V12, V12b. In Figure 2b, the extreme values Vcc and Vcc - RI have been shown. The origin of axes 0, then corresponds to the middle voltage between these two voltages. The reference voltages introduced by an interpolation cell depend on the intersection of the folded voltage curves at

its input, V01, V01b, V02, V02b.

  From the architecture of FIG. 3, it follows that the reference voltages, which depend in particular on the voltage differences among Vo01, Vo01b, V02, V02b, therefore depend on the base-emitter voltages Vbe of cascaded transistors. The base-emitter voltage Vbe varies in particular with temperature. The precision of the reference voltages, and therefore the precision

  of the analog-to-digital converter are then affected.

  In addition, the double voltage Vbe unnecessarily uses available voltage

  between the current source 36 and Vcc, which tends to increase the voltage Vcc.

  Increasing the latter to then maintain a significant voltage range goes against a general trend which decreases the supply voltages. FIG. 4 presents a possible embodiment of a circuit according to the invention, which limits the influence of the base-emitter voltages, allowing in particular an improvement of the precision, but also a

  lower supply voltage for analog converters

  digital. This folding circuit comprises two pairs of differential branches supplied by the same current source 41 connected to a first supply terminal 42. Each branch comprises at least one O transistor, the transistors of a pair being in parallel on the transistors of the other pair. Each group of two transistors in parallel is connected by a respective common resistor R, Rb to a second supply terminal 43, the two outputs V12, V12b of the folding circuit being the combined collectors of the two groups of transistors in parallel. In other words, the collector of a first transistor Q1 is connected with the collector of a second transistor Q2 to the second supply terminal via a first resistor R. Similarly, the collector of a third transistor QI b is connected with the collector of a fourth transistor Q2b to the second supply terminal via a second resistor Rb. The emitters of these four transistors are connected to the current source 41. A first output V12 is the connection point of the collectors and of the first resistor R and the second output V12b is the connection point of the collectors and of the second resistor Rb . A first pair of differential branches comprises the transistors QI and Q2b, and the second pair of differential branches comprises the transistors Q2 and Qlb. An emitter resistor RE1, RE2, RE3, RE4 is for example

  wired between each transistor Q1, Q2, Ql b, Q2b and the current source 41.

  These resistors make it possible in particular to obtain linear waveforms in the vicinity of the intersection 21, in FIG. 2a, of the various folded voltage curves Vo1, VO0b, V02, V02b, which is an important element for the precision of the reference voltages, which are defined by these intersections 21. It is indeed important that these curves intersect at levels o

  they have a sufficiently large gain.

  To simplify the representation, the voltages V0ol, V01b, V02, V02b have been placed directly at the inputs of the folding circuit of FIG. 4. In fact, to ensure the correct operation of the circuit, follower devices are for example interposed between the voltages V01, V0olb, V02, V02b and the inputs of the circuit, in particular for questions of adaptation of impedance, and also for aspects of common mode. These devices are for example transistors mounted in a known manner as voltage trackers. The voltage drop introduced by these followers is notably

  neutralized by the symmetry of the assembly.

  The operation of the circuit of Figure 4 can be explained by referring to Figures 2a and 2b. From, for example, four waveforms Vol, V01b, V02, V02b as illustrated in FIG. 2a, this circuit makes it possible to obtain the two waveforms Vil, Vllb in FIG. 2b. These two waveforms are said to be offset, because their reference values, which correspond to their intersections 22 on the abscissa axis, are offset with respect to the reference values produced by the waveforms of FIG. 2a. The reference values of the two waveforms V11, V11b of FIG. 2b in fact correspond to the intermediate intersections 21 of the waveforms of FIG. 2a. Considering this figure, from the reference value 0 to the first intermediate point of intersection 21, when V0Ob is greater than the other voltages, the current I of the current source 41 passes through the transistor Q2 controlled by Volb. Then, in accordance with the relative values of the voltages between the first intermediate intersection point 21 and the reference value 1, the current I passes successively through the transistor Qlb controlled by V02 until the intermediate intersection comprised between the reference values 0 , 5 and 1, then finally by the transistor Q1 controlled

  by Vo1, from this point of intersection to the value 1.

  FIG. 5a then illustrates the corresponding passage in the resistors R and Rb, the latter two having the same ohmic value. The current waveforms of the resistors R and Rb, denoted respectively IR and IRb, are given in two respective axis systems as a function of the relative values of the input voltage Vin. Thus, from 0 to the first intermediate intersection point 21, the current I passes through the resistance Rb and not into the resistance R. Then, up to the intermediate intersection point 21 between 0.5 and 1, the current I goes into resistance R and not into resistance Rb. Finally, from this intermediate point 21 to the reference value 1, the current I passes through the resistance Rb and not through the resistance R. The operation of the circuit can likewise be explained during the following half-period, it is that is to say between the relative reference values 1 and 2 of FIG. 2a. From the relative value 1 at the next intermediate intersection point 21, it is always the transistor Q1 which conducts the current I, since having the base voltage, Vo01, the highest. Resistor Rb therefore continues to conduct current to this intermediate point, while resistor R remains without current. Then, up to the point of intersection between the reference values 1.5 and 1, the transistor Q2b conducts the current, having the base voltage, Vo2b, the highest. It is then the resistance R which is crossed by the current I. Finally, up to the value 2, the current QIb, controlled by the voltage VOib which again becomes the highest, leads to

  again current 1, which then again passes through resistor Rb.

  The waveforms at the outputs are illustrated in a third system of axes in FIG. 5. When the resistor R starts to conduct, the output voltage V11 goes from the voltage Vcc, present at terminal 43, to the voltage Vcc-RI, while the output voltage Vlb goes from Vcc-RI to Vcc. The waveforms V11 and Vllb are then in phase opposition and intersect at values V'refl, V'ref2, V'ref3, V'ref4 equidistant each from the reference values 0, 0.5, 1, 1.5 and 2 of Figure 2a surrounding them, provided that these intersections occur where the curves are linear. This can be obtained by playing in particular on the values of the resistors of transmitters RE1, RE2, RE3, RE4. The aforementioned values V'refl V'ref2, V'ref3, V'ref4 constitute the new reference values created by the folding circuit of FIG. 4. The latter has been described for the folding of the voltages V01, Vo0b, V02, V02b, it works of course for the folding of all higher order waveforms, in particular in a cascade

  of interpolation cells in an analog-digital converter.

  A circuit according to the invention, as illustrated in FIG. 4, makes it possible by folding the waveforms Vo01, VO1b, V02, V02b to obtain what have previously been called the offset folded voltages V11 and Vllb. To make a series interpolation cell as defined relative to FIG. 1, it is necessary to add to the folding circuit of FIG. 4, another circuit which makes it possible to obtain the folded voltages V12 and V12b, which can be called direct folded voltages. For this purpose, one can for example add to the circuit of FIG. 4 another identical circuit, provided with a complementary assembly which makes it possible to obtain waveforms in quadrature, V12

and V12b.

  Figure 6 shows a possible embodiment of a

  interpolation cell, provided with two folding circuits according to the invention.

  This cell therefore has a circuit 61 identical to that of FIG. 4, and receives on its inputs the voltages Vol, V0o1b, V02, V02b as described relative to this figure. In other words, the voltages V01 attack the base of the transistor Q1, the voltages Vo1b attack the base of the transistor Q2, the voltages V02 attack the base of the transistor Ql b and the voltages V02b attack the base of the transistor Q2b. The cells have a second circuit 62 such as that of FIG. 4, comprising the same elements as the preceding 61, the latter, the functional characteristics of which may nevertheless be different, have the same references but the latter are

distinguished by the sign "'".

  Unlike circuit 61 which supplies offset folded voltages V11 and V1lb, circuit 62 which supplies direct folded voltages V12 and V12b on its two outputs does not directly receive voltages Vo1, VOb, V02, Vo2b. Thus, the folding circuit 62 receives on its four inputs, the two outputs of a first circuit 63 of combination of currents and the two outputs of a second circuit 64 of combination of currents. Each current combination circuit comprises for example two differential pairs each supplied by a respective current source 631, 632, 631 ′,

  632 'and having common collector resistances Rc, Rcb, R'c, R'cb.

  Still for each current combination circuit 63, 64, one pair receives the voltages Vo1 and V01b as inputs, and the other pair receives the voltages V02 and V02b as inputs. The two outputs of a combination circuit

  currents are taken from the resistors of collectors Rc, Rcb, R'c, R'cb.

  More specifically, a current combination circuit 63 comprises a first transistor QA, a second transistor QB, a third transistor QC and a fourth transistor QD, the first two transistors QA, QB forming the first differential pair and the other two QC, QD forming the second differential pair. The collectors of the first transistor QA and the third transistor QC are connected to the first resistor Rc, while the collectors of the second and fourth transistors QB, QD are connected to the second resistor Rcb. The emitters of the first two transistors QA, QB are connected to a first current source 631 and the emitters of the other two transistors are connected to the second current source 632. Preferably, to allow in particular to obtain very linear signals, the transmitters are connected to these current sources 631, 632 by resistors REA, REB, REC, RED. These current sources provide for example the same current. The connection point of the collectors of the two first and third transistors QA, QC and of the resistance O Rc forms a first output of the circuit 63, which is for example connected to the base of the transistor Q'1 of the folding circuit 62. Similarly , the connection point of the collectors of the two other transistors QB, QD and of the resistor Rcb forms a second output of the circuit 63, which is by

  example connected to the base of transistor Q'2 of the folding circuit 62.

  The collector resistors Rc, Rcb are also connected to the potential Vcc, that is to say to the aforementioned second terminal 43. To prevent saturation of the transistors QA, QB, QC, QD, these resistors Rc, Rcb are for example connected to this second terminal 43 via a diode Dl. The voltages V0o1, V0lb, V02, V02b respectively attack the bases of the transistors QA, QB, QC, QD respectively. The second circuit 64 for combining currents has the same components as the first 63, these elements being distinguished by the sign "'" in FIG. 6. In particular, the voltages Vo1, V0olb, V02, V02b respectively attack the bases transistors Q'A, Q'B, Q'C, Q'D. Finally, the connection point of the collectors of the two first and third transistors Q'A, Q'C and of the resistor R'c forms a first output of the circuit 64, which is for example connected to the base of the transistor Q'2b of the folding circuit 62. Similarly, the connection point of the collectors of the other two transistors Q'B, Q'D and of the resistor R'cb forms a second output of circuit 64, which is for example connected to the base of the transistor Q'lb of the folding circuit 62. For reasons of impedance adaptation in particular, the voltages V0o1, V01b, V02, Vo2b are not applied directly to the bases of the transistors of the interpolation cell, but

  for example by means of transistors mounted as voltage trackers.

  Furthermore, diodes, not shown and having an offset function, make it possible for the potential references on the first folding circuit 61 to be the same as on the second folding circuit 62, in particular to compensate for the base voltages. -transmitter

  Vbe of the transistors of circuits 63, 64 of combination of currents.

  As regards the operation of circuits 63, 64 for combining currents, it should be noted that the resistors of collectors Rc, Rcb transform the variations of currents produced by the circuit into voltages applicable to the input of the bases of the transistors. One role of the current combination circuits 63, 64 is in particular to create an offset of the waveforms Vo1, Volb, V02, V02b before they attack the inputs of the folding circuit 62. This offset in fact corresponds to the AV variation between a reference voltage, for example 0, and the next intermediate point of intersection 21. It is also the offset between the direct and offset folded waveforms. The operation of a circuit 63, 64 can be described with reference to FIGS. 2a and 2b, to show for example that the waveform Vo2 is offset on the base of the transistor Q'2 of the second folding circuit 62 d ' an AV offset by

  compared to its input on the base of transistor Q2.

  FIG. 7 illustrates by two systems of axes the current IRc in the resistance Rc and the voltage VQ'2 present on the base of the transistor Q'2. In broken lines, the waveform V02 is recalled. The currents Il and 12 of the sources 631, 632 are identical and for example equal to I. When Vin is between O and 0.5 the current Il passes through the transistor QC because the voltage V02 which controls the latter is greater than the voltage V02b which controls the transistor QD, and the current 12 passes through the transistor QB because the voltage VOlb which controls the latter is greater than the voltage Vol which controls the transistor QA. The current IRc which passes through the resistor Rc is therefore equal to I. When Vin is between 0, 5 and 1 the current It always passes through the transistor QC because the voltage V02 which controls the latter remains higher than the voltage Vo2b which controls the transistor QD, but the current 12 then passes through the transistor QA because the voltage V01 which controls the latter again becomes greater than the voltage VOlb which controls the transistor QB. The current IRc which passes through the resistance Rc is therefore equal to 21. By comparing the voltages Vol, VO0b, V02, V02b with one another, it is easy to show that when Vin is between 1 and 1.5 the current IRc which passes through the resistance Rc is equal to 1, and that when Vin is between 1.5 and 2 the current IR, which passes through the resistance Rc is equal to 0. The current wave IRc which crosses the collector resistance Rc is periodic and offset by AV, in advance, with respect to the waveform V02. The waveform V'02 generated on the basis of the transistor Q'2 of the second folding circuit 62 is therefore offset, in advance of AV, relative to the waveform V02 present at the input of the transistor Q2 of the first folding circuit 61. What has just been described for this waveform V02 also applies to the other waveforms Vo1, Volb, V02b. The folded waves V12 and V12b obtained at the output of the second folding circuit 62 will therefore be offset, in advance of AV, relative to the waveforms V11 and Vllb obtained at the output of the folding circuit 61. The interpolation cell of the Figure 6 therefore allows

  to obtain the four folded voltages V11, Vlîb, V12, V12b. The description of

  operation of this cell was made to obtain the voltages V11, V1lb, V12, V12b from the voltages Vo1, Vo01b, V02, Vo2b. The operation is of course the same regardless of the order of the folded waveforms, the reference values 0, 0.5, 1 and 1.5 on which this was based.

  description is also relative values of the input voltage Vin.

  The latter therefore apply regardless of the order of the folded voltages.

  Regarding the linearity of the signals mentioned above, it is

  portions of signals between the vertices of the waveforms.

  This linearity is for example obtained by playing on the resistances

emitters of the transistors.

  The interpolation cell described in FIG. 6 is presented by way of example. This cell includes a signal folding circuit as illustrated in FIG. 4 which gives the offset folded waveforms V11 and Vllb. It also includes a signal aliasing cell which makes it possible to obtain direct waveforms V12 and V12b. In this cell, the previous folding circuit is completed by circuits 63, 64 of combination of currents which make it possible to carry out the AV offset to obtain the direct folded waveforms. It is of course possible to use other circuits than these current combination circuits to obtain this offset. FIG. 8 shows another possible embodiment of a folding cell which makes it possible to obtain the direct waveforms. For simplicity, only the offset circuit has been shown. This circuit includes for example four pairs of resistors R1 and R'1, Rlb and R'lb, R2 and R'2, R2b and R'2b. The voltage Vol occurs between a first pair R1, R'1 and a second pair Rl b, R'1 b. The voltage Vo2 occurs between the second pair Rlb, R'lb and a third pair R2, R'2. The voltage V0lb occurs between the third pair R2, R'2 and a fourth pair R2b, R'2b. The voltage V02b occurs between the fourth pair R2b, R'2b and the first pair R1, R'1. The connection point 81 between the two resistors R1, R'1 of the first pair is connected to the base of the transistor Q'I. The connection point 82 O between the two resistors RIb, R'lb of the second pair is connected to the base of the transistor Q'lb. The connection point 83 between the two resistors R2, R'2 of the third pair is connected to the base of the transistor Q'2. The connection point 84 between the two resistors R2b, R'2b of the fourth pair is

  connected to the base of transistor Q'2b.

  FIG. 9 illustrates the operation of the assembly in the case of the voltage V02. Resistors can for example all have the same value. In this case, the voltage at point 83 present on the base of transistor Q'2 is equal to V'02 = (V02 + V01b) / 2. Referring to the waveforms V01, V1Ob, V02, V02b as presented in FIG. 2a, we obtain at this point 83 a waveform V'02 which is shifted in advance by AV with respect to the voltage Vo2 , thus obtaining a result similar to that of the assembly of FIG. 6. The assembly of FIG. 8 has in particular the advantage that it does not

involves only passive circuits.

  As regards the technology of the components, the transistors used can be in particular NPN or PNP transistors or

NMOS or PMOS transistors.

  With regard to the speed of a signal aliasing or interpolation cell, it can be characterized by the time for establishing the voltages and the propagation times when the input signals are voltage steps. These parameters can very simply be optimized by correctly dimensioning the currents, in particular in the differential pairs of the current combination circuits 63, 64, since these are advantageously independent for each pair. The operating speed can be further improved by the addition of cascade structures, called cascodes, in the collectors of the differential pairs, in a more optimized manner than in the prior art which already comprises cascade transistors, and which therefore requires higher supply voltages. Circuits according to the invention therefore make it possible advantageously to increase the speed of operation, in particular5 of analog-digital converters without however significantly increasing the supply voltage of the circuits. Finally, the structures

  used by the invention are simple. The circuits can therefore easily be implemented and optimized.

Claims (10)

  1. Signal folding circuit, characterized in that it comprises two pairs of differential branches (Q1, Q2, Qlb, Q2b) supplied by the same current source (41) connected to a first supply terminal (42) , each pair comprising two transistors, the transistors (Q1, Q2b) of one pair being in parallel with the transistors of the other pair (Q2, Q lb), each group of two transistors in parallel being connected by a respective common resistor (R, Rb) to a second supply terminal (43), the two outputs of the folding circuit (V1l, Vllb) being   collectors combined from two groups of transistors in parallel.   2. Signal folding cell, intended to receive four voltages (Vol, Vo01b, V02, V02b) varying according to an analog signal Vin, the functions varying according to Vin in phase opposition two by two and in quadrature of phase two by two, this cell providing at least two folded output signals (Vil and Vo1b, V12 and V12b), varying in phase opposition and having more aliasing than the input voltages for the same variation in Vin, characterized in that it includes a folding circuit (61) according to claim 1 in which the bases of the four transistors (Q1, Q2, Qlb, Q2b) receive the four voltages (V01, V01b, V02,   Vo2b) varying according to the analog signal Vin.   3. signal folding cell according to claim 2, characterized in that the two transistors (Q1, Q2b) of a differential pair receive two voltages (VoI, Vo2b) varying in phase quadrature and the two transistors of the other pair (Q2, Qlb) receive both   other voltages (VOlb, V02) varying in phase quadrature.   4. Signal folding cell according to any one of the   Claims 2 or 3, characterized in that it comprises another circuit for   folding (62) according to claim 1, this other circuit receiving on its four inputs the two outputs of a first current combination circuit (63) and the two outputs of a second current combination circuit (64), each current combination circuit comprising two differential pairs (QA and QB, QC and QD) each supplied by a respective current source (631, 632, 631 ', 632') and having common collector resistors (Rc, Rcb, R 'c, R'cb), one of the pairs (QA, QB) receiving as inputs two input voltages (Vo1, Vo01b) varying in phase opposition and the other pair (QC, QD) receiving as inputs the two other voltages (V02, Vo2b) varying in phase opposition, the outputs of the current combination circuit (63, 64) being taken from the resistors   collectors (Rc, Rcb, R'c, R'cb) of the two differential pairs.   5. Cell according to claim 4, characterized in that the resistors of collectors (Rc, Rcb, R'c, R'cb) being connected to the second terminal (43), an offset diode (D1, Dlb) is wired between these resistors and this terminal.   6. Cell according to any one of claims 4 or 5,   characterized in that the transistors of the differential pairs (QA and QB, QC and QD) are connected to the current sources (631, 632) by an emitter resistance.   7. Cell according to any one of claims 2 or 3,   characterized in that it comprises another folding circuit (62) according to claim 1, this other circuit receiving on its four inputs the four outputs of a circuit comprising four pairs of resistors (R1 and R'1, Rlb and R '1b, R2 and R'2, R2b and R'2b) connected in series, the connection point (81, 82, 83, 84) between the two resistors of each pair forming the outputs, the connection points between each pair forming the inputs receiving the voltages (Vo1, VO0b, V02, V02b) varying as a function of the analog signal Vin, the voltages varying in phase opposition being separated by two pairs of resistors and the voltages varying in quadrature being   separated by a pair of resistors.   8. Cell according to claim 7, characterized in that the resistors have the same value.   9. Circuit according to claim 1, characterized in that the emitters of the transistors (Q1, Q2, Qlb, Q2b) are connected to the source of   current (41) via resistors (RE1, RE2, RE3, RE4).   10. Interpolation cell for an analog converter   digital interpolation, characterized in that it includes a   folding according to any one of claims 2 to 8.