FR2695523A1 - Electronic analogue=to=digital converter - uses initial stage to determine sign of input current and subsequent stages to determine Gray Code - Google Patents

Abstract

The input current (Ieo) is fed to a primary stage (E0) which generates an output (G5) indicating the sign of the current. A current convertor circuit generates an output current for input to the next stage (E1). If the input current (Ieo) is negative then the current convertor transmits the absolute value of the input current. N subsequent stages (E1-E5) in series generate output bits (G4-G0) representing the Gray code for the analog input current. USE/ADVANTAGE - Analog to digital conversion for video signal processing. Adequate speed but reduced complexity over existing designs.

Description

FAST ANALOG TO DIGITAL CONVERTER
AND ASSOCIATED CONVERSION METHOD
The invention relates to fast analog / digital converters. In particular, it finds applications in the field of video signal processing and instrumentation.

 Fast analog / digital converters are very diverse depending on the application. There are mainly four types of parallel structures, parallel-series, interpolation and folding and pipeline.

The parallel converter with N bits of resolution also called flash converter (in Anglo-Saxon literature), comprises 2N-1 comparators and a network of at least as many resistors for delivering voltage references for each comparator. A voltage to be measured Ve is applied simultaneously to the input of all the comparators. All the comparators below Ve will not switch while those located above will switch. To obtain a binary coding on N bits, it is necessary to put a logic circuit of coding in series on the output of the comparators. This type of converter is the fastest, because all the comparators act in parallel. It offers good resolution; you can get 8-10 bit resolution at a few tens of
Megahertzs. On the other hand, due to this parallel structure, its consumption is high and it occupies a very large area.

 A serial converter parallel to N bits of resolution also called semi-flash converter (in English literature), comprises a first analog / digital converter parallel to P bits of resolution followed in series by a digital / analog converter and a second analog / digital converter parallel to Q resolution bits with P + Q = N + 1. The first analog / digital converter performs a first coding of an input voltage. The result of this coding is applied to a digital / analog converter with P bits of resolution and N bits of precision. A voltage V'e is obtained at the output. The error (V'e-Ve) is amplified and then applied to the second parallel analog / digital converter which performs a second coding. Correction logic processes the two codings to configure the final result on N bits in binary code. This structure requires the presence of an input sampler-blocker, whose performance must be compatible with the analog / digital N-bit converter. Such a series-parallel structure decreases the speed of conversion, but makes it possible to obtain a very good resolution at the cost of a very bulky complex structure and a consumption which remains high.

 An interpolation and aliasing converter has an input stage comprising P groups of M comparators for delivering P folded waveforms of the input signal to be converted. Between two consecutive waveforms, N interpolations are carried out by means of a resistance bridge. We obtain P (N + 1) interpolated outputs. We find at this level the structure of the parallel converter (flash), each output being applied to a comparator. We have at output 2N bits of resolution. The input stage of this converter makes it possible to reduce the number of comparators used in flash structures. But in return, the structure of this converter is quite complex.

 An overlapping converter with Nbits of resolution, commonly referred to as a pipeline in Anglo-Saxon literature, comprises N to N + 2 comparators cascaded and as many amplification stages. It requires a compatible performance sampler-blocker as input. Each comparator compares an input voltage with a voltage reference. The voltage reference is the same for each comparator. The first stage receives the input voltage to be converted. The second input stage receives the amplified difference between the input voltage of the previous stage and the voltage reference. A logic circuit combines the comparator outputs to obtain binary coding.

 The surface of such a structure is medium for an equally rapid speed.

 Overall, all these converters occupy a large area, due to the number of comparators or the need for a sampler-blocker and amplification stages. It has a relatively high consumption, especially in the case of parallel structures. They all require a logic circuit to obtain binary coding. They also require an encoding circuit in Gray code from the outputs delivered by each conversion stage when this code wants to be used. This Gray code is in fact the one which allows the least conversion error, in particular, in the middle of the scale, since a single bit changes between two successive digital values. It is therefore widely used, especially in video signal processing and instrumentation applications.

 The object of the invention is to provide an analog / digital converter which is relatively compact and of low consumption for a low resolution (6 to 8 bits) but sufficient for video signal processing and instrumentation applications. It is indeed necessary to reduce as much as possible the surfaces of the converters in order to increase the complexity of the integrated electronic circuits of the video and instrumentation equipment.

 Another object of the invention is a converter which has a fast conversion with a conversion speed comparable to that of known fast converters. In an example, we seek to obtain a conversion with 6 to 8 bits of resolution at 15MHZ.

 According to the invention, a conversion is carried out not of an input voltage but of a current placed in a range symmetrical with respect to zero. A conversion stage comprises means for detecting the sign of the input current and delivering a corresponding digital signal. such a characteristic makes it possible to obtain a much simpler structure, in particular because it is generally easier to obtain stable and precise references in current rather than in voltage.

 Advantageously, the structure of the converter of the invention is a series structure, which intrinsically limits consumption.

Finally, the structure of the converter of the invention makes it possible to obtain directly, with the digital outputs of the conversion stages, coding in code
Gray. This is particularly advantageous.

 As claimed, the invention therefore relates to an analog / digital converter of an input current presented in a first range symmetrical with respect to zero. This converter comprises at least one conversion stage comprising means for detecting the sign of the input signal, and delivering a digital signal corresponding to the sign.

 Advantageously, the analog / digital converter comprises N stages of cascade conversion, the input signal of each stage being obtained by rectifying the current of the preceding stage and by adding to it the half-amplitude of the range of the preceding stage .

 Each conversion stage delivers a bit corresponding to the sign of the input signal applied to it. The N bits obtained thus directly form coding in Gray code.

The invention also relates to an analog / digital conversion method which consists of
a) - to put an input current in a range symmetrical with respect to zero and of amplitude IM;
b) - detecting the sign of this input current and delivering a corresponding digital signal;
c) - to rectify the input current;
d) - to add to the rectified current, the half-amplitude of the range of the input current;
e) - to start again (Nl) once operations b), c) and d), to have directly from the digital signals obtained a coding of the current in code
Gray on N bits.

Other characteristics and advantages of the invention are presented in the following description, given by way of non-limiting illustration of the invention and with reference to the appended drawings in which
- Figure 1 is a block diagram of a converter
analog / digital comprising six stages according to
the invention;
- Figure 2 shows the input currents of
each stage of the converter of figure 1, for
a converter input current between
+ IM;
- Figure 3 shows the digital outputs
corresponding for each of the floors;
- Figure 4 shows an electrical diagram of a
converter according to the invention;
- Figures 5a and 5b show the different
analog input and output signals (a) and
the digital outputs (b) of the diagram in figure
4, depending on the input current IeO of the conver
weaver;
- Figures 6a and 6b show a first (a) and
a second (b) bias circuits of a
converter according to the invention;
- Figure 7 shows a block diagram of a
circuit for converting Gray code to binary,
placed at the output of the converter of the invention;
- Figure 8 shows an electrical diagram of a
differential voltage conversion circuit
towards a bi-directional current, to be placed in front of the
converter according to the invention; and
- Figure 9 is a voltage / current diagram
corresponding to the circuit of figure 8.

FIG. 1 represents a block diagram of an analog / digital converter according to the invention. We chose to represent a 6-bit resolution converter. This converter then comprises six stages
E0 to E5 cascaded.

 The first stage E0 receives the current to be converted, denoted IeO. It delivers an output current IsO and a digital signal G5.

The second stage El receives an input current Iel equal to the output current IsO of the preceding stage increased by a reference current 10. It delivers an output current Isl and a digital signal G4. The stages E2, E3, E4 are identical to the stage El. They respectively receive an input current Ie2 = Isl + Il,
Ie3 = Is2 + I2, Ie4 = Is3 + I3, where I1, I2 and I3 are reference currents and output a current Is2, Is3, Is4 and a digital signal G3, G2, G1. Finally, the last (sixth) stage E5 receives an input current
Ie5 equal to the output current Is4 of the previous stage E4, increased by a reference current I4.It outputs the digital signal GO.

 According to the invention, the input currents IeO to Ie5 are in a current range symmetrical with respect to zero. In addition, between each stage, the amplitude of the range of the input current is halved. This is what is shown in Figure 2. The current IeO thus has a value between -IM and + IM. The current Iel therefore has a value between -IM / 2 and + IM / 2. The current Ie2 has a value between -IM / 4 and + IM / 4 and so on, up to Ie5 which has a value between -IM / 32 and + IM / 32. The digital signal (G5-G0) delivered by each of the stages corresponds to the sign of the input current of each of the stages with respect to zero.

 We have taken as a convention that, when the current is negative, the digital signal is equal to zero at output and when it is positive, it is equal to 1. We then obtain digital outputs G5-G0 according to the current to be converted IeO represented at figure 3.

 The analog / digital converter according to the invention thus makes it possible, by cascading conversion stages each determining the sign of its input current, to obtain at output a digital coding corresponding to the Gray code. This leads to a definite advantage, since the Gray code is that which allows the least possible conversion error, in particular in the middle of the scale, since a single bit changes between two consecutive digital values. And this is obtained in the invention, by simply taking the outputs of the stages of the analog / digital converter.

 We will now describe an electrical diagram of a stage of the converter according to the invention, with reference to FIG. 4. In the following, we have chosen to describe a bipolar structure of the converter of the invention. This description can easily be transposed for a structure in other technologies, such as for example in MOS. In particular, it will be noted that the conduction electrodes of a bipolar transistor will be called emitter (reference e) and collector (reference c) and that the control electrode will be called base (reference b). In technology, MOS, for example, we would speak of source and drain for the conduction electrodes, and of grid for the control electrode.

As regards the conduction threshold voltages, it is generally noted Vbe in bipolar and
Vt in MOS technology.

 In the following, we will use the vocabulary reserved for bipolar technology.

 A conversion stage E0 comprises a transistor T1 whose base bl is connected to a fixed potential P0. Its transmitter el is connected to the entry point E of stage E0.

A transistor T2 is mounted as a diode with its base b2 and its collector c2 joined together at the entry point E.

Its emitter e2 is connected to the collector c4 of a transistor T4. The emitter e4 of this transistor is connected to a resistor Re, the other terminal of which is biased at a fixed potential Q0.

A transistor T5 is mounted as a diode with its collector c5 and its base b5 joined together at the base b4 of the transistor T4. Its emitter e5 is connected to a resistor R'e, the other terminal of which is connected to the fixed potential Q0. The collector c5 is further connected to the emitter e3 of a transistor T3. The base b3 of this transistor is connected to the base b2 of the transistor
T2. Finally, the collectors cl of the transistor T1 and c3 of the transistor T3 are joined together and deliver the output IsO of the stage E0. The transistors T2 and T3 thus form a current mirror. The entire structure composed by the transistors T2, T3, T4 and T5 forms a Wilson mirror. Preferably, the resistances Re and R'e are identical.

The conversion stage further comprises a voltage level comparator 101 receiving on one input the input point E of the stage E0 and on the other input a voltage reference Ref 0. This comparator 101 delivers the digital output G5 of the conversion stage
E0.

The transistors T1, T2 and the comparator 101 make it possible to detect the sign of the input current IeO applied to the input E. In fact, the potentials P0 and
Q0 are such that when the current IeO is positive, the voltage VE at point E increases and, as a result, the base-emitter voltage of transistor T1 decreases. The transistor T1 will block. The voltage VE reaches a high potential denoted VH.

 On the contrary, if the input current IeO is negative, the voltage VE at point E decreases and the base-emitter voltage of transistor T1 increases. The transistor T1 turns on. The voltage VE reaches a low potential denoted VL. The comparator receives a reference voltage RefO between the levels VL and VH.

thus, when the current is positive, the voltage VE is greater than the reference voltage Ref0, the comparator detects a positive sign and the digital output signal G5 is equal to 1. When the current is negative, the voltage VE is less than the voltage Ref 0, the comparator detects a negative sign and the digital output signal G5 is 0.

 We have just described the detection of the input current IeO. We will now describe how the input current IeO, which is in a range symmetrical with respect to zero and of amplitude IM, is transformed into a symmetrical range of lower half-amplitude.

The conversion stage EO therefore includes a current rectifier for copying the input current IeO, either by the transistor T1 when it is negative, or by the transistor T3 when it is positive. The rectifier mainly comprises a current mirror formed by the transistors T2 and T3.

 When the current IeO is negative, we have seen that the transistor T1 is conducting. It has a voltage equal to its conduction threshold Vbe between its transmitter and its base.

The potentials PO and QO are such that the voltage difference VE-QO is then insufficient for the transistor T3 to be conducting. It is sufficient for the base-emitter voltage of the transistor T3 to be less than the conduction threshold voltage Vbe. Under these conditions, the transistor T3 is blocked and all the input current
The negative IeO passes through the transistor T1 (except for the basic current). We therefore obtain, at the output, the current
IsO = IeO.

 When the current IeO is positive, the transistor T1 is blocked. The potentials PO and QO are such that the voltage difference VE-QO is sufficient to make transistor T3 pass. The positive current IeO is then copied by the transistor T2 into the transistor T3 (current mirror). We then find a current -IeO on the collector c3 of the transistor T3. The output current IsO is therefore equal to -IeO.

 There is thus an output current IsO which, in general terms is written: IsO = -IIeOl. The input current is rectified.

 The value of the current IsO as a function of the input current IeO is shown in Figure Sa.

 To improve the copying of the current by the current mirror formed by the transistors T2 and T3, it is preferable to add the transistors T4 and T5. A so-called Wilson mirror is thus obtained which compensates for the effects of Early in the transistor T3 and of base current in the transistor T2, to ensure the best possible copying.

 Under these conditions, the positive current feedback branch comprises two transistors T3 and T5. the negative current copying branch comprises a single transistor T1.

For correct operation of the rectifier, the potentials PO and QO must be such that PO-QO is at least equal to twice Vbe and less than three times Vbe where Vbe is the conduction threshold voltage of the bipolar transistor. Preferably, we choose
PO-QO = 2Vbe. Indeed, when the current is negative, there is then PO-VE = 1Vbe and VE-QO = lVbe, which ensures that the transistors T3 and T5 are blocked.

 When the current is positive, the transistor T1 is blocked, the voltage VE is then equal to PO. We then have VE-QO = PO-QO = 2Vbe which is sufficient for the transistors T3 and T5 to be on and copy the positive current.

 Under these conditions, the voltage VE will have a high value VH equal to 2Vbe and a low value VL equal to lVbe.

 Preferably, it is chosen that the reference voltage RefO of the comparator which must be between VH and VL is equal to RefO = PO-2 / 3Vbe. There is thus an optimal value for detecting the polarity of the input current.

 The output current IsO is a negative rectified current which therefore varies between 0 and -IM: the amplitude is divided by 2 with respect to the input current. But it must be put back in a symmetrical range with respect to zero. To do this, simply add the half-amplitude of the range of the input current IeO. An output current is obtained in the + IM / 2 range. The input current Iel of stage El is therefore the sum of the output current IsO of the preceding stage EO and a reference current IO equal to IM / 2 delivered by a circuit 200 for generating currents.

 In this way, the conversion stages of the converter are cascaded. Each time, the half-amplitude of the range of the input current of this stage is added at the output of the stage.

 The analog / digital converter of the invention therefore includes a current generation circuit referenced 200 in FIG. 4.

This current generation circuit 200 must deliver a current IO = IM / 2, a current I1 = I0 / 2, a current I2 = I1 / 2, a current I3 = I2 / 2, and a current
I4 = I3 / 2.

It includes, for each current reference to be delivered, a network of series or parallel resistors (RO, R1, R2), mounted between the supply voltage
VCC and the transmitter of one or more bipolar transistors (T10, T20, T30, T40, T50). The reference currents are delivered on the collectors of these transistors.

 The base voltage of these transistors is delivered by a voltage reference circuit 201. All the transistors are therefore biased on their base in the same way.

 The resistance networks are calculated to have the best possible proportionality between these reference currents because any error in proportion will reduce the precision of the converter.

The circuit 200 shown in FIG. 4 gives an example of a configuration of resistors and transistors for an amplitude of the input current IeO of two milliamps and a supply voltage VCC of 9 volts. The current IO is thus delivered on the common collectors of 4 transistors of which only one (T10) has been shown, mounted in parallel. A network of resistors is placed between the supply voltage
VCC and the transmitters common to the four transistors.

 The collector (s) of the transistors of the current generation circuit 200 are connected, for each reference current, to the common collectors of the transistors T1 and T3 of the corresponding conversion stage, which thus makes it possible to add the currents .

 FIG. Sa represents the output current of IsO of the first stage EO and the input current Iel of the stage El which follows, as a function of the input current IeO of the analog / digital converter.

 FIG. 5b represents the corresponding digital outputs G5 and G4 as a function of the input currents IeO and Iel.

 We have seen in the description of the conversion stages, that the detection of the sign required different polarization voltages denoted QO, RefO and PO for the first stage EO.

 We will now describe a particularly compact bias circuit which generates these voltage references for each of the stages.

 In FIG. 6a, the first three stages EO, El and E2 have thus been represented.

- The EO stage receives the QO, RefO voltages as input
and PO.

- The stage El receives the input voltages Q1, Refl
and P1.

 - Stage E2 receives input Q2, Ref2 and P2 as input.

We have seen, according to the invention, that there was, for each stage Ei 2Vbe çPi-Qi <3Vbe with, preferably, Pi - Qi = 2Vbe and Refi = Pi - 2 / 3Vbe.

 The voltage reference circuit according to the invention comprises a first bias line comprising diodes in series, 3, 6, 9, 12, directly biased by a current generator 300.

 In parallel on this first line of polarization is placed a second line of polarization comprising resistors. These resistances are such that between each diode respectively 3, 6, 9, 12, there is in parallel a resistance respectively 1, 4, 7, 10, of value R and a resistance respectively 2, 5, 8, 11, of value 2R. As the diodes are direct, we find at the terminals of each of them a voltage equal to the conduction threshold voltage Vbe.

The resistive bridge placed in parallel therefore makes it possible to obtain 1/3 or 2/3 of Vbe. For example, depending on whether you take the voltage between the cathode of diode 6 and the midpoint between resistors 4 (R) and 5 (2R) or between the anode of diode 6 and this same midpoint. The values of the bias voltages are thus very easily obtained, each of these voltages being offset by 1Vbe between each stage.

 Thus, the voltage QO is taken at the common point between the cathode of the diode 3 and the resistance 1 of value R.

 The reference RefO is taken between the resistor 4 of value R and the resistor 5 of value 2R, these two resistors in series being in parallel on the diode 6.

 The reference PO is taken at the common point between the resistor 5 and the anode of the diode 6.

 We thus obtain an offset of 2Vbe between QO and PO and of 213 Vbe between PO and RefO.

 The voltage Q1 of the stage El is taken at the common point between the resistor 4 of value R and the cathode of the diode 6.

 The reference Refl is taken between the resistor 7 of value R and the resistor 8 of value 2R which are placed in parallel on the diode 9.

 Voltage P1 is taken between resistor 8 of value 2R and the anode of diode 9.

We thus obtain an offset of lVbe between QO and
Q1, 1 Vbe between RefO and Refl and ivbe between PO and P1: Q1 = QO + Vbe; Refl = RefO + Vbe; P1 = PO + Vbe.

 This is not a problem, since it is the potential differences (P1-Q1, Pl-Refl) which must be constant for a given stage (El).

 This bias circuit structure has its limits since it cannot generate more than the supply voltage of the converter VCC, which is for example 9 volts, Vbe being approximately 0.7 volt.

 But insofar as the converter which interests us is of low resolution comprising at most six to seven stages of conversion, this bias circuit is very advantageous since it comprises only two bias lines supplied by the same current generator 300. This structure is particularly simple and makes it possible to limit the consumption of current.

 Another embodiment of the voltage bias circuit is shown in Figure 6b. The second resistance bias line has been replaced by a second diode bias line 13,14,15,16.

Each diode bias line is biased by a common current generator 301. On the first polarization line is placed a resistor R 'in series between the current generator 301 and the diodes.

On the second bias line is placed a resistor KR 'in series between the voltage Vcc and the diodes. There is thus the potential QO on the cathode of the first diode 13 of the second polarization line, the potential Q1 on the cathode of the second diode 14 of the second polarization line, the potential PO on the anode of this same second diode, the potential
Q2 on the cathode of the third diode 15 and the potential P1 on the anode of this third diode. We have the potential RefO on the anode of the first diode 3 of the first polarization line, the potential Refl on the anode of the second diode 6 of the first polarization line and so on. The resistance R 'is calculated so that the potential RefO is offset by 1/3
Vbe with respect to the potential QO. The constant K is calculated to have an identical current IP in the two branches, so that the diode voltage is identical. The different voltage references are thus obtained with the appropriate offsets.

 The conversion stages of the analog / digital converter and the bias circuits (current, voltage) according to the invention have thus been described. We have seen that this converter directly outputs the Gray code conversion of the input signal.

 However, if the Gray code is very advantageous from the point of view of conversion, since it limits the conversion errors, it is unusable for the digital processing of these signals. In practice, therefore, a Gray to binary converter must be placed at the output.

 In one example, the voltage levels of the Gray code bits delivered by the comparators are equal to a reference voltage REF + 125 millivolts and this reference voltage REF is of the order of 2 to 2.5 volts. These voltage levels correspond to the levels used in binary technology with emitter coupling, noted ECL (Emitter Coupled Logic) in Anglo-Saxon literature.

 It is proposed here to place at the output of the analog / digital converter, a converter of Gray code into binary code in ECL technology.

 This Gray / binary code converter represented in FIG. 7 mainly comprises six comparators 30 to 35 with storage register 40 to 45 and at the output of registers 41 to 45, five XOR logic gates 51 to 55.

Register 40 directly delivers the output in binary
B5, and its complement / B5. The XOR circuits 51 to 55 deliver the outputs in binary B1 to B5, and their complements / B1 to / B5.

The comparators with storage register make it possible to store each of the bits of the Gray code G5 to GO. They receive the reference voltage REF (Gi =
REF + 125mv). They deliver for each bit Gi, the logic levels gi and their complements / gi.

 In known manner, the most significant bit G5 is equal to the most significant bit B5 in binary.

For all the other bits, the logical conversion consists in presenting the bit of weight (g5) immediately higher and its complement (/ g5) and the bit to be converted (g4) and its complement (/ g4) on the logic gate XOR (51 ) to deduce the corresponding bit in binary (B4) and its complement (/ B4).

In the example shown, the binary bits B5 to BO and their complements / B5 to / BO are then output. We can then change the voltage levels to switch to other technologies. For example (figure 7), we will use a technology circuit
ECL to CMOS technology, that is to say we will go from a voltage level between 2 and 2.5 volts to a voltage level between 0 and 5 volts.

This circuit will not be detailed further.

 Preferably, a Gray / binary conversion circuit with vertical structure will be used (FIG. 7) using a clock signal CK and a current generator 302. On the rising edge of the clock CK, the output of the current generator is switched to the comparator which establishes the logical output levels.

On the falling edge of the clock CK, the output of the current generator is switched to the storage registers which store the outputs of the comparators and these stored levels are directly converted into series by the logic gates. Thus, a single current generator 302 makes it possible to do all the operations vertically. This structure is particularly advantageous in consumption and also on the surface since it is very dense.

 In many applications, including video signal processing applications, the converted signals are not currents but voltages.

More specifically, television signals are differential signals. To use a converter according to the invention, it is therefore necessary to place in front of the analog / digital converter, a circuit for converting a differential voltage to a bidirectional current.

 Such a circuit is shown in FIG. 8. It comprises a differential circuit consisting of two transistors T6 and T7, the emitters of which are each connected by a resistor RP to a current generator 63.

The transistor T6 receives on its base b6 the negative pole V- of the differential voltage. The transistor
T7 receives on its base b7 the positive pole of the differential voltage V +.

Another differential circuit comprises a transistor T8 and a transistor T9 whose emitters e8 and e9 are each connected by a resistor RP to a current generator 64. The collector c8 of the transistor
T8 is connected to the input of a current mirror 62. The collector c9 of the transistor T9 is connected to the output of the current mirror 62.

 Between the base b8 of the transistor T8 and the base b9 of the transistor T9, a resistor R4 is placed. The output of the voltage-current converter is taken on the base b9 of the transistors T9.

 The collector c6 of the transistor T6 is connected to the collector c9 of the transistor T9. The collector c7 of the transistor T7 is connected to the collector c8 of the transistor T8.

 The voltage VC at the output node of the current mirror 62 controls a current generator 65 connected to the base b8 of the transistor T8.

 Finally a current generator 66 is placed on the base b8 of the transistor T8.

 The operating principle is as follows: the differential circuits make it possible to copy the difference 6V = V + - V- at the terminals of the resistor R4 by the feedback circuit formed by the second differential circuit (T8, T9) and the generator of current 66. Resistor R4 is calculated to pass from the input voltage range to the output current range. In an example where 6V varies between + 500 millivolts and the input current of the analog / digital converter must be in a range + 2 milliamps, the resistance will be 250 ohms (V = RI). We obtain the curve (1) represented in FIG. 9.

In the case where the input voltage is not in a symmetrical range with respect to zero, a circuit is added on one of the poles of the differential voltage to put this differential voltage back into a symmetrical range. In an example, we place on the pole
V +, a current amplifier 61 connected in series to a resistance terminal R3. A current generator Ir is placed in series on the other terminal of the resistor.

Under these conditions, there is a current Ir which passes through the resistor R3 and which induces a voltage drop
V = R3.Ir. This voltage drop is added to the voltage carried by the positive pole. It follows that the difference 6V between V + and V- is shifted by the same amount.

 In the example where 6V varies between 0 and 1 volt (curve (2) in figure 9), we choose a resistance R3 of 2 Kohms and a current generator Ir of 250 amps. The voltage drop in resistance R3 is then 500 millivolts, which is deduced from 6V. We therefore obtain a differential voltage between -500 and +500 millivolts as shown on the curve (1) in Figure 9.

 The bidirectional differential voltage / current converter described with its feedback provides great precision. This is very important if we do not want to lose resolution bits in the analog / digital conversion that follows. The voltage / current conversion must be as linear as possible.

 The analog / digital converter of the invention thus makes it possible to convert a current in a symmetrical range directly into Gray code. Simple and dense conversion circuits allow this Gray code to be translated into binary code used by digital processing machines. Uncomplicated voltage / current conversion circuits convert the analog voltages that you want to convert into bidirectional current.

 The converter itself has very few elements: a maximum of 6 to 7 stages of simple structure connection and current and voltage bias circuits themselves very simple and very dense.

In an exemplary embodiment of a circuit comprising a differential voltage to bidirectional current converter, the analog / digital converter of the invention and the code converters
Gray / binary and binary ECL / CMOS, this circuit occupies an area approximately four times less important than that of known analog / digital converters. It provides a resolution of six to eight bits at 10 or 15 Megahertz.

Claims (15)

 1. Analog / digital converter, of an analog signal. input in the form of a current (IeO) presented in a first symmetrical range (+ IM) with respect to zero, characterized in that it comprises at least one conversion stage (EO) comprising a means for detecting the sign of this current (IeO) applied to an input (E) of the conversion stage (EO), this means for detecting the sign delivering a corresponding digital signal (G5).  2. Converter according to claim 1, characterized in that a conversion stage (EO) further comprises an input current rectifier (IeO) for delivering an output current (IsO) equal to the inverse of the value absolute of the input current (-iîeoi).  3 converter according to claim 2, characterized in that it comprises N stages of cascade conversion (EO-E5) and a circuit for generating Nl reference currents (IO-I4), the input signal IeO of the first stage (EO) being in the first symmetrical range (+ IM) with respect to zero, the input signal (Iel) of the following stages (El) being equal to the output current (IsO) of the preceding stage (EO) increased a reference current (IO) equal to half the amplitude of the range of the input current of the previous stage.  4. Converter according to claim 3, characterized in that each of the N stages delivers a digital signal corresponding to the sign of the input current of this stage, and that all of these digital signals (G5 and GO) correspond to a coding in code Gray on N bits, the digital signal (G5) delivered by the first stage (EO) being the most significant bit and that (G8) delivered by the last stage being the least significant bit.  5. Converter according to claim 1, characterized in that the means for detecting the sign of the input current of a stage (EO) comprises a first transistor T1 of which a conduction electrode (el) is connected to the input point (E), the control electrode being polarized at a first fixed potential PO, a second transistor (T2) mounted as a diode and in series between the input point (E) and a second fixed potential QO, and a comparator of voltages of which one input (+) is connected to the input point (E) of the stage, the other input (-) being biased to a voltage reference RefO and which delivers, at output, the digital signal (G5) corresponding to the sign of the current (IeO) applied to the entry point (E).  6. Converter according to claim 2, characterized in that the means for detecting the sign of the input current of a stage (EO) comprises a first transistor T1 of which a conduction electrode (el) is connected to the input point (E), the control electrode being polarized at a first fixed potential PO, a second transistor (T2) mounted as a diode and in series between the input point (E) and a second fixed potential QO, and a comparator of voltages of which one input (+) is connected to the input point (E) of the stage, the other input (-) being biased to a voltage reference RefO and which delivers, at output, the digital signal (G5) corresponding to the sign of the current (IeO) applied to the entry point (E).  7. Converter according to claim 6, characterized in that the current rectifier comprises a current mirror formed by the second transistor (T2) and a third transistor T3 of which a conduction electrode (c3) is connected to the other electrode conduction (cl) of the first transistor (T1) and the other conduction electrode (e3) is biased at the second fixed potential QO.  8. Converter according to claim 7, characterized in that the current rectifier comprises a fourth transistor (T4) in series between the second transistor (T2) and the fixed potential QO and a fifth transistor (T5) mounted as a diode, with a conduction electrode (c5) joined to its control electrode (b5), this control electrode (b5) being connected to that of (b4) of the fourth transistor (T4), and the fifth transistor being placed in series between the third transistor (T3) and the fixed potential QO, so that this structure with four transistors forms a mirror of Wilson.  9. Converter according to claim 8, characterized in that the potentials Pi and Qi of a conversion stage are such that: 2Vbe XPi-Qi <3Vbe where Vbe is the conduction threshold voltage of the transistors.  10. Converter according to claim 9, characterized in that the reference voltage Refl, of the comparator of a conversion stage is such that  Refi = Pi - 2/3 Vbe.  11. Converter according to claim 8 or 9 characterized in that the voltages Pi, Qi and Refi of a conversion stage are offset by a threshold voltage Vbe respectively with respect to the voltages Pi-l, Qi-l and Refi-l of the previous stage.  12. Converter according to claim 11, characterized in that the voltages Pi, Qi and Refi of each stage Ei are delivered by a voltage circuit comprising two polarization lines traversed by the same current, a first composed of diodes (3,6 ) in series reverse between the supply voltage VCC and a current generator (300) and a second composed of resistors (1,2,4,5) in series between the supply voltage and the current generator, these resistors grouping into identical groupings (1,2), each grouping (1,2) being placed in parallel on a diode (3) of the first polarization line so as to obtain the ratios 2 / 3Vbe and 2Vbe between the potentials d 'the same stage and an offset of lVbe between the potentials of the same nature of two consecutive stages.  13. Converter according to claim 11, characterized in that the voltages Pi, Qi and Refi of each stage Ei are delivered by a voltage circuit comprising two polarization lines traversed by the same current, a first composed of diodes (3) in reverse series between a resistor of value R 'and a current generator (301) and a second composed of diodes (13) in reverse between a resistor of value KR 'and the current generator, so as to obtain the ratios Vbe and 2 / 3Vbe between the potentials of the same stage and an offset of lVbe between the potentials of the same nature of two consecutive stages.  14. Analog to digital conversion method characterized in that it consists  a) - to put an input current in a range symmetrical with respect to zero and of amplitude IM;  b) - detecting the sign of this input current and delivering a corresponding digital signal;  c) - to rectify the input current;  d) - to add to the rectified current, the half-amplitude of the range of the input current;  e) - to start again (N-l) times operations b), c), d), to have directly from the digital signals obtained a coding of the current in Gray code on N bits.  15. Analog to digital conversion method according to claim 14 of an analog voltage signal, characterized in that operation a) is preceded by an operation of converting the analog voltage signal into a bidirectional current in a symmetrical range d amplitude IM.