FR2796492B1 - Methode amelioree pour graver les materiaux tin et sio2 a la meme vitesse - Google Patents
Methode amelioree pour graver les materiaux tin et sio2 a la meme vitesseInfo
- Publication number
- FR2796492B1 FR2796492B1 FR0004852A FR0004852A FR2796492B1 FR 2796492 B1 FR2796492 B1 FR 2796492B1 FR 0004852 A FR0004852 A FR 0004852A FR 0004852 A FR0004852 A FR 0004852A FR 2796492 B1 FR2796492 B1 FR 2796492B1
- Authority
- FR
- France
- Prior art keywords
- improved method
- same speed
- etching tin
- sio2 materials
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000005530 etching Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L2924/01033—Arsenic [As]
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- H01L2924/01057—Lanthanum [La]
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- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/049—Nitrides composed of metals from groups of the periodic table
- H01L2924/0494—4th Group
- H01L2924/04941—TiN
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99480060 | 1999-07-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2796492A1 FR2796492A1 (fr) | 2001-01-19 |
FR2796492B1 true FR2796492B1 (fr) | 2005-05-20 |
Family
ID=8242450
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0004852A Expired - Fee Related FR2796492B1 (fr) | 1999-07-13 | 2000-04-14 | Methode amelioree pour graver les materiaux tin et sio2 a la meme vitesse |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP3418162B2 (fr) |
FR (1) | FR2796492B1 (fr) |
TW (1) | TW463260B (fr) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4405488B2 (ja) * | 2006-08-30 | 2010-01-27 | 株式会社東芝 | 半導体装置及び半導体装置の製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5164330A (en) * | 1991-04-17 | 1992-11-17 | Intel Corporation | Etchback process for tungsten utilizing a NF3/AR chemistry |
US5413669A (en) * | 1994-02-07 | 1995-05-09 | Applied Materials, Inc. | Metal CVD process with post-deposition removal of alloy produced by CVD process |
US5550399A (en) * | 1994-11-03 | 1996-08-27 | Kabushiki Kaisha Toshiba | Integrated circuit with windowed fuse element and contact pad |
JP3440599B2 (ja) * | 1995-01-24 | 2003-08-25 | 松下電器産業株式会社 | ビアホール形成方法 |
-
2000
- 2000-04-14 FR FR0004852A patent/FR2796492B1/fr not_active Expired - Fee Related
- 2000-06-28 TW TW089112734A patent/TW463260B/zh not_active IP Right Cessation
- 2000-07-11 JP JP2000209902A patent/JP3418162B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP3418162B2 (ja) | 2003-06-16 |
TW463260B (en) | 2001-11-11 |
JP2001060586A (ja) | 2001-03-06 |
FR2796492A1 (fr) | 2001-01-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20081231 |