FR2773238B1 - Circuit de bus - Google Patents

Circuit de bus

Info

Publication number
FR2773238B1
FR2773238B1 FR9813860A FR9813860A FR2773238B1 FR 2773238 B1 FR2773238 B1 FR 2773238B1 FR 9813860 A FR9813860 A FR 9813860A FR 9813860 A FR9813860 A FR 9813860A FR 2773238 B1 FR2773238 B1 FR 2773238B1
Authority
FR
France
Prior art keywords
bus circuit
bus
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9813860A
Other languages
English (en)
Other versions
FR2773238A1 (fr
Inventor
Fumihiko Sakamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2773238A1 publication Critical patent/FR2773238A1/fr
Application granted granted Critical
Publication of FR2773238B1 publication Critical patent/FR2773238B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G06F13/4077—Precharging or discharging

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
FR9813860A 1997-11-05 1998-11-04 Circuit de bus Expired - Fee Related FR2773238B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30229097A JP3299151B2 (ja) 1997-11-05 1997-11-05 バス入出力回路及びそれを用いたバス入出力システム

Publications (2)

Publication Number Publication Date
FR2773238A1 FR2773238A1 (fr) 1999-07-02
FR2773238B1 true FR2773238B1 (fr) 2003-01-10

Family

ID=17907220

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9813860A Expired - Fee Related FR2773238B1 (fr) 1997-11-05 1998-11-04 Circuit de bus

Country Status (3)

Country Link
US (1) US6150846A (fr)
JP (1) JP3299151B2 (fr)
FR (1) FR2773238B1 (fr)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6686774B1 (en) * 2001-07-19 2004-02-03 Raza Microelectronics, Inc. System and method for a high speed, bi-directional, zero turnaround time, pseudo differential bus capable of supporting arbitrary number of drivers and receivers
US6806737B2 (en) * 2002-03-21 2004-10-19 Raymond Jit-Hung Sung Bi-directional amplifier and method for accelerated bus line communication
US7196942B2 (en) * 2004-10-20 2007-03-27 Stmicroelectronics Pvt. Ltd. Configuration memory structure
DE102006030114B4 (de) * 2006-06-28 2010-09-09 Phoenix Contact Gmbh & Co. Kg Sichere Eingangsschaltung mit einkanaligem Peripherieanschluss für den Eingang eines Busteilnehmers

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158317A (ja) * 1984-08-30 1986-03-25 Nec Corp 内部バス回路
JPH01211014A (ja) * 1988-02-19 1989-08-24 Hitachi Ltd バス駆動方式および正帰還回路
JPH02135817A (ja) * 1988-11-16 1990-05-24 Mitsubishi Electric Corp プリチャージ方式バス回路のための放電回路
JPH02306325A (ja) * 1989-05-19 1990-12-19 Mitsubishi Electric Corp 双方向バッファ回路
JPH0374722A (ja) * 1989-08-16 1991-03-29 Matsushita Electric Ind Co Ltd バス回路
US5148047A (en) * 1990-06-11 1992-09-15 Motorola, Inc. CMOS bus driver circuit with improved speed
US5115150A (en) * 1990-11-19 1992-05-19 Hewlett-Packard Co. Low power CMOS bus receiver with small setup time
US5248905A (en) * 1990-12-28 1993-09-28 National Semiconductor Corporation High speed, master/slave latch transceiver having a directly-driven slave stage
US5189319A (en) * 1991-10-10 1993-02-23 Intel Corporation Power reducing buffer/latch circuit
JP3625881B2 (ja) * 1994-12-20 2005-03-02 株式会社ルネサステクノロジ バスシステム及びバスセンスアンプ
US5661675A (en) * 1995-03-31 1997-08-26 Intel Corporation Positive feedback circuit for fast domino logic
US5831451A (en) * 1996-07-19 1998-11-03 Texas Instruments Incorporated Dynamic logic circuits using transistors having differing threshold voltages
US5856752A (en) * 1996-09-13 1999-01-05 Hewlett-Packard Company Driver circuit with precharge and active hold
US5942917A (en) * 1997-12-29 1999-08-24 Intel Corporation High speed ratioed CMOS logic structures for a pulsed input environment

Also Published As

Publication number Publication date
FR2773238A1 (fr) 1999-07-02
US6150846A (en) 2000-11-21
JP3299151B2 (ja) 2002-07-08
JPH11143599A (ja) 1999-05-28

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090731