FR2728102A1 - Procede de fabrication de transistors mos de circuit integre - Google Patents

Procede de fabrication de transistors mos de circuit integre Download PDF

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Publication number
FR2728102A1
FR2728102A1 FR9415019A FR9415019A FR2728102A1 FR 2728102 A1 FR2728102 A1 FR 2728102A1 FR 9415019 A FR9415019 A FR 9415019A FR 9415019 A FR9415019 A FR 9415019A FR 2728102 A1 FR2728102 A1 FR 2728102A1
Authority
FR
France
Prior art keywords
layer
conductive material
regions
field oxide
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9415019A
Other languages
English (en)
French (fr)
Other versions
FR2728102B1 (enrdf_load_stackoverflow
Inventor
Philippe Gayet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics SA
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA, SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics SA
Priority to FR9415019A priority Critical patent/FR2728102A1/fr
Publication of FR2728102A1 publication Critical patent/FR2728102A1/fr
Application granted granted Critical
Publication of FR2728102B1 publication Critical patent/FR2728102B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H10D84/014—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
FR9415019A 1994-12-08 1994-12-08 Procede de fabrication de transistors mos de circuit integre Granted FR2728102A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9415019A FR2728102A1 (fr) 1994-12-08 1994-12-08 Procede de fabrication de transistors mos de circuit integre

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9415019A FR2728102A1 (fr) 1994-12-08 1994-12-08 Procede de fabrication de transistors mos de circuit integre

Publications (2)

Publication Number Publication Date
FR2728102A1 true FR2728102A1 (fr) 1996-06-14
FR2728102B1 FR2728102B1 (enrdf_load_stackoverflow) 1997-02-28

Family

ID=9469775

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9415019A Granted FR2728102A1 (fr) 1994-12-08 1994-12-08 Procede de fabrication de transistors mos de circuit integre

Country Status (1)

Country Link
FR (1) FR2728102A1 (enrdf_load_stackoverflow)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0357205A1 (en) * 1988-07-28 1990-03-07 Fujitsu Limited Polishing liquid for polishing semiconductor substrate and polishing process
EP0429404A2 (en) * 1989-10-24 1991-05-29 STMicroelectronics S.r.l. A process for forming a field isolation structure and gate structure in integrated MISFET devices
US5030584A (en) * 1988-10-06 1991-07-09 Nec Corporation Method for fabricating MOS semiconductor device operable in a high voltage range using polysilicon outdiffusion
US5183771A (en) * 1989-01-07 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing lddfet having double sidewall spacers
JPH06181310A (ja) * 1992-12-15 1994-06-28 Mitsubishi Electric Corp 半導体装置の製造方法
US5346587A (en) * 1993-08-12 1994-09-13 Micron Semiconductor, Inc. Planarization of a gate electrode for improved gate patterning over non-planar active area isolation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0357205A1 (en) * 1988-07-28 1990-03-07 Fujitsu Limited Polishing liquid for polishing semiconductor substrate and polishing process
US5030584A (en) * 1988-10-06 1991-07-09 Nec Corporation Method for fabricating MOS semiconductor device operable in a high voltage range using polysilicon outdiffusion
US5183771A (en) * 1989-01-07 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing lddfet having double sidewall spacers
EP0429404A2 (en) * 1989-10-24 1991-05-29 STMicroelectronics S.r.l. A process for forming a field isolation structure and gate structure in integrated MISFET devices
JPH06181310A (ja) * 1992-12-15 1994-06-28 Mitsubishi Electric Corp 半導体装置の製造方法
US5346587A (en) * 1993-08-12 1994-09-13 Micron Semiconductor, Inc. Planarization of a gate electrode for improved gate patterning over non-planar active area isolation

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"IMPROVED ISOLATION AND GATE LEVEL FORMATION PROCESS", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 34, no. 11, 1 April 1992 (1992-04-01), pages 197 - 199, XP000303235 *
PATENT ABSTRACTS OF JAPAN vol. 018, no. 518 (E - 1612) 29 September 1994 (1994-09-29) *

Also Published As

Publication number Publication date
FR2728102B1 (enrdf_load_stackoverflow) 1997-02-28

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Effective date: 20060831