FR2722639B1 - METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK - Google Patents

METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK

Info

Publication number
FR2722639B1
FR2722639B1 FR9408858A FR9408858A FR2722639B1 FR 2722639 B1 FR2722639 B1 FR 2722639B1 FR 9408858 A FR9408858 A FR 9408858A FR 9408858 A FR9408858 A FR 9408858A FR 2722639 B1 FR2722639 B1 FR 2722639B1
Authority
FR
France
Prior art keywords
link
elextric
wafer
establishing
electronic card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9408858A
Other languages
French (fr)
Other versions
FR2722639A1 (en
Inventor
Michel Gaumet
Alain Larchevesque
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Solaic SA
Original Assignee
Solaic SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Solaic SA filed Critical Solaic SA
Priority to FR9408858A priority Critical patent/FR2722639B1/en
Publication of FR2722639A1 publication Critical patent/FR2722639A1/en
Application granted granted Critical
Publication of FR2722639B1 publication Critical patent/FR2722639B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
FR9408858A 1994-07-18 1994-07-18 METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK Expired - Fee Related FR2722639B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9408858A FR2722639B1 (en) 1994-07-18 1994-07-18 METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9408858A FR2722639B1 (en) 1994-07-18 1994-07-18 METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK

Publications (2)

Publication Number Publication Date
FR2722639A1 FR2722639A1 (en) 1996-01-19
FR2722639B1 true FR2722639B1 (en) 1996-08-30

Family

ID=9465478

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9408858A Expired - Fee Related FR2722639B1 (en) 1994-07-18 1994-07-18 METHOD FOR ESTABLISHING AN ELEXTRIC LINK BETWEEN TWO PRINTED CIRCUITS LOCATED ON THE OPPOSITE FACES OF A WAFER, AND ELECTRONIC CARD COMPRISING SUCH A LINK

Country Status (1)

Country Link
FR (1) FR2722639B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0805614B1 (en) * 1995-11-17 2005-04-13 Kabushiki Kaisha Toshiba Multilayered wiring board, prefabricated material for multilayered wiring board, process of manufacturing multilayered wiring board, electronic parts package, and method for forming conductive pillar
JP3867523B2 (en) 2000-12-26 2007-01-10 株式会社デンソー Printed circuit board and manufacturing method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4383363A (en) * 1977-09-01 1983-05-17 Sharp Kabushiki Kaisha Method of making a through-hole connector
DE3372054D1 (en) * 1982-11-15 1987-07-16 Storno As A method of making a double-sided thick-film integrated circuit
JPH01228196A (en) * 1988-03-08 1989-09-12 Sharp Corp Manufacture of printed wiring board
JP2610036B2 (en) * 1988-07-23 1997-05-14 北陸電気工業 株式会社 Circuit board

Also Published As

Publication number Publication date
FR2722639A1 (en) 1996-01-19

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Legal Events

Date Code Title Description
ST Notification of lapse