FR2694425A1 - Decoder and method for decoding variable length codes. - Google Patents

Abstract

A set of variable length codes are classified into a set of groups based on a predetermined bit string of each code. An address space of a table memory (21a) is divided into a set of blocks which respectively correspond to the groups. A block selection circuit (22) selects any one of the blocks on the basis of the predetermined bit string (B0-B5) of the variable length code applied thereto. A bit selector (23) responds to an output signal of the block selection circuit (22) by applying to the table memory (21a), as an address signal, the corresponding bit string of the length code variable that is applied.

Description

DECODER AND METHOD FOR DECODING CODES

VARIABLE LENGTH

  The present invention relates to a decoder with

  variable length, and in particular a long decoder

  variable feed designed to decode length codes

  variable by consulting a table.

  A high-performance image coding system has been used in image processing to compress the data volume by the use of redundancy of image signals. In this high-performance coding system, processing is carried out. length coding

  variable to further reduce the volume of data

  Variable length coding reduces total volume

  codes by assigning codes with short lengths

  data feeders to input data whose frequency of appearance is statistically high, and by assigning codes having long data lengths to input data whose frequency of appearance is

statistically weak.

  Figure 17 shows a structure of a dispo-

  sitive for coding image data, and Figure 18 shows a structure of a device for decoding

compressed image data.

  In FIG. 17, a Discrete Cosine Transformation (or DCT) processing device 100 applies a discrete cosine transformation processing (or DCT processing) to image data, to provide a discrete cosine transform coefficient from -of this data The discrete cosine transform coefficient corresponds to a spatial frequency component of the image This discrete cosine transformation processing extracts a spatial redundancy from the image data A quantizer 200 quantifies the dicrete cosine transform coefficient for provide an index of

  quantification which consists of long data

  fixed duration The extracted redundancy is thus eliminated A

  variable length encoder 300 codes the quantification index

  cation consisting of fixed length data, to form variable length codes Image data

compressed are thus obtained.

  In FIG. 18, a decoder of varying length

  ble 400 decodes the compressed data which is represented

  variable length codes, to provide the fixed length data, and it applies them as a quantification index An inverse quantifier 500

  apply inverse quantization to the quantification index

  cation to provide the discrete cosine transform coefficient, which corresponds to the spatial frequency component of the image A device for processing in inverse dicrete cosine 600 applies an orthogonal transformation treatment (inverse discrete cosine transformation treatment) to the coefficient of transform in discrete cosine, to reproduce the

image data.

  In the image decoding processing which is described above, the variable length decoder 400 is used to decode the compressed data which are constituted by the variable length codes, for

  provide the quantification index constituted by the data

born of fixed length.

  FIG. 19 is a block diagram showing a structure of a variable length decoder of the prior art This variable length decoder accomplishes the

  decoding processing by means of a consultation operation

table tation.

  A variable length code input circuit receives a variable length code which is transmitted in series by a signal line L1 The variable length code input circuit 10 converts the length code

  variable, which is applied in series, in a long code

  variable length in a parallel format, and it applies the variable length code parallel to an input terminal

  address A of a decoding table 20, via

  diary of a signal line L 2 The input circuit of

  variable length code 10 applies a com-

  requests CNT to decoding table 20 via

a signal line L 5.

  The decoding table 20 reacts to the com-

  commands CNT by decoding the variable length code and by applying the fixed length data to a signal line L 3, via its data output terminal D Simultaneously with this operation, the table

  decoding 20 applies the code length of the long code

  variable length at length code input circuit

  variable 10, via a signal line L 4.

  The signal line L 2 has a signal line width which corresponds to the maximum code length of the

variable length.

  FIG. 20 shows the decoding table which is contained in the variable-length decoder of the prior art The decoding table 20 comprises a table memory 21 in which a correspondence table is recorded which is represented in FIG. 21 This table of correspondence represents the correspondence between variable length codes, fixed length codes

  and code lengths of variable length codes.

  We will generally call code information the data of fixed length and the code lengths of

  corresponding variable length codes.

  In practice, each piece of code information comprising the fixed length data and the code length is stored at the address which is indicated by the corresponding variable length code in

  the address space of the table memory 21.

  For example, at addresses "l XXXXXXXXXX" are

  recorded the fixed length data "O" and the long

  code code "1", and at the addresses "011 XXXXXXXX" are

  the fixed length data "1" and the long

  variable variable "3" "X" here represents "O" or "1" The fixed length data "32" and the code length "11"

  are registered at the address "00000011000" In the example

  ple of Figure 21, the maximum code length of

  variable length codes equals 11.

  The table memory 21 in FIG. 20 receives the parallel variable length code as an address signal, via the signal line L 2, having a signal line width of 11 bits When the code of variable length which is received has a code length shorter than the maximum code length, one or more higher order bits, which correspond to the variable length code applied, among the 11 bits AO-A 10 of the address signal , are valid bits, and the remaining bit (s), i.e. one or more bits

  of lower order, are invalid bits.

  For example, if the variable length code is "1", only the higher order bit AO of the address signal is the valid bit, and the ten lower order bits Al-A 10 are invalid bits If the variable length code is "011", the three higher order bits AO, Ai and A 2 of the address signal are the valid bits, and the

  the remaining eight bits A 3-A 1 O are invalid bits.

  Therefore, to obtain correct code information corresponding to the variable length code that is applied, regardless of the value of the bits

  invalid, it is necessary to record the same information

  code mation to all addresses, which are common

  to valid higher order bits, in the address space

table memory 21.

  For example, fixed length data "O" and

  a code length "1" is stored in 2 addresses

  its "10000000000", "10000000001", and "11111111111".

  Fixed length data "1" and code length "3" are stored at the 28 addresses "01100000000",

  "01100000001", and "01111111111" Long data

  fixed length "32" and a code length "11" are saved

  entered at an address "00000011000".

  An example of the operation of the decoder to be described below, with reference to FIG. 22

variable length of figure 19.

  By way of example, a variable length code "1001101100000111" is applied in series by the signal line L 1 to the variable length code input circuit 10 The variable length code input circuit 10 applies in parallel to the higher-order 11-bit decoding table "10011011000" of the serial variable length code, as an address signal The decoding table 20 reacts to the control signal CNT by reading the data of fixed length "O" and the code length "1" at the address "10011011000" in the memory of

  table 21 (figure 20) The code length "1" is applied

  via signal line L 4 to code input circuit

of variable length 10.

  The variable length code input circuit abandons the first bit "1" in the serial variable length code, based on the code length "1", and applies the following 11 bits in parallel "00110110000"

  to the decoding table 20, as an address signal.

  Under the effect of the control signal CNT, the decoding table 20 reads the data of fixed length "3" and the code length "4" at the address "0011011000" in the table memory 21 The code length " 4 "is applied by signal line L 4 to the code input circuit of

variable length 10.

  The variable length code input circuit abandons the 4 higher order bits "0011" in the

  variable length code series, based on length

  code code "4", and it applies in parallel to the decoding table 20 the following Il bits "0110000011 l" as an address signal The decoding table 20 reacts to the control signal CNT by reading the length data sets "1" and -code length "3" to address

  "01100000111" in table memory 21.

  In this way, the fixed length data and the code lengths corresponding to the variable length codes are supplied sequentially by the decoding table 20, by the consultation operation of

table.

  With the decoding table of the variable length decoder of the prior art, as described above, only some of the bits, i.e. the higher order bits, of the address signal are determined by the code of variable length, in the case of code application

  of variable length whose code length is less than

  less than the maximum code length, and the remaining lower order bits become invalid. It is therefore necessary to store the same code information at a set of addresses in the table memory 21, and by

  therefore additional address space is required.

  If it is assumed that the maximum code length of the variable length codes is N, the table memory 21 requires an address space of 2 N words. For example, in the case of the variable length code which is represented on the Figure 21, the maximum code length is 11 bits, and the number of codes is 33 Despite this, with the structure of the decoding table 20 which is shown in Figure 20, the table memory 21 requires space address space of 2 = 2048 words Therefore, the required address space is very large, compared to the

number of codes.

  The memory having the large address space has a large extent, and it also consumes a high power In particular in the case where the decoder has

  variable length is formed by a semi-integrated circuit

  conductive, the above reason prevents obtaining a high level of integration for the variable length decoder In addition, a high level of integration cannot be obtained for the image decoding device

  which contains the variable length decoder.

  An object of the invention is therefore to provide a variable length decoder in which it is possible to reduce an address space of a table memory which is required

  to store variable length codes.

  Another object of the invention is to provide a

  variable length decoder which has a recording range

  reduced additional registration for the registration of variable length codes having code lengths shorter than a maximum code length, and having reduced circuit dimensions, suitable for obtaining

of a high level of integration.

  Yet another object of the invention is to provide a variable length decoder in which multiple kinds of tables can be stored in a

small address space.

  Yet another object of the invention is to provide a variable length decoder in which a

  variable length code be decoded by software.

  A variable length decoder according to the invention comprises a memory device, a circuit

  memory block selection and a bit selector.

  The memory device has an address space which is divided into a set of blocks, and it contains a table representing the correspondence between a set of variable length codes and a set of information items which are used to decode the codes

  of the variable length code set.

  The set of variable length codes and the set of information items in the table are classified into a set of groups based on first bit strings, each of which is formed by one or more predetermined bits in each code of variable length The set of groups corresponds respectively

to the set of blocks.

  The memory device stores each item of information in each group at an address in the corresponding block which is indicated by a second bit string which is formed by one or more bits of the corresponding variable length code The second bit string is determined independently of

  those found in other groups.

  The memory block selection circuit selects any blocks from the set of blocks in the memory device, based on the first bit string of the variable length code that is applied. The bit selector reacts to an output signal from the memory block selection circuit by selecting the second bit string which corresponds to the variable length code applied, and it applies it to

address signal title.

  In the variable length decoder, the set of variable length codes are classified into the set of groups based on the first bit strings

  (bit fields) codes of variable length respectively

  tifs, and the respective groups are assigned to the different

  rents blocks in the memory device Each item of information in each group is stored at the address in the corresponding block which is indicated by the second bit string (bit field) of the length code

corresponding variable.

  Therefore, the block is selected based on the first bit string of the variable length code that is applied, and the address in the selected block is designated based on the second bit string of the variable length code II the result is that the number of addresses that record the same information

decreases.

  Since the address in the memory device is designated using part of the variable length code bits, as described above, it is possible to reduce the address space that is required to save the table. , by using a specific property of the code string (bit string) of the variable length code, space is effectively used

  memory device address.

  A variable-length decoder according to another aspect of the invention comprises a memory device, a region selection circuit, a

  selection of memory blocks and a bit selector.

  The memory device has an address space which contains a set of regions, each of which is divided into a set of blocks, and it stores multiple kinds of tables, each of which indicates the correspondence between a set of codes of variable length and a set of information items which are respectively used to decode the set

of variable length codes.

  The regions of the corresponding set of regions

  tooth respectively to the multiple kinds of tables.

  The set of variable length codes and the set of information items in each table are classified into a set of groups based on first bit strings, each of which is formed by one or more

  predetermined bits of each variable length code.

  The set of groups corresponds respectively to the set-

  ble of blocks in the corresponding region.

  The memory device stores each item of information in each group and in each table, in the corresponding block in the corresponding region, at an address which is indicated by a second string of bits which is formed by one or more bits of the code of corresponding variable length The second string of bits is determined independently of those found

in the other groups.

  The region selection circuit reacts to a

  predetermined signal by selecting any regions

  ques from the set of regions in the memory device, so as to select any sort

  among the many kinds of tables.

  The memory block selection circuit selects any blocks from the set of blocks in the selected region of the memory device, based on the first bit string of the length code

variable that is applied.

  The bit selector reacts to an output signal from the memory block selection circuit by selecting the second bit string corresponding to the

  variable length code that is applied, and it applies it

  as an address signal to the memory device.

  The variable length decoder allows recording

  manage the multiple kinds of tables in the small

address space.

  il A variable length decoder conforming to

  yet another aspect of the invention includes a provision

  memory, a circuit for selecting blocks of

memory and a bit selector.

  The memory device has an address space which is divided into a set of blocks, and it maintains a table representing the correspondence between a set of variable length codes and a set of information items which are respectively used for

  decode the set of variable length codes.

  The set of variable length codes and the set of information items in the table are

  classified into a group of groups, based on first-

  res bit strings, each of which is formed by one or more predetermined bits of each variable length code The set of groups corresponds respectively

to the set of blocks.

  The memory device stores each item of information in each group at an address, in the corresponding block, which is indicated by a second bit string which is formed by one or more bits of the corresponding variable length code. The second bit string is determined independently of those of other groups. The memory block selection circuit selects any blocks from the set of blocks in the memory device based on the first bit string of the variable length code applied, for example.

  a conditional decision, taken by software.

  The bit selector reacts to an output signal from the memory block selection circuit by selecting the second bit string corresponding to the variable length code applied, and it applies it to the

  memory device as an address signal.

  This variable length decoder makes it possible to decode the variable length codes, using software.

  According to the invention, and as described above

  above, the address in the memory device is designated using part of the bits of the variable length code, which makes it possible to reduce the space

  address that is required to register the table.

  Therefore, the variable length decoder may have

  a circuit of reduced dimensions and low consumption

  power, which is suitable for obtaining a

high level of integration.

  These and other objects, features, aspects and advantages of the present invention will become apparent.

  more from the following detailed description of modes of

  realization, given by way of nonlimiting examples La

  continuation of the description refers to the attached drawings in

  which: Figure 1 is a block diagram showing the overall structure of a variable length decoder of a first embodiment of the invention; Figure 2 is a block diagram showing the structure of a decoding table which is used in the variable length decoder of Figure 1; Figure 3 shows an address space of a table memory which is included in a decoding table shown in Figure 2; FIG. 4 shows an example of a correspondence table representing the correspondence between variable length codes and code information articles; Figure 5 shows code information which is stored in a block in the table memory; FIG. 6 shows code information which is recorded in another block in the memory of

table;

  Figure 7 shows code information that is stored in yet another block in memory

of table;

  FIG. 8 shows code information which is recorded in a block remaining in the memory of

table;

  FIG. 9 is a circuit diagram showing an example of a structure of a memory block selection circuit; Figure 10 shows a truth table of the memory block selection circuit of Figure 9; Figure II shows an example of the structure of a bit selector; Figure 12 shows another example of the structure of the bit selector; Figure 13 is a block diagram showing the structure of a decoding table which is used in

  the variable length decoder of a second embodiment

  sation of the invention; Figure 14 shows an address space of a table memory which is included in the decoding table which is shown in Figure 13; Fig. 15 is a flow chart showing an example of operation of a code switching signal generation circuit; Fig. 16 is a flowchart showing processing which is performed by software in a variable length decoder of a third embodiment of the invention; Fig. 17 is a block diagram showing the structure of a device which performs coding processing of image data; Fig. 18 is a block diagram showing the structure of a device which performs a decoding operation of compressed image data; Figure 19 is a block diagram showing the overall structure of a variable length decoder of the prior art; Figure 20 is a block diagram showing a decoding table which is used for the variable length decoder of Figure 19; FIG. 21 shows an example of a correspondence table which represents the correspondence between variable length codes and code information; and Figure 22 shows an example of operation

  a variable length decoder.

  (1) First embodiment Figure 1 is a block diagram showing the structure of a variable length decoder of a first embodiment The variable length decoder of Figure 1 differs from the variable length decoder of Figure 19 by the decoding table structures 20 a and The other structures are similar to those which

  are shown in Figure 19.

  Figure 2 is a block diagram showing the

  structure of the decoding table 20 a The decoding table

  dage 20 a includes a table memory 21 a, a memory block selection circuit 22 and a bit selector 23. The table memory 21 has an address space which is divided into a set of blocks In this mode of embodiment, as shown in FIG. 3, the address space in the table memory 21 a is divided into

  four blocks BAO, B Al, BA 2 and BA 3.

  The table memory 21 a is constituted for example by a read-only memory (or ROM) This read-only memory comprises 7-bit address entries, and it stores data corresponding to 128 words The width or the number of bits of each word data is 10

bits.

  In FIG. 2, the signal line L 2 receives an 11-bit variable-parallel length code BO-Bl O, coming from the variable length code input circuit in FIG. 1 The 6 higher order bits BO -B 5 of the variable length code are applied to the memory block selection circuit 22, and all the bits BO-Bl O of the variable length code are applied to the selector

of bits 23.

  The memory block selection circuit 22 reacts to the 6 bits BO-B 5 of the variable length code by generating a 2-bit BSL memory block selection signal The BSL memory block selection signal is applied to the memory table 21 a, in the form of the 2 higher order bits AO and Ai of the address signal The memory block selection signal BSL is also

applied to bit selector 23.

  The bit selector 23 reacts to the memory block selection signal BSL by selecting 5 bits from the 11 bits BO-Bl O of the variable length code, and it applies the 5 selected bits to the table memory 21 a, under the form of the 5 lower order bits A 2-A 6 of

address signal.

  On the basis of the 2 higher order bits AO and Ai of the address signal, a block is selected from the

  four BAO-BA 3 blocks in table memory 21 a.

  The address is designated in each block on the basis of the 5 lower order bits A 2-A 6 of the address signal Under the effect of the control signal CNT, code information is read at the address in the selected block, and it is applied through the output terminal of

  data D at signal lines L 3 and L 4.

  The table memory 21a maintains a correspondence table, which is represented for example on the

  figure 4 The correspondence table represents the corres-

  weight between variable length codes and information

  code mation (fixed length data and code lengths). The variable length codes and code information found in the correspondence table in Figure 4 are classified into first to fourth groups, G 1-G 4, in accordance with the following rule. the left end bit of the variable length code having the maximum code length (11 bits) is the higher order bit (the most significant bit) BO and that the right end bit is the bit

  lower order (the least significant bit) B 10.

  The variable length code having the four higher order bits B O B which satisfy the relation 0 3

  is classified in the first group G 1.

O + B 1 + B 2 + B 3 O (1)

  The variable length code having the 5 higher order bits B O B 4 which satisfy the relations

  are classified in the second group G 2.

  B O + B 1 + B 2 + B 3 = 0 and B 4 = 1 (2) The variable length code having the 6 higher order bits B O B 5 which satisfy the relations

  is classified in the third group G 3.

  B O + Bl B 2 + B 3 + B 4 = 0 and B 5 = 1 (3) The variable length code having the 6 higher order bits B O B 5 which satisfy the relation

  is classified in the fourth group G 4.

  B O + B 1 + B 2 + B 3 + B 4 + B 5 = O (4)

  The first to fourth groups G 1, G 2, G 3 and G 4 are respectively assigned to the blocks BA 0, BA 1, BA 2 and

  BA 3 in table memory 21 a.

  Each code information item in the first group G 1 is stored at the address in the BAO block which is designated by the 5 higher order bits BOB 4 of the corresponding variable length code Each code information item in the second group G 2 is stored at the address in block B Al which is designated by the 5 bits B 4 B 8 of the corresponding variable length code Each code information item in the third group G 3 is stored at l address in block BA 2 which is designated by the 5 bits B 6 Bl of code 6 10 of corresponding variable length Each item of information in the fourth group G 4 is registered at the address in block BA 3 which is designated by 5 bits

  B 6 B 10 of the corresponding variable length code.

  Figures 5, 6, 7 and 8 show the code information that is stored in the BAO, BA 1, BA 2 blocks.

  and BA 3 in table memory 21 a.

  As shown by way of example in FIG. 5, at the addresses "l XXXX" in the BAO block are stored the data of fixed length "000000" (= "O") and the code lengths "0001" (= "1 ") At the addresses" 011 XX "the fixed length data" 000001 "is saved

  (= "1") and the code lengths "0011" (= "3").

  As shown by way of example in FIG. 6, at the addresses "111 XX" in block BA 1 are stored the data of fixed length "000111" (= "7") and the code lengths "0111" (= " 7 ") In addition, at addresses" 110 XX "in block B Al, the fixed length data" 001000 "(=" 8 ") and the code lengths are saved

"0111" (= "7").

  As shown by way of example in FIG. 7, at the addresses "11 XXX" in block BA 2, the fixed length data "001101" (= "13") and the code length data "1000" ( = "8") At addresses "10 XXX" in block BA 2 the fixed length data "001110 (=" 14 ") and the code lengths are saved

"1000" (= "8").

  As shown by way of example in FIG. 8, at the addresses "11111" in block BA 3, the data of fixed length "011001" (= "25") and the code length "1011" (= " 11 ") At address" 11110 "in block BA 3 the fixed length data are saved

  "011010" (= "26") and the code length "1011" (= "11").

  As stated above, each news article

  Code code comprising the fixed length data and the code length, is stored at the address which is designated by the 5 bits of the corresponding variable length code. Figure 9 is a circuit diagram showing an example of the structure of the memory block selection circuit 22 Figure 10 shows a truth table of the

  memory block selection circuit 22.

  The memory block selection circuit 22 which is represented in FIG. 9 comprises a NOR gate 221, AND gates 222, 223 and 224, OR gates

  225 and 226, and inverters 227 and 228.

* If the variable length code which is applied belongs to the first group Gi, at least one of the bits BOB 3 of the variable length code has the value "1" Therefore, the NOR gate 221 generates a signal value output "'", and AND gates 222, 223 and 224 generate output signals of value "O" As a result, the two outputs of OR gates 225 and 226 are at "O" Therefore, the bit AO of the BSL block selection signal becomes "O", and the bit Ai also becomes "O"

  done, the BAO block is selected.

  If the variable length code applied appears

  comes from the second group G 2, each of the bits BOB 3 of the variable length code is equal to "O", and the bit B 4 is equal to "1" Therefore, the NOR gate 221 generates an output signal with value "1", and AND gate 222 generates an output signal with value "1" AND gates 223 and 224 generate output signals with value "O" As a result, the output signal from OR gate 225 is equal to "1", and the output signal from OR gate 226 is equal to "O" Therefore, the bit AO of the block selection signal BSL becomes "'", and the bit Ai becomes "1" The BAI block is

thus selected.

  If the variable length code which is applied belongs to the third group G 3, each of the bits BB 4 of the variable length code is equal to "'", and the bit B 5 is equal to "1" Therefore, the gate NOR 221 produces an output signal of value "1", and AND gate 223 produces an output signal of value "1" The outputs of AND gates 222 and 224 produce output signals of value "0" Consequently , the output signal from the OR gate 225 is equal to "O", and the output signal from the OR gate 226 is equal to "1" As a result, the bit AO of the block selection signal BSL becomes "1 "and the bit Ai becomes

  "O" Block BA 2 is thus selected.

  If the variable length code which is applied belongs to the fourth group G 4, each of the bits BB 5 of the variable length code is equal to "O" Therefore, the NOR gate 221 produces a value output signal " 1 ", and gate ET 224 produces an output signal from

  value "1" The outputs of doors ET 222 and 223 produced

  feels output signals with value "O" It follows that the output signal from OR gate 225 is equal to 'vl',

  and the output signal from the OR gate 226 is equal to "1".

  Consequently, the bit AO of the block selection signal BSL becomes "1", and the bit Ai becomes "1". Block BA 3 is

thus selected.

  Figure II shows an example of the structure of the bit selector 23, which includes a decoder 230 and

  selectors 231, 232, 233, 234 and 235.

  The decoder 230 decodes the 2 bits AO and Ai of the block selection signal, and sets one of the

  selection signals Si, 52, 53 and 54 Each of the selections

  ters 23 I-235 has four input terminals Il, I 2, I 3 and I 4, as well as an output terminal Each selector reacts to selection signals Sl-54 by selecting one of the signals which are applied to the input terminals I 1-I 4, and it applies this signal to the output terminal. The input terminals Il, I 2 and I 3 of the selector 231 respectively receive bits B 0, B 4 and B 6 of the variable length code The input terminals Il, I 2 and I 3 of the selector 232 respectively receive the bits Bi, B 5 and B 7 of the variable length code The input terminals Il, I 2 and I 3 of the selector 233 receive bits B 2, B 6 and B 8 of the variable length code respectively The terminals

  input Il, I 2 and I 3 of selector 234 receive respectively

  bits B 3, B 7 and B 9 of the variable length code.

  The input terminals Il, I 2 and I 3 of the selector 235 receive

  wind bits B 4, B 8 and BI O respectively of the

  variable length The input terminal I 4 of each selection

  tor receives the same bit as the input terminal I 3.

  The bits which are emitted by the selectors 231-235 are applied to the table memory 21 a, under the

  form of bits A 2-A 6 of the address signal.

  When the two bits AO and Ai of the signal

  block selection is equal to "O", the selection signal

  tion Si is equal to "1" Consequently, the selectors 23 I-235 respectively supply the bits B 0-B 4 When the bits AO and Ai of the block selection signal are respectively equal to h O "and" 1 ", the selection signal 52 is equal to "l" Consequently, the selectors 231-235

  provide bits B 4-B 8 respectively.

  When the bits AO and Ai of the block selection signal are equal to "'" and "O" respectively, the signal

  selection 53 is equal to "1" Therefore, the selections

  tors 231-235 respectively supply bits B 6-B 1 O. When the two bits AO and Ai of the block selection signal are equal to "1", the selection signal 54 is equal to "1" Therefore, the selectors 231-235 respectively provide the bits B 6-B 1 O. FIG. 12 shows another example of the structure of the bit selector 23 The bit selector 23 of FIG. 12 comprises selectors 241- 245 Each of the selectors 241 -245 receives bits AO and Ai of the block selection signal Each selector reacts to bits AO and Ai by selecting one of the signals which are applied to the input terminals Il, I 2, I 3 and I 4, and it apply this

signal to the output terminal.

  While the bit selector 23 in FIG. 11 includes the detector 230 which is common to the five selectors 231-235, the bit selector 23 in FIG.

  12 has five selectors 241-245 each having a function

  decoding The operation of the bit selector 23 in Figure 12 is similar to the operation of the

  bit selector 23 in Figure 11.

  The operation of the

  decoding table 20 a which is shown in FIG. 2.

  If the variable length code to be decoded is for example "011", the variable length code "01 l" is applied to the three higher order bits of the signal line L 2, and invalid eight bit data is

  applied to the remaining bits This invalid data includes

  take some or all of the length code

  variable which will be decoded later.

  It is assumed here that the signal line L 2 receives

  the code "01100000111" The 6 higher order bits BO -

  B 5 ("011000") of the variable length code on the signal line L 2 are applied to the block selection circuit

  22, and all the bits BO B 10 ("01100000111") are applied

ques to the bit selector 23.

  Under the effect of these bits BO B 5, the block selection circuit 22 sets the 2 bits AO and Ai of the block selection signal BSL respectively at "'" and "" The block BAO in the table memory 21 a is thus selected (see figure 3) Depending on the signal of

  selection of BSL blocks, the bit selector 23 selects

  selects 5 bits BO B 4 ("011000") from bits BO and B 10, and applies them as an address signal to the table memory 21 a The address "01100" in the BAO block is thus designated As a result, the fixed length data "000001" (= "1") and the code length

  "0011" (= "3") are read at the address "01100".

  Although an example has been described of the

  decoding considering the case in which the variable length code "011" belongs to the first group Gi, other variable length codes are treated with

similar way.

  The conventional variable-length decoder requires table memory 21 having an address space of 2048 words to store the correspondence table which is shown in Figure 21. On the other hand, the variable-length decoder of this embodiment requires the table memory 21 a having an address space of only 128 words, for storing the correspondence table which

is shown in Figure 4.

  As described above, the capacity of the table memory 21 a which is used in this embodiment is equal to sixteenth of the capacity of the conventional table memory 21 In addition, the table memory 21 has the same structure of width of words as table memory 21, and therefore the total number of bits of table memory 21 a is equal to sixteenth of

  total number of bits of the conventional table memory 21.

  In the above embodiment, the memory block selection circuit 22 applies the same BSL block selection signals to the table memory 21 a and to the bit selector 23 It is however possible to apply to the memory table 21a and bit selector 23 different representative signals

of group classes.

  Although in the above embodiment the table memory 2 la is constituted by a read only memory, this table memory 2 la can also be

  constituted by a random access memory (or RAM).

  In the above embodiment, the blocks BAO, B A1, BA 2 and BA 3 in the table memory 21 a are switched by the higher order bits in the address of the table memory 21 a, but bit switching

  higher order is not essential As an example

  ple, blocks can be switched using the lower and lower order bits in memory

table 21 a.

  (2) Second embodiment Figure 13 is a block diagram showing the structure of a decoding table which is used in

  a variable length decoder of a second embodiment

  The overall structure of the variable length decoder of the second embodiment is similar to

  the one shown in Figure 1.

  A variable length decoder 20 b comprises a table memory 21 b, a memory block selection circuit 22 and a bit selector 23 The table memory 21 b is formed by a read only memory The read only memory a

  an 8-bit address entry, and it contains data

  born of 256 words The width of each data word is

10 bits.

  The address space in the table memory 21b includes a set of regions, and each of them is

  divided into a set of blocks In this embodiment

  As shown in FIG. 14, the address space of the table memory 21 b comprises two regions Ri and R 2, and each of them is divided into four blocks

BAO, B Al, BA 2 and BA 3.

  Bit A 7 of the address signal is used to select one of the two regions Ri and R 2 in the

  table memory 21 b The bits A O and Ai of the address signal

  are used to select one of the four BAO BA 3 blocks in each region The five bits A 2 A 6 of the address signal are used to designate the address

in each block.

  The regions Ri and R 2 in the table memory 21 b respectively record different kinds of correspondence tables In the region Ri, the correspondence table, for example that shown in FIG. 4, is saved in a similar manner to the memory 21 a of the first embodiment In the region R 2 is recorded a correspondence table

  which differs from that shown in Figure 4.

  Similar to the correspondence table in FIG. 4, the correspondence table which is recorded in the region R 2 is divided into groups going from a first group to a fourth group, Gi G 4, which are

  respectively saved in BAO BA 3 blocks.

  The code information that the table memory 21 b supplies to the signal lines L 3 and L 4 is applied to a code switching signal generation circuit. The code switching signal generation circuit 30 generates the signal. code switch CSW based on the code information, and applies it to the table memory 21 b, in the form of bit A 7 of the address signal Under the effect of the code switch signal CSW, the correspondence table which is saved in the region Ri or R 2 is selected, and the selected correspondence table is used for decoding

variable length code.

  The memory block selection circuit 22 and the bit selector 23 have structures similar to that of the memory block selection circuit 22 and the bit selector 23 which are shown in FIG. 2. FIG. 15 is a flowchart showing an example of operation of the code switching signal generation circuit 30 In the figure, the correspondence table which is recorded in the region Ri is designated by CT 1, and the correspondence table which

  is recorded in the region R 2 is designated by CT 2.

  First, the generation circuit of

  code switching signal 30 sets the communication signal

  tation of CSW code to "O" This has the effect of selection-

  ner the correspondence table CT 1 which is recorded in the region Ri (step Si) Then, the code switching signal generation circuit 30 fixes the code switching signal CSW at "1" This has the effect of selecting the CT 2 correspondence table which is

  recorded in the region R 2 (step 52).

  The switching signal generation circuit

  code 30 sets the CSW code switching signal to "O" if the fixed length data which is supplied by the table memory 21 b is the "EOB" data (end of segment) Under these conditions, the correspondence CT 1 is selected again (step Si) On the other hand, in step 53, if the table memory 21 b provides data

  of fixed length other than "EPO", the generation circuit

  code switching signal 30 keeps the CSW code switching signal at "1"

  correspondence CT 2 is thus selected (step 52).

  In this way, the correspondence table CT 2 is selected repeatedly after the selection of the correspondence table CT 1, and before the table memory 21 b transmits the data of fixed length indicating

  the end of segment "EOB" condition.

  The variable length decoder which includes the decoding table 20b is used when multiple kinds of variable length codes, which must be decoded using different correspondence tables, are applied in timeshare For example, the correspondence table CT 1 to decode a first kind of variable length codes is registered in the region

  Rl in the memory of table 21 b, and the table of corres-

  pondance CT 2 to decode a second kind of variable length codes is recorded in the region R 2 in

table memory 21 b.

  In practice, code information corresponds to

  the first kind of variable length codes is recorded in the corresponding block in the region Ri, and code information corresponding to the second kind of variable length codes is recorded in

  the corresponding block in the region R 2.

  The CSW code switching signal indicates the kind (i.e. first or second) of the variable length code which is applied If the kinds of variable length codes which are applied are to be switched according to a rule predetermined, the code switching signal generating circuit 30 generates the code switching signals CSW according to the same rule If the kinds of variable length codes which are applied are to be determined according to the code information which is decoded , the code switching signal generating circuit 30 generates the code switching signals CSW based on the code information which is provided by the memory of

table 21 b.

  In the variable length decoder of the above embodiment, when the multiple kinds of variable length codes are applied in timeshare, the kinds of look-up tables to be used are switched by selecting the regions in the table memory 21 b, depending on the CSW code switching signals We can therefore decode the various kinds of variable length codes using the

table memory 21 b single.

  (3) Third embodiment A decoding table for a variable length decoder of a third embodiment is formed

  by a microprocessor or a digital signal processor

  that in this case, the functions of the memory block selection circuit 22 and of the bit selector 23 which are

  shown in Figure 2 are filled with treat-

software.

  FIG. 16 is a flowchart showing a processing which is intended to fulfill the same function as the memory block selection circuit 22 It is assumed

  that the table memory 21 has saved the correspondence table

  pondance which is represented on figure 4 The correspondence table is divided into groups going from the first to

  fourth, in accordance with the rules expressed by the rela-

tions (1) (4).

  The decoding table receives the codes for

  variable length of the maximum code length format, including the variable length code to be decoded If the variable length code to be decoded has a code length less than the maximum code length, the higher order bits of the variable length code of the maximum code length format constitute the actual variable length code, and the lower order bits

are the invalid bits.

  First, we determine if the 4 bits

  of higher order BO-B 3 are all equal to "O" (step S 11).

  If any of the 4 higher order bits B 0-B 3 is

  equal to "1", the BAO block is selected (step 512).

  In step 511, if the 4 higher order bits BO-B 3 are all equal to "O", it is determined whether the fifth bit B 4 is equal to "O" or not (step 513) If the fifth bit B 4 is equal to "1", the block B Al is selected (step 514). In step 513, if the fifth bit B 4 is equal to "O", it is determined whether the sixth bit B 5 is equal to "O" or not (step 515) If the sixth bit B 5 is equal to "1 ", the

  block BA 2 is selected (step 516).

  At step 515, if the sixth bit B 5 is "O", the

  block BA 3 is selected (step 517).

  Each conditional decision that is represented

  seen in figure 16 can be executed by a

  conditional branch instruction among instruc-

  that are stored in the microprocessor or the

digital signal processor.

  Under the effect of the block selection in the processing which is represented in figure 16, the variable length code applied is shifted appropriately according to the group, using an shift circuit which is incorporated in the microprocessor or the processor digital signal The shifted variable length code is applied to the table memory 21 a, as an address signal, which gives access to

  the address in table memory 21 a.

  As described above, the software processing allows the variable length decoder to have functions similar to those of the first mode of

production.

  In this case also, the table memory 2 la requires an address space having only 128 words, for the decoding of the variable length codes. The number of bits required is therefore equal to sixteenth of that of the

  table memory of the prior art.

  It goes without saying that many modifications can be made to the device and to the process described.

  and shown, without departing from the scope of the invention.

Claims (13)

  1 variable length decoder for decoding variable length codes, characterized in that it comprises: memory means (21 a) having an address space divided into a set of blocks (BAO-BA 3), for recording a table indicating the correspondence between a set of variable length codes and a set of information items which are used to respectively decode this set of variable length codes; the set of variable length codes and the set of information items in the table being classified: s into a set of groups (G 1-G 4) on the basis of first bit strings (BOB 5), each of them being formed by one or more bits of each variable length code,   this set of groups (G 1-G 4) corresponding respectively-   ment to the set of blocks (BAO-BA 3); the means to   memory (21 a) recording each of the informational articles   tion in each group at an address which is indicated by a second bit string which is formed by one or more bits of the corresponding variable length code, in the corresponding block; this second bit string being determined independently of the second bit string in the other groups; means of selecting   memory blocks (22) for selecting any blocks   of the set of blocks (BAO-BA 3) in the memory means (21a), on the basis of the first bit string   (BO-B 5) of the variable length code applied to them   than; and bit selection means (23) for selecting   the second bit string corresponding to the code of   variable length applied to them, under the   dance of an output signal (BSL) of the memory block selection means (22), and to apply it to the means   memory (21 a), as an address signal (A 2-A 6).   2 Variable length decoder depending on the res   dication 1, characterized in that each of the information articles includes fixed length data and a   code length of the corresponding variable length code dant.   3 Variable length decoder depending on the res   dication 1, characterized in that the first bit string comprises a predetermined number of command bits   of each variable length code, and the whole   ble of groups (G 1-G 4) are determined on the basis of the number of bits having continuously the same value at   from a first bit in the first bit string.   4 Variable length decoder depending on the res   dication 1, characterized in that the selection means   of memory blocks (22) select any blocks   among the set of blocks (BAO-BA 3) in the memory means (21 a), by a conditional decision which is taken by software.   Variable length decoder depending on the res   dication 4, characterized in that the decision conditions-   taken by software includes a decision regarding   the fact that a predetermined number of higher order bits   laughing have a predetermined value or not.   6 Variable length decoder for decoding variable length codes, characterized in that it comprises: memory means (21 b) having an address space which comprises a set of regions (Ri, R 2), each being divided into a set of blocks (BAO-BA 3), for registering multiple kinds of tables, each of which indicates the correspondence between a set of variable length codes and a set of information items which are used to respectively decode the set of variable length codes;   the respective set of regions (Ri, R 2)   ment to the multiple kinds of tables, the set of codes   of variable length and the set of informational articles   tion in each of the tables being classified into a set of groups (G 1-G 4) on the basis of first bit strings (BO-B 5), each of which is formed by one or more bits of each code of variable length, the set of groups (G 1-G 4) corresponding respectively to the set of blocks (BAO-BA 3) in the corresponding region; the memory means (21 b) recording each of the aforementioned items of information in each group at each table at an address which is indicated by a second bit string formed by one or more bits of the corresponding variable length code, in the block corresponding in the corresponding region, this second bit string being determined independently of the second bit string in the other groups; region selection means (30) for selecting a region - any of the set of regions (Ri, R 2) in the   memory means (21 b), for selecting any one   that multiple kinds of tables, depending on a predetermined signal; memory block selection means (22) for selecting any block from the set of blocks (BAO-BA 3) in the region selected in the memory means (21a), based on the first chain of bits (B 0-B 5) of the variable length code applied to them; and bit selection means (23) for selecting the second bit string corresponding to the variable length code applied thereto, depending on an output signal (BSL) of the memory block selection means (22 ), and to apply it to the memory means (21 b) in the form of a address signal (A 2-A 6).   7 Variable length decoder according to the res   dication 6, characterized in that each of the information articles comprises data of fixed length and a   code length of the corresponding variable length code dant.   8 Variable length decoder depending on the res   dication 6, characterized in that the first bit string comprises a predetermined number of command bits   of each variable length code, and the whole   ble of groups (G 1-G 4) are determined on the basis of the number of bits having continuously the same value at   from a first bit in the first bit string.   9 Variable length decoder according to the res   dication 7, characterized in that the predetermined signal comprises data of fixed length which are read in the memory means (21 b).   Decoding method for decoding variable length codes, characterized in that it comprises the following steps: a table is prepared indicating the correspondence between a set of variable length codes and a set of information items which are used for respectively decoding the set of variable length codes; the set of variable length codes and the set of information items in the aforementioned table are classified into a set of groups (G 1-G 4), on the basis of a first bit string (BO- B 5) which is formed by one or more predetermined bits of each variable length code; determining the correspondence of the set of groups (G 1-G 4) with a set of blocks (BAO-BA 3) which are included in the memory means (21 a); each item of information is stored in each group at an address which is indicated by a second bit string which is formed by one or more bits of the corresponding variable length code, in the corresponding block in the memory means (21a) , this second bit string being determined independently of the second bit strings in the other groups; selecting any block from the set of blocks (BAO-BA 3) in the memory means (21a), on the basis of the first bit string (BO-B 5) of the variable length code which is their applied; and the second bit string corresponding to the variable length code applied is selected, on the basis of the result of the aforementioned selection, and it is applied to the memory means (21 a) as an address signal (A 2- A 6), to read the corresponding information article.   11 The method of claim 10, character-   laughed at in that each of the news items includes fixed length data and a code length of the   corresponding variable length code.   12 Method according to claim 10, character-   that the first bit string includes a predetermined number of higher order bits of each variable length code, and the step of classifying into groups includes the step of classifying the set of variable length codes and the set of information items in the set of groups (G 1-G 4) based on the number of bits having the same value continuously from a first bit in the first string of bits.   13 The method of claim 10, character-   that the step of selecting any block from the set of blocks includes the step of selecting any block from the set of blocks (BAO-BA 3) by a conditional decision made by software.   14 Decoding method for decoding variable length codes, characterized in that it comprises the following steps: multiple kinds of   tables each indicating the correspondence between a set   ble of variable length codes and a set of arti-   information keys that are used to decode respec-   the set of variable length codes; the set of variable length codes and the set of information articles are classified into a set of groups (G 1-G 4), on the basis of a first bit string   (B O B 5) which is formed by one or more predeter-   mined with each variable length code; determining the correspondence of the multiple kinds of tables with a set of regions (Ri, R 2) which are included in memory means (21 b); each item of information is recorded in each group in each table at an address which is indicated by a second string of bits formed by one or more bits of the corresponding variable length code, in the corresponding block in the corresponding region of the memory means (21 a), this second bit string being determined independently of the second bit strings in the other groups; selecting any region from the set of regions (Ri, R 2) in the memory means (21 a), to select any table from the multiple kinds of tables; any block is selected from a set of blocks (BAO-BA 3) in the region selected in the memory means (21 b), on the basis of the first bit string (BO-B 5) of the variable length code applied to them; and the second bit string corresponding to the variable length code applied is selected, based on the result of the selection of the set of blocks, and it is applied to the memory means (21 b) as signal of address (A 2-A 6), for   read the corresponding information article.   Method according to claim 14, character-   laughed at in that each of the news items includes fixed length data and a code length of the   corresponding variable length code.   16 The method of claim 14, character-   laughed in that the first bit string includes a predetermined number of higher order bits of each variable length code, and the step of classifying into groups includes the step of classifying the set of variable length codes and the set of information items in the set of groups (G 1-G 4) based on the number of bits having the same value continuously from a first bit in the first string of bits.