FR2655787A1 - CIRCUIT ARRANGEMENT FOR OPERATING ON A CONTINUOUS VOLTAGE NETWORK A SYNCHRONOUS POLYPHASE ENGINE. - Google Patents

Abstract

a) Circuit arrangement for operating a polyphase synchronous motor on a direct voltage network. b) circuit arrangement characterized in that for the switching of two winding phases successively traversed by the current (u, v, w) the two switching signals (S1 - S6) for the switches (T1 - T6) associated with the switching phases, temporarily overlap, and in that at least one of the two switching signals (S1 - S6) is synchronized in the overlap zone (DELTA t) so that the mean value of the winding phase current ( Iu, Iv, Iw) increases in the phase of winding entering switching and decreases in the phase of exiting switching winding, and this preferably linearly or else according to a function e. c) The invention relates to circuit arrangements for operating a polyphase synchronous motor on a DC network.

Description

The invention starts from a circuit arrangement for operating on a network

continuous voltage, a

  synchronous motor comprising a poly-induced armature winding

  phased arrangement comprising a switching device

  to successively connect the winding phases

  winding of the armature winding to the conti-

  naked, a device which comprises a plurality of switching

  electronics associated with the different phase windings, and switching logic being provided

  to order in correct successions the

  by switching signals in accordance with the

  rotational position of the rotor of the synchronous motor.

  In a known circuit arrangement of this type, for a four-phase synchronous motor (DE 42 42 819 A1), the switching device respectively of an armature winding, arranged in this case in the stator of the synchronous motor, in series with the sentence

  winding, is switched by switches

  in the form of power transistors and is placed between a winding phase end and the zero potential. The other winding phase ends of the armature winding are combined with one another.

  a neutral point which, through a

  network, is likely to be connected to the

  Positive voltage of the DC line voltage The switching logic to allow the control in correct succession of the commutation in accordance with the rotation position of the preferably excited rotor

  by permanent magnets, is carried out by

  voltage equalizers, by logic combination devices and by an annular counter whose parallel counting outputs are connected to the control inputs of the transistors In the voltage comparators, the voltages induced by the winding phases succeeding each other cyclically by blocking transistors are respectively compared with each other and an output signal is then effectively

  when the voltage induced in the phases of

  cyclically succeeding rotation, is greater than

  the voltage induced in the cyclic winding phase

  Previously, these output signals from comparisons

  The voltage meters are combined with the output signals of the ring counter, according to "AND" logic, so that a switching signal then reaches, and only then, a monostable flip-flop, when the next winding phase cyclically the winding phase exhibiting the highest induced voltage is traversed by the current due to

  the opening of the associated transistor The output of the

  annular actuator connected to the control input of this current valve, provides for this purpose a potential H The annular counter continues to operate thanks to

  on the positive side of the output pulse of the

  the monostable, so that henceforth the potential H

  is located at the next exit of the meter and the

  sistor momentarily open is blocked, while the

  Next transistor cyclically is open.

  In the case of a circuit arrangement

  The switching logic of the type initially mentioned for a three-phase synchronous motor (P 37 09 168 9) comprises a switching signal generator with a voltage-to-frequency converter, with a start-up device connected upstream thereof.

  converter, and with an effective restart unit

  after synchronization of the synchronous motor, as well as with an annular counter having three parallel outputs which are connected with the control inputs of the transistors connected to a phase

  star-wound winding of the armature winding.

  Rectangular pulses produced by the general

  of the switching signals, apply as counting pulses to the counting input or synchronization input of the ring counter With each counting pulse, the ring counter

  one step forward, so that successively

  Output voltages at the different outputs of the annular counter, switch from logic L to logic H and vice versa At each instant, only one counting output provides the potential H. In these two circuit arrangements, the

  electronic switches are controlled by im-

  rectangular impulses, the positive flank (amount) of

  the switching pulse for the switch in de-

  switching object, coinciding with the negative side (falling) of the switching signal for the switch at the end of switching Such an arrangement of the circuit causes in the synchronous motor, also called EC motor in combination with the circuit arrangement, during the switching of the current, that is to say during the transition of the passage of the current of one of the momentarily conducting winding phases (phase

  winding up at the end of switching) to the

  following conductive rolling (winding phase of the start of commutation) significant noises and

  is also the cause of parasites.

  The circuit arrangement according to the invention

  characterized in that for the switching of two winding phases successively traversed by the current, the two switching signals for the switches associated with the switching phases temporarily overlap, and in that at least one of the two signals of switching is synchronized in

  the area of overlap so that the average value

  no winding phase current will grow in the

  winding phase entering into switching and decreasing

  in the outgoing switching winding phase, and this, preferably, linearly or according to a

function e.

  The circuit arrangement, with the characteristics

  However, the above-mentioned advantages have the advantage that, due to the overlapping of the switching signals and the synchronization of these switching signals in the overlapping zone, switching flanks, falling or rising regularly, of the phase currents. in the winding phases

  respectively switching, are obtained at low

  with a predictable evolution Thus, for a

  reduced switching power, a reduction in

  noise is obtained and noise is also considerably reduced. Noise reduction results from the fact that the average torque is not

  switched but slowly controlled by the flanks of the neck.

  increasing switching power in the winding phase.

  at the beginning of switching or decreasing in the winding phase at the end of switching, and that the dynamic effects caused by the slowly increasing current, do not occur suddenly but damped Thanks to this "soft" switching, the spikes of the switching current are avoided and of

  this fact, the parasites are removed.

  During the switching process, it is possible to synchronize either the switching signal for the switch associated with the winding phase at the start of switching, or the switching signal for the switch associated with the winding phase at the end of switching. the synchronization of one of the switches, the other switch participating in the

  switching is fully open The synchronization

  One of the switches causes the phase current to decrease on average in the winding phase at the end of switching, while also the phase current increases on average in the winding phase.

  at the beginning of switching, preferably

linear or exponential.

  The circuit arrangement according to the invention

  can be used without modification for synchronous motors or EC motors that are controlled or not controlled. The armature winding can then be connected in a star or without a neutral point.

  In the first case, the communication device

  There are three electronic switches which are respectively connected to one of the three winding phases. In the second case, the switching device comprises six electronic switches grouped into a bridge, in which case respectively a winding phase between two switches placed one by one. behind the other, is connected to one of the three

parallel connections in series.

  According to another characteristic of the in-

  vention, a voltage drop taken from a resistor

  of the sum of the phase currents,

  determines the charging voltage of the capacitor.

  According to another characteristic of the in-

  the capacitor voltage is compared with a predetermined voltage in a fixed ratio to the charging voltage, and in that the end of the overlap area of the switching signals is determined by the fact that the tension of the

  capacitor becomes equal to the preset voltage.

  According to another characteristic of the in-

  vention, the actual value signal is constituted by

  a measurement voltage which is taken from a resistor

  measured in series with the winding phase.

LEMENT.

  According to another characteristic of the in-

  vention, the actual value signal is constituted by

  the voltage drop on the one that is not synchronized

  of the two electronic switches associated with the

  respectively switching winding phases.

  According to another characteristic of the in-

  vention, the actual value signal and the setpoint signal can be applied

  the inputs of a comparator whose output signals

  are applied as switching signals

  at the control input of the switch to be synchronized.

  According to another characteristic of the in-

  from the rising or falling edge of the switching signal respectively produced by the

  switching logic is derived from a control signal

  for the association of the output of the comparator to

  the control input of the switch to be res-

respectively synchronized.

  According to another characteristic of the in-

  tion, a number of comparators cor-

  corresponding to the number of comparator switches

  whose outputs are indirectly or directly

  linked respectively with an order entry of

  whose inputs and inputs are respectively

  the set-point signal and one of the actual value signals respectively derived from the phase currents and that from the rising or falling edge of the respective switching signal are

  produced by the switching logic a

  The activation signal is derived for the comparator connected to the switches to be respectively synchronized.

  According to another characteristic of the in-

  As a result, the comparator outputs are connected to the control inputs of the switches each time via a gate whose other input is connected respectively to the output of the switching logic to which the signal is emitted.

  output associated with the relevant switch.

  According to another characteristic of the in-

  vention, that the charging voltage of the capacitor is fed to this capacitor via a charge transistor and in that this charge transistor is capable of being made conductive, and

  when the preset voltage is exceeded by the voltage

  capacitors, to be blocked by the flank

  amount or the falling edge of the switching signal

  respectively produced by the switching logic

tion.

  According to another characteristic of the in-

  vention, a discharge transistor is connected in

  rises on the capacitor, this discharge transistor being made conductive when the predefined voltage

  is exceeded by the capacitor voltage.

  According to another characteristic of the in-

  Invention, a transition-operated latch is connected via its input to each of the switching signal outputs of the switching logic via its output to the base of the load transistor and to its output with the

  base of the discharge transistor and that a comparison

  controller is connected on the output side to the reset input of the flip-flop, while on the input side the capacitor voltage and the

  predefined voltage, and this comparator generates a

  output signal when the capacitor voltage has

  reaches or exceeds the preset voltage.

  According to another characteristic of the in-

  vention, that a discharge transistor is connected in

  parallel on the capacitor, this transistor de

  load being liable to be rendered conductive by the rising edge or the falling edge of the

  switching produced by the switching logic.

  According to another characteristic of the in-

  vention, the charge voltage of the capacitor is

  brought to the capacitor via a trans-

  load istor, which is likely to be made conductive when the capacitor voltage crosses

  down the predefined voltage and that is susceptible

  to be blocked by the rising edge or the falling edge of the switching signal respectively

  issued by the switching logic.

  According to another characteristic of the in-

  a transition-operated latch is connected via one of its inputs to each of the switching signal outputs of the switching logic, via its output with the base of the discharge transistor, and by

  through its exit with the basis of the transis-

  tor, and that a comparator is connected on the output side to the reset input of

  the rocker, while it is applied to it, side

  the capacitor voltage and the predetermined voltage

  finite, and this comparator delivers an output signal when the voltage of the capacitor crosses to the

low the preset voltage.

  According to a preferred embodiment of the invention, the synchronization of the switching signal

  is obtained by comparison in a signal of vari-

  their actual corresponding to the evolution of the value

  actual phase current in at least one of the phases

  switching windings, with a set-point signal corresponding to the desired change in

  the set point of the phase current This pre-

  the advantage that the necessary synchronization can be derived very simply, with only

  reduced technical means for circuits, of a

  The set point value is simple to obtain, and a desired change in phase current during the switching process can be predefined without problems. The set-point signal is obtained according to a preferred form of the invention, by charging or discharging a capacitor, the charging voltage for the capacitor being able to be slaved to the

  load current of the synchronous motor.

  The actual value signal is derived from

  phase currents of the respective winding phases

  If this is done in accordance with

  an advantageous form of the invention by means of

  measurement sistances in the winding phases of the armature winding, the measurement voltage thus taken then constituting the actual value signal, one of the

  measurement voltages from the two phases of

  switching bearings, can then be used to

  the comparison between the set value and the

  If, in accordance with another form of

  embodiment of the invention, it is used as a signal

  real value, the voltage drop on switching

  respectively switching electric transmitters made for example in the form of MOSFET or SENSEFET, it

  is then used for the comparison between the

  their setpoint and the actual value, at the voltage drop on that of the two switching switches which

  during the switching process, is not synonymous

  according to whether the actual value signal is

  taken from the phase current of the phase of

  at the beginning of commutation or at the end of

  tation, the setpoint signal must be adapted correspondingly and is implemented by

  charging or discharging the capacitor.

  The comparison between the set point

  and the actual value is effected in accordance with a

  embodiment of the invention, through the

  a comparator, which delivers a switching pulse when the setpoint signal

  exceeds the actual value signal If during the pro-

  switching, the switch associated with the

  winding phase at the end of switching is synchronized

  nized, then, according to another embodiment of the invention, the control pulses are provided

  through an OR gate at the com entry

  Switching the other input of the OR gate receives the associated rectangular switching signal

  to the switch and produced by the switching logic

  Thanks to the switching pulses of the comparator

  the switch at the end of switching is temporarily extended beyond the

  switching generated by the switching logic.

  During this extension in time, the commutation

  associated with the winding phase at the beginning of com-

  mutation is completely controlled.

  According to one embodiment of the invention, the activation signal for the comparator is derived from the positive edge of the switching signal for the switching control of the associated electronic switch. In the same way, the negative isochronous edge of the signal of switching can also be used.

  The same flanks of the switching signals are also

  used to trigger the charge or the

  capacitor discharge generating the voltage signal

  their setpoint, since the generation of the signal of

  their setpoint must be synchronized with the

switching process.

  The invention will be explained in more detail

  in the description below, using an example of

  embodiment shown in the accompanying drawings.

  Figure 1 is a diagram of an arrangement

  circuit to operate on a network with voltage con-

  tinue, a three-phase synchronous motor with electronic commutation (EC motor),

  FIG. 2 is a detailed representation of

  detail II in the diagram of Figure 1, Figure 3 shows in tabular form

  the whole of the evolution of the commutation with the

  sociation of switching signals and real value signals, Figure 4 is a diagram of the switching signals produced by a switching logic

  in the circuit arrangement of Figure 1.

  In the diagram shown in FIG. 1, reference numeral 10 denotes the three-phase armature winding of the synchronous motor, whose winding phases u,

  v, w, are housed in the stator of the synchronous motor.

  We have given up the representation of a rotor, for example

  bipolar, preferably equipped with permanent magnets

  and winding in the stator of the synchronous motor or around this stator The winding phases ut v, W are at one end gathered at one point

  neutral, while their other ends are connected

  corded to a switching device 11 This arrangement

  The switching circuit 11 consists of six power transistors T1 to T6 which are combined to form a two-way three-phase bridge rectifying coupling. Two transistors Ti, T 4 or else T 2, T 5 or

  T 3, T 6 are connected in series respectively.

  in parallel with the three serial connections

  transistors T1 to T 6 may be connected

  by means of a network switch 12 to the DC voltage designated by "+" of a DC voltage network The free ends of the winding phases u, v, W are respectively connected to one of the parallel planes of transistors Ti to T 6, and

  this on the connecting links which connect

  tively together the transistors placed one behind

  the other T1, T4 or T 2, T 5 or T 3, T 6.

  The control inputs of transistors T1 to

  T 6 are connected via amplifiers

  Vi to V 6 at the outputs of a switching logic

  13 This switching logic 13 which can be reset

  For example, as described in DE 42 819 A1, it generates on its six outputs, in accordance with the rotational position of the rotor, switching signals Si at 56 which respectively open the

  transistors T1 to T6 for the duration of their application.

  the control input of these, so that in the associated winding phases u, v, W,

  a corresponding phase current appears.

  in time of the switching signals Si to 56

  at the outputs of the switching logic 13, is

  shown in solid lines in FIG. 4 It can be seen that the falling edge of the switching signal for the transistor momentarily conducting the current and the rising edge of the switching signal for the transistor conducting the current immediately after,

are isochronous.

  To obtain a "soft" switching of the

  With the advantages of reducing the noise and eliminating the peaks of the switching current, the switching signals Si to 56 of the switching logic 13 are modified by means of a control circuit 14, so that the two switching signals for the transistors T1, T 2, or T 2, T 3, or T 3, T 1 and correspondingly, T 4, T 5 or T 5, T 6 or T 6, T 4 associated with the two winding phases respectively switching u, v,

* or v, w, or w, u, overlap temporarily-

  and one of the two switching signals is

  timed in the overlap area A t so that the average value of the phase current Iu or Iv or I, increases in the winding phase in

  start of switching u, v, W and decreases in phasing

  winding up at the end of switching v, w, u, and

  this in a corresponding way, in this case, to the evolution

  a function e The overlap of the switching signals If at 56 is the synchronization of one of the

  respective switching signals in the area of

  Temporary overlap At t, is shown in dashed lines in FIG. 4 The overlap is here obtained by a temporary extension of the switching signal.

  for the transistors Ti to T 6 associated with the phases of

  rolling respectively at the end of switching u, v,

  w The synchronization of the switching signal corresponds to

  is obtained in a simple manner from the comparison of a real value signal corresponding to the evolution of the real value of the phase current Iul, Iv, Iw, in at least one of the switching phases

  ut v, w, with a corresponding setpoint signal

  the desired evolution of the valuation value of

  phase current gne The end of the overlap occurs when the setpoint signal reaches a predefined value hereinafter referred to as the preset voltage.

  In more detail, the commu-

  Mande 14 comprises six comparators K1 to K6, whose

  outputs are coupled via the respective

  from a door OR OR 1 to OR 6 on the connection of

  between the outputs of the switching logic 13 and the inputs of the amplifiers V1 to V6, one of the inputs of the gates OR0R1 to OR6 is then connected to an output of the switching logic 13 respectively, while the others door entrances OR O Ri to

  OR 6 are respectively connected to an output of the com-

  K to K 6 outfeeds OU O R to OR 6 outlets

  are respectively fed to the inputs of the amplifiers

  Vl to V 6, whose outputs are connected to the basics

  associated transistors T1 to T 6 In each comparator

  Kl to K 6 a comparison is made between

  real value, which is obtained from the

  phase current I, Iv, Iw of one of the winding phases

  u, v, w, participant in the switching process

  tion, with the setpoint signal.

  setpoint value exceeds the actual value signal, it then appears at the output of the comparator

  K1 to K6, a switching pulse which, by

  door OR OR 1 to OR 6 and amplifiers

  V1 to V6, is fed to the corresponding transistor T1 to T6. These switching pulses result in a synchronized extension of the duration of

  in circuit of the corresponding transistor T1 to T 6.

  In order to obtain the actual value signals, on each winding phase u, v, w, of the armature winding 10, a measurement resistor 15 is connected on which a measurement voltage Uu, U, and U appears when the winding phase considered u, v, w is traversed by the current The measuring voltage Uu

  is applied, on the one hand, to the voltage amplifier

  MV 1 and on the other hand, being inverted, to the MV voltage amplifier 4 correspondingly,

  the measurement voltage U is applied to the amplifiers

  MV 2 and MV 5 measuring probes and measuring voltage U.

  is applied to MV 3 and MV 6 measurement amplifiers.

  The outputs of the MV 1 to MV 6 signal amplifiers

  are connected in correct association through

  of an association unit 16, to one of the

  comparators K1 to K6 The association unit

  16 and its connection in correct inheritance with the

  measuring plifiers MV 1 to MV 6 and comparators

  K 1 to K 6 are shown in detail in FIG.

  The setpoint signal for the

  comparators Ki to K6 is taken from a condenser

  17, which is reloaded at the beginning of each

  switching voltage The charging voltage for the con-

  densifier 17 is then slaved to the charging current in the armature winding 10, that is to say to the sum

  respective phase currents Iu, Iv, Iw, a resistor

  18 being arranged for this purpose between

  transistors T 4 to T 6 and the zero potential of

  the DC voltage, the voltage drop of this resistor being applied to an amplifier 19 The output voltage of this

  amplifier 19 constitutes the charging voltage for the capacitor 17, the output of the amplifier 19 being, for this purpose, connected to the capacitor 17 via a load transistor 20 and a resistor 21.

  series of a resistor 22 and a transistor transistor.

  load 23, which is connected in parallel on

  the capacitor 17, ensures the rapid discharge of the con-

  After the end of the charging process, the voltage 17 is taken from a voltage divider constituted by the resistors 24 and 25 which is connected in parallel to the output of the amplifier 19. A comparator 26 compares the voltage on the capacitor. 17 at the preset voltage and emits an output signal as soon as the capacitor voltage reaches

  or exceeds the preset voltage.

  The control of the discharge process and

  discharge of the capacitor 17 is ensured by a

  the RS 27 electronics operating by transition The Q output of the flip-flop 27 is connected to the base of the load transistor 20 and the Q output is connected to the base of the discharge transistor 23, while the reset input is initial R is connected to the output

  of the comparator 26 The outputs of the logic of

  tation 13 are connected through redres-

  28 and capacitors 32 to a resistor 29

  which, in turn, is at zero potential Resistance

  these 33 discharge the capacitors 32 The voltage drop on the resistor 29 is applied as a switching pulse to the flip-flop 27 The flip-flop 27 is positioned by each positive side (amount) of a switching signal Si to 56 , thanks to

  what its output Q takes the logic H With each im-

  switching pulse at the output of the comparator 26, the latch 27 is reset, thanks to

  what its Q output goes to logic H Correctly

  corresponding, the load transistor 20, or the

  discharge transistor 23, is controlled and the conden-

  17 is charged or discharged. The charging voltage of the capacitor 17 is supplied via

  entry 30 to the association unit 16 and is

  pleaded by it to the comparator Kl to K 6 in front

to be activated respectively.

  The association unit 16 which ensures the se-

  correct selection of one of the comparators 11 to K 6 of

  corresponding to the respective winding phases u, v, w, which is symbolically represented in FIG. 2 by six double switches, is controlled by the switching signals

  If at 56 For the duration of the international control signal

  If at 56, the corresponding double switch is closed and the associated comparator K 1 to K 6 receives the target value signal and the actual value signal The combination of the comparators K1 to K6 to the transistors T1 to T6 is then such that during the

  switching process is respectively prolonged

  by the switching pulses of the comparator K 1 to K 6 associated, the duration of opening of the

  transistors Tl to T 6 which is associated with the phase of

  rolling u, v, w, respectively at the end of commuta-

  The actual value signal brought to this comparator

  K 1 to K 6, starting from the association unit 16, is obtained from the phase current Iu, Iv, I, of the other winding phase u, v, w, participating in the process of switching The combination of switching signals Si to 56 to switching transistors T1 to T6 and the actual value signals used Uu, U ,, UW

  are shown in Figure 3 in tabular form.

  If, for example, the transistors T 3 and T 5 are momentarily traversed by the current, so

  that the currents of phases I, and -Iv circulate through

  towards the winding phases w, v, then the

  tor T1 is controlled at the opening by the rising edge of the switching signal Si and the comparator K 3 is

  connected to the measuring voltage amplifier MV 1.

  The measuring voltage amplifier MV 1 delivers a signal of real value derived from the measurement voltage U ,, and which constitutes a measurement for the current of

  phase I, circulating in the winding phase u as-

  associated with the transistor Tl With the rising edge of the

  If the flip-flop 27 is positioned, whereby the load transistor 20 is open and the capacitor 17 is loaded, the voltage of the capacitor

  increasing by one function (1 e-t / T) is

  plicated, through the double switch

  closed to the comparator K 3 If the signal of real value

  exceeds the set point signal, an impulse

  switching voltage then arrives via

  from the gate OR OR 3 to the transistor T 3, thanks to which this

  it is open for the duration of the commu-

  mutation despite the suppression of the switching

  As a result of the opening of the transistor T 3, the actual value signal will again pass below

  from the setpoint signal, to the com-

  mutation, on transistor T 3 is deleted.

  cessus repeats until the phase current

  iu in the early phase of switching u, have

  its final value, and that the phase current I, in the winding phase W at the end of switching, has decreased to zero As the actual value signal is slaved to the setpoint signal, the increase in Iu phase current in the phase

  winding up at the beginning of switching u and decreasing

  phase I current in the winding phase.

  At the end of the switching operation w is effected on average according to a function e as predefined by the charging process of the capacitor 17. At the end of the switching process, the winding phases u and v are now traversed by the currents of

  phase I and -Iv The switching process is ter-

  As soon as the voltage on the capacitor 17 exceeds the voltage preset by the voltage divider 24, the switching pulse thus obtained from the comparator 26 resets the flip-flop

  27, whereby the discharge transistor 23 is

  The capacitor 17 is completely discharged even before the switching signal is followed by the opening Q via the Q output of flip-flop 27.

  56 appears at the output of the communication logic.

tation 13.

  The following switching process is

  rolls during the appearance of the rising edge of the signal

  At this switching process,

  the transistors T 5 and T 6 and correspondingly

  the winding phases v and w With the ap-

  switching off the positive edge of the switching signal 56,

  comparator K 5 is connected to the measuring amplifier

  At the same time, the process of loading the con-

  the denser 17 is again started via the flip-flop 27 With the switching pulses

  now appearing in the same way as

  described at the output of the comparator K 5, the transistor

  tor T 5 is controlled at the opening synchronously

  despite the removal of its switching signal.

  55, whereby the phase current -Iv in the winding phase v decreases to zero according to a function e, while the phase current -I1, in the winding phase w, increases from zero to his value

  final according to a function e The process of switching

  When the predetermined final voltage of the capacitor 17 is obtained, the winding phases are traversed by the current and are now the winding phases u and W with the phase currents Iu and -I. The other switching processes

  can be easily followed with the help of

  by table in Figure 3.

  In the case of a controlled EC engine, the

  rotation speed can be controlled by modification

  For this purpose, the current of

  its is modified by synchronization of the transistors T1, T 2, T 3 or transistors T 4, T 5, T 6 during their control phase In the circuit arrangement described here, it is provided for this purpose between the OR gates. OR 4 to OR 6 and the amplifier V 4 to V 6, respectively

  an AND gate 31, which is controlled by

  With a change in the relative duration of this frequency signal, the charging current can be influenced. In a variant, the AND gates 31 can also be arranged between the OR OR g and the OR gates.

  OR 3 and the amplifiers Vl to V 3.

  The invention is not limited to the embodiment previously described. Thus, in the circuit arrangement according to FIG. 1, the six comparators K1 to K6 can be replaced by a single comparator, which will be respectively connected by appropriate multiplexers to the OR gates OR 1 to OR 6 concerned and to the concerned measurement amplifiers MV 1 and MV 6 The desired value signal may have any evolution, for example also a linear increase or decrease The value signal actual can, when picked up with a measuring resistor in the winding phases u,

  v, w, also be taken from the other of the two

  its winding elements participating in the process of

  tion, that is to say on the winding phase u, v, w

  which is associated with the synchronized transistors T1 to T 6.

  In the example of FIGS. 1 and 2, the measurement voltage

  re U, could also be applied for example to the comparator Ki, the measuring voltage Uu to the comparator K 2 and the measuring voltage Uv to the comparator K 3, etc. The measuring voltage can also be taken from the voltage drop of the switches of power Tl to T 6 can be made for example in the form of bipolar transistors or in the form of MOSFET or SENSEFET transistors In this case, it is called the voltage drop on the transistors which is not synchronized during the process

of commutation.

  Instead of getting the switching impulses

  by comparing a setpoint signal

  and a signal of real value by means of a comparison

  it can be provided for the area of overlap

  also switching pulses with a frequency of

  This synchronization frequency is preferably synchronized with the frequency of the synchronization.

  synchronization for controlling the speed of rotation

EC motor.

  As a variant, with respect to the synchronization

  tion of the control signal being effected in the

  circuit circuit according to FIG. 1 for the transistor at the end of switching in the temporary overlap zone A t of the control signals, the control signal can also be synchronized for the transistor at the beginning of switching. In this case, the

  switching signal of the transistor at the end of

  must be extended from the overlap area D t It is also possible to synchronize

  two transistors involved in switching.

  If the neutral point of the armature device 10 is taken out and set to zero potential by means of the resistor 18, the transistors T 4 to T 6 can

then be deleted.

  The control circuit for synchronizing

  switching can be brought together with the

  switching mechanism to form an integral unit

  The control circuit 14 operates independently

  the type of production of the switching signals

  by switching logic 13.

  The setpoint signal can also

  In this case, the Q output of the flip-flop 27 is connected to the base of the discharge transistor 23, and the Q output is connected to the base of the charge transistor. 23 is then commanded to open by the sides of the control signals Si to 56 The set value signal taken from

  of the capacitor voltage then has the evolution of u-

  does function e-t / T discharge transistor 23 is

  blocked, and thus the process of discharging the condensa-

  17 is stopped when the capacitor voltage

  goes below the preset voltage.

  The invention can also be implemented

  for engines with another number of phases or else another phase connection, for example a

triangle connection.

Claims (19)

  1. Circuit arrangement for operating on   a DC voltage network a synchronous synchronous motor   carrying a polyphase armature winding, an arrangement comprising a switching device for successively connecting the winding phases of the armature winding to the DC voltage network, which device comprises a plurality of electronic switches associated with the different windings of phases, and a switching logic being provided for controlling in correct succession the switches by switching signals in accordance with the rotor rotation position of the synchronous motor, circuit arrangement   characterized in that for the switching of two phases   its windings successively traversed by the current (u, v, w), the two switching signals (St 56) for the switches (Tl T 6) associated with the switchable phases temporarily overlap, and in that at least one two switching signals   (St 56) is synchronized in the overlap area   (A t) so that the average value of the winding phase current (IU, Iv, II,) increases in the   winding phase entering into switching and decreasing   in the outgoing switching winding phase, and this preferably, linearly or according to a function e.   2. Circuit arrangement according to the   cation 1, characterized in that the synchronization of the switching signal (St 56) is obtained from   comparison of a signal of real value corresponding to   coupling to the actual evolution of the phase current (Iu, Iv, Ij) in at least one of the switching phases (u, v, w) with a real value signal corresponding to the desired desired evolution of the phase current ( Iur Iv I IW)   3. Circuit arrangement according to the   cation 2, characterized in that the amplitude of the signal   setpoint is slaved to the load current. synchronous motor ge.   4 Circuit arrangement according to any one   of claims 2 or 3, characterized in that   than the voltage of a capacitor (17) during the   its charge or discharge is used.   as a setpoint signal.   5 Circuit arrangement according to any one   of claims 3 or 4, characterized in that   a voltage drop taken from a resistor (18) traversed by the sum of the phase currents,   determines the charging voltage of the capacitor (17).   Circuit arrangement according to the   cation 5, characterized in that the voltage of the capacitor   is compared with a preset voltage in a fixed ratio to the voltage   charge, and that the end of the riding area   (A t) of the switching signals (Sl 56) is determined by the fact that the capacitor voltage   becomes equal to the preset voltage.   7. Circuit arrangement according to any one   conque of claims 2 to 6, characterized in that   the actual value signal is constituted by a   measurement (A ,, U, Uj) which is taken from a   measuring resistor (15) placed in series with the phasor winding (u, v, w).   8. Circuit arrangement according to any one   conque of claims 2 to 6, characterized in that   the actual value signal consists of the voltage drop on the one which is not synchronized of the two electronic switches (Tl T 6) associated with the respectively switching winding phases (u, v, w).   9. Circuit arrangement according to any one   conque of claims 2 to 8, characterized in that   the actual value signal and the value signal of   instructions are likely to be applied to   of a comparator (Ki K 6) whose signals   output are applied as switching signals.   at the control input of the synchro-switch (Tl T 6).   10. Circuit arrangement according to the   9, characterized in that from the vertical flank   as much as or as a descendant of the switching signal (Si 56) respectively produced by the switching logic   (13) is derived a control signal for the association   the comparator output at the control input   of the switch (Tl T 6) to be respectively synchronized.   11. Circuit arrangement according to the   cation 9, characterized in that there is provided a number of comparators (K1 K6) corresponding to the number of switches (Tl T 6), comparators whose outputs   are indirectly or directly related respectively   with a switch control input (Tl   T 6), and whose inputs are respectively   plicated the setpoint signal and one of the   of real value derived respectively from the   phases (Iu, Iv, I,), and in that, from   the rising or falling edge of the switching   (56) respectively produced by the switching logic (13), an activation signal is derived   for the comparator (K K K) connected to the switches   (Tl T 6) to be respectively synchronized his.   12. Circuit arrangement according to the   cation 11, characterized in that the connection of the   from the comparator to the control inputs of the   (Tl T 6) is carried out each time by the in-   an OR gate (OR 1 OR 6), whose other input is connected respectively to the output of the   switching logic (13) to which the signal is   output signal associated with the switch (Tl T 6) consi- ided.   13. Circuit arrangement according to any one   of claims 6 to 12, characterized in that   that the charging voltage of the capacitor (17) is   capacitor (17) via a charge transistor (20), and in that this transistor   charge (20) is likely to be rendered conductive   when the preset voltage is exceeded by the voltage of the capacitors, to be blocked by the   rising edge or the falling edge of the   mutation (Si 56) respectively produced by the than switching (13).   14. Circuit arrangement according to the   cation 13, characterized in that a transistor transistor   charge (23) is connected in parallel with the capacitor   (17), this discharge transistor being made   driver when the preset voltage is exceeded by the capacitor voltage.   15. Circuit arrangement according to the   cation 14, characterized in that a functional flip-flop   transition (27) is linked through the intermediary   its input with each of the switching signal outputs of the switching logic (13), by   through its output Q with the base of the trans-   load sistor (20), and with its output Q with the base of the discharge transistor (23), and in that a comparator (26) is connected on the output side to the reset input (R) of the rocker (27), while it is applied to it, on the input side, the tension   capacitor and the preset voltage, and this comparator   generator generates an output signal when the voltage   of the capacitor has reached or exceeded the over.   16. Circuit arrangement according to any one   of claims 6 to 12, characterized in that   that a discharge transistor is connected in parallel with the capacitor, this discharge transistor being   likely to be made conductive by the vertical flank   the falling edge of the switching signal   produced by the switching logic.   17. Circuit arrangement according to the   16, characterized in that the charging voltage   capacitor is supplied to the capacitor by the   a load transistor, which is capable of   tible to be made conductive when the voltage of the   capacitor crosses down the predetermined voltage   denies and that is likely to be blocked by the flank   amount or the falling edge of the switching signal   tion (Si 56) respectively issued by the logic of switching (13).   18. Circuit arrangement according to the   cation 17, characterized in that a functional flip-flop   transition is connected through   one of his entrances with each of the exits of   switching logic of the switching logic,   through its output Q with the base of the tran-   discharge, and through its   Q with the base of the load transistor, and that a comparator is connected on the output side to the reset input of the flip-flop, while   the input side is applied to the condensate   and the preset voltage, and this comparator deli-   an output signal when the condenser voltage   sator goes down the preset voltage.   19 Circuit arrangement according to any one   of claims 8 to 18, characterized in that   that the electronic switches (T 1 T 6) are   switched in the form of bipolar transistor, MOSFET, or SENSEFET.