FR2646289A1 - INTEGRATED CIRCUIT OF THE MOSFET TYPE, PARTICULARLY LOGIC INVERTER - Google Patents

Abstract

Provided is an integrated circuit having depletion type field effect transistors. According to the invention, it comprises a semiconductor substrate 7 of the p or n type, a source region 10 formed on the main surface of the substrate, a drain region 12 formed close to the source region, an isolation film of gate 16 formed at the surface position of the semiconductor substrate between the source and drain regions, which is not doped with impurities of a conductivity type opposite to the substrate, and a gate electrode 17 formed on the film of gate isolation, having a work function weaker than that of the p-type semiconductor substrate or stronger than that of the n-type semiconductor substrate. The invention applies in particular to integrated circuits.

Description

The present invention relates to an improvement to a transistor

  a depletion type field effect (MOSFET) and in particular an enrichment / depletion type inverter comprising the field effect transistor or FET indicated above and an enrichment type FET and a semiconductor integrated circuit, where FET or inverters

are integrated on a substrate.

  The increase in speed and the increase in the degree of integration of an integrated circuit using MOSFETs has progressed, this being accompanied by the

decrease in size.

  For example, contrary to the fact that in a random access memory "1M D-RAM", the smallest channel length is about 1.3 pim, it is possible to make a MOSFET having a channel length of about 0 , 1.m. Although the switching speed of a semiconductor logic circuit increases with decreasing size, it can be said that its operating speed is generally slower than that of a logic integrated circuit using bipolar transistors. However, the switching speed of the MOSFET increases due to the increase of the mobility and the rate of saturation, if the working temperature is decreased from the ambient temperature (27 C) to the temperature of the liquid nitrogen (- 196 C). Furthermore, it is known that the RC time constant in the wiring is reduced by the decrease in the resistance of the wiring so the working speed of the integrated circuit using MOSFETs can be as high as the working speed of the integrated circuit using transistors. bipolar. It is also known that, since the electric power consumption per door for a MOSFET circuit is smaller than that for an integrated circuit with bipolar transistors, the degree of chip integration is greater than that of the bipolar transistor integrated circuit. Thus, it is possible to achieve a large scale integrated circuit and high integration by attacking the integrated circuit MOSFET at the temperature of liquid nitrogen. Even if a bipolar transistor is attacked at the temperature of the liquid nitrogen, its switching speed is not increased because of the freezing of the layer

basic.

  Until now, the source voltage for the MOSFET was determined at 5V, in order to maintain

  interchangeability with transistor logic

  transistor. However, if the source voltage is maintained at 5V, for a MOSFET having a channel length of less than 1m, the electric field strength in the element increases. Thus, it has become increasingly difficult to provide normal function and good reliability of a MOSFET due to the deterioration of the hot carriers and the failure of the drain. Accordingly, for a MOSFET having a channel length smaller than i m, one can not avoid lowering the source voltage for the integrated circuit. For example, in the case of a channel length of 0.5 μm, it is estimated that it is about 3.3 V in the case of a length of

  channel of 0.1) m, it is estimated of the order of 1 to 1.5V.

  Therefore, accurate MOSFET operation with a channel length smaller than 1 μm at the liquid nitrogen temperature of -196 C can be expected as a high density high speed integrated circuit having both speed as high as that of the integrated circuit using bipolar transistors and high density integration of

integrated circuit to MOSFET.

  Until now, it was considered that, for example, a Josephson logic circuit operating at the temperature of liquid helium (-268.8 C) made it possible to produce a fast integrated logic circuit. However, since a Josephson logic element using the superconducting phenomenon only operates at -268.80C and can not operate at room temperature, its operation can not be verified at room temperature. For example, in the case of the construction of a large-scale computer, it is not possible to quickly change defective patches or plates and in the case of construction

  of a system, it takes a lot of time and work.

  As a result, it is virtually impossible to build a large-scale system. Accordingly, in a system in which an attempt is made to obtain a high performance by a low operating temperature, it is necessary that the device or system can be driven both at room temperature and at low temperature, although its speed is low to

ambient temperature.

  A prior art MOSFET integrated circuit driven at the temperature of the liquid nitrogen is constructed by a complementary type logic circuit (CMOS) composed of CMOS circuits, because their threshold voltage does not vary significantly between the ambient temperature and -196 C. However, as a

  logical circuit structure enrichment / impoverish-

  (hereinafter referred to as the E / D structure) can only be built with n-type channel MOSFETs, the manufacturing process is easier than for a CMOS logic circuit, for which MOSFETs must be p-type channels and n-type channel MOSFETs on the same substrate. On the other hand, as a NAND or NON-OR circuit having n inputs is constructed by 2n MOSFET by the CMOS structure, contrary to the fact that it is constructed by (n + 1) MOSFET by the E / D structure, in the If the same logic circuit is built, the E / D structure has the advantage that it can be built with less MOSFET than the CMOS structure. Accordingly, if a logic circuit of E / D structure can be constructed to such a small size that its channel length is smaller than 0.5 μm and stably attacked at both room temperature and at room temperature. liquid nitrogen, it is possible to achieve, by a relatively simple method, as described above, a high-speed ultra-high density integrated circuit having both the high speed of the bipolar transistor and the high integration density.

of the MOSFET.

  However, a MOSFET logic circuit having an E / D logic structure of the prior art poses the following problems and can not present the

  characteristics described above.

  Fig. 7A shows an example of the prior art E / D inverter circuit, where the reference numeral 1 is an input terminal; 2 is an output terminal; 3 is a source terminal; 4 is a depletion type n-channel MOSFET; 5 is an enrichment type n-channel MOSFET; and 6 is the mass. Since a logic integrated circuit or a memory integrated circuit is constructed by modifying an inverter, it is constructed by two MOSFETs, which are the enrichment-type n-channel MOSFET and the n-channel MOSFET 4 impoverishment. The inverter as described above is the basic unit of the integrated circuit. Since, in general, in Si, electron mobility is more important than hole mobility, n-channel MOSFETs, through which fast operation is possible, are used. In the following explanation, the case where n-channel MOSFETs are used will be taken as an example. Figure 7 shows an example of

  output characteristic of the inverter.

  In the operation of the inverter circuit shown in Fig. 7A, when the input voltage Ven applied to the input terminal 1 is sufficiently lower than VINV, a voltage, which is approximately equal to the applied VDD source voltage at the source terminal 3, is produced at the output terminal 2. When a voltage, which is approximately equal to the source voltage VDD, is applied as the input voltage Ven, the output voltage Vsor is at a level that is almost equal to zero. In practice, the level is not zero but a slight voltage VBAS is produced. Usually, the voltage VBAS is about 1/10 of the voltage of

source VDD.

  DD 'With respect to the SE and SD characteristics of the enrichment-type n-channel MOSFET and the depletion-type n-channel MOSFET, as shown in Fig. 8, the gate voltage for which the drain current ID starts to flow, when the gate voltage VG is applied, i.e. the threshold voltage Vth, is positive (Vth E) for the enrichment type and negative (Vth D) for the type to

impoverishment.

  In order to perform the inverter operation as shown in FIG. 7B, the threshold voltages Vth E and Vth D of the enhancement type MOSFET and the depletion type constituting the inverter are designed to be about 0, 2 VDD and - 0.6 VDD, respectively. FIG. 9 is a cross-sectional view of an example of the structure E / D MOSFET shown in FIG. 7A, which is manufactured by the method

known isolation LOCOS.

  In the figure, the reference numeral 7 is a p-type conductivity Si substrate; 8 is a field oxide film; 9 is a p + doped region (channel stopper); 10 is an n + doped region (acting as the source region S of the enrichment type MOSFET); 11 is another n + doped region (acting as the enrichment type MOSFET drain region D and the depletion type MOSFET source region S formed in the same region); 12 is another n + doped region (acting as the D depletion region of the depletion type MOSFET); 13 is a gate insulation film for the enrichment type MOSFET; 14 is a gate electrode for the enrichment type MOSFET; 15 is an impure doped enrichment-type MOSFET channel doped region of the same conductivity as the p-type conductivity Si; 16 and -17 are a gate oxide film and an electrode of

  gate for the depletion type MOSFET, respectively

  tively; 18 and 18 'are doped impurity-doped depletion-type MOSFET channel regions of p-type conductivity type opposite conductivity type p; 19 is a PSG film (insulating film); 20 is an electrode electrically connected to the gate 16 for the depletion type MOSFET; 21 is a metal Al wiring (ground line); 22 is a metallic Al wiring (source line); 23 is the channel length of the enrichment type MOSFET; and 24 represents the channel length of the depletion type MOSFET. The gate electrodes 14 and 17 are made of n + polycrystalline silicon. Impurity ions such as B, etc., having the same type of conductivity as the p-type conductivity Si substrate 7 are implanted in the channel doped region 15 Just below the gate oxide film 13 for the enrichment-type MOSFET, to adjust the threshold voltage Vth E to be approximately 0.2 VDD with respect to the source voltage VDD. P or As ions, which are impurities having a conductivity of the opposite type to p-type conductivity Si substrate 7, are implanted in the channel doped region 18 Just below the gate oxide film 16 for the MOSFET of the depletion type to adjust its threshold voltage Vth D so that it is approximately -0.6 VDD relative to

the source voltage VDD.

  The electrode 20 electrically connected to the gate electrode 17 of the depletion type MOSFET extends in a plane perpendicular to the sheet. The electrode 20 is made of the same material as the gate electrode for the depletion type MOSFET, i.e. polycrystalline n + Si. The depletion type MOSFET source and the enrichment type MOSFET drain are connected to the n-region 11 by the electrode electrically connected to the gate electrode 17 for the depletion type MOSFET. The electrode 20 serves as an output terminal 2

  of the inverter circuit shown in Figure 7A.

  Since the enrichment-type MOSFET forms an n-type inverted layer in the surface portion of the Si substrate by electrically bending the forbidden band in the surface portion of the p-type conductivity Si substrate by the voltage applied to it. gate electrode, both at room temperature and at the temperature of the liquid nitrogen, it performs an enrichment-type operation, that is, its threshold voltage VthE remains positive. However, although the depletion type MOSFET in which P or As ions, which are impurities having a conductivity of the opposite type to the p-type conductivity Si substrate 7, are implanted to intentionally form the channel 18 'of the n Just below the gate oxide film 16, perform the depletion operation at room temperature, at the liquid nitrogen temperature, as the As or P implanted as conductivity impurities of the opposite type is in the case where no door voltage is applied, no channel layer n is formed which is frozen and un-ionized. Just below the gate oxide film 16 and therefore does not perform operation of impoverishment. In fact, the MOSFET which can perform the depletion operation thanks to impurities implanted with a conductivity of the opposite type performs the operation

  enrichment at the temperature of the liquid nitrogen.

  Accordingly, a problem was posed by the fact that although the prior art inverter of structure E / D using the depletion type MOSFETs comprising the impurity-doped channel portion 18 'of opposite conductivity accomplishes normal operation at room temperature, it can not perform normal operation at the temperature of

liquid nitrogen.

  The logic circuit MQSFET of structure E / D is characterized in that the manufacturing method is easier and the number of MOSFETs during the construction of the same logic circuit is smaller compared to the

CMOS structure logic circuit.

  The operating speed of the logic circuits remains almost equal for the I / O structure and for the CMOS structure and it is also possible, therefore, to increase the speed of operation by the

  operating at the temperature of the liquid nitrogen.

  However, as previously described, the E / D structure inverter using depletion MOSFETs where the channel is doped with impurities of a conductivity of the type opposite to the conductivity type of the semiconductor substrate used, has a disadvantage. in that it can not perform the depletion operation at low temperature because of the impurities that are frozen at this time. It is an object of the present invention to provide a MOSFET capable of performing depletion operation without doping the impurity channel portion of a conductivity type opposite to that of the semiconductor substrate used as well as a method for constructing an inverter. E / D structure

using it.

  A MOSFET according to the present invention is characterized in that the surface portion of a semiconductor body Just below an insulating film, where the gate electrode is disposed, is not doped with impurities of a type. of conductivity opposite to the conductivity type of the semiconductor substrate and in the case where the conductivity type of the semiconductor substrate is p, the working function of the gate electrode is lower than that of the substrate and in the case where the type of conductivity of the substrate is n, the working function of the gate electrode is greater than that of the substrate. If a MOSFET is constructed as described above, the bandgap for the surface portion of the substrate is bent to the negative side by the work function difference in an energy band diagram using the electron energy. Therefore, although the surface portion is not doped with impurities of a conductivity type opposite to that of the substrate, an n-type inverted layer is formed in the surface portion of the substrate. Since the working function hardly varies, depending on the temperature, the n-type inverted layer is formed in the surface portion of the substrate both at ambient temperature and at the temperature of the liquid nitrogen. As a result, the MOSFET built as described above makes it possible to perform the operation

  depletion both at room temperature and at room temperature.

low temperature.

  On the other hand, when constructing an E / D inverter, using a depletion type MOSFET constructed as described above and a prior art enhancement type MOSFET, it can accomplish the inverter operation. both at room temperature and at the temperature of the liquid nitrogen. In particular, at low temperature, it is possible to produce a logic circuit having a high switching speed by increasing the

  mobility or saturation velocity.

  The invention will be better understood and other purposes, features, details and advantages thereof

  will appear more clearly during the description

  explanatory text which will follow with reference to the accompanying schematic drawings given solely by way of example illustrating several embodiments of the invention

and in which: -

  FIG. 1 is a cross-sectional view of an embodiment of the depletion type MOSFET, where the channel portion is not doped with impurities of a conductivity type opposite to that of the substrate according to the present invention; invention; FIG. 2 is a graph showing an example of the measurements of the high frequency curve C-V for the depletion type MOSFET according to the present invention; FIG. 3 is a diagram showing the relationship between the concentration of impurities in the substrate, for which the threshold voltage is negative, and the thickness of the gate oxide film in the embodiment shown in FIG. 1; FIG. 4 is a cross-sectional view of the n-channel MOSFET inverter of structure E / D for the depletion type MOSFET whose channel is not doped with impurities of a type of conductivity opposite to that of the substrate; FIG. 5A is a circuit diagram of the inverter E / D according to the present invention; Fig. 5B is a graph showing an example of the input / output characteristics of the E / D inverter shown in Fig. 5A, for a channel length of 0.5 μm; FIG. 6A is a circuit diagram of the E / D inverter according to the present invention; FIG. 6B is a graph showing an example of the input / output characteristics of the E / D inverter shown in FIG. 6A, for a channel length of 0.1 μm; FIG. 7A is a circuit diagram of a MOSFET inverter circuit according to the prior art of structure E / D; Fig. 7B is a graph showing an example of the input / output characteristics of the prior art MOSFET inverter of the E / D structure shown in Fig. 7A; FIG. 8 is a graph showing an example of the drain current (ID) curves as a function of the gate voltage (VG) of a prior art depletion type n-channel MOSFET and enrichment type. of the prior art; and FIG. 9 is a cross-sectional view of a prior art n-channel MOSFET inverter of structure E / D, for the depletion type MOSFET whose channel is doped with the type of impurity.

  conductivity opposite to that of the substrate.

  The present invention will be explained below with reference to the embodiment shown in the drawings. FIG. 1 is a cross-sectional view of an embodiment of the depletion type MOSFET, where the channel portion is not doped with impurities of a conductivity type opposite to that of FIG.

  substrate according to the present invention.

  In FIG. 1, the same reference numbers as those used for FIG. 7A represent identical or similar parts and 25 is an n + doped region (the source region S of the depletion type MOSFET). The surface channel portion 18 'of the substrate 7 in Si just below the insulating film 16 of the gate electrode 17 is not doped with impurities of a type of conductivity (type n) opposite to that of the substrate. 7. This portion 18 'can be doped with impurities of the same type of conductivity (p type) as the substrate 7. Moreover, the gate electrode 17 is made of a material having a working function, which is lower that the working function of the p-type conductivity Si substrate 7. The substrate 7 in Si may be of n-type conductivity. In this case, the portion 18 'described above is not doped with p-type conductivity impurities and the gate electrode 17 is made of a material having a larger working function than that of the substrate 7. In this case also the portion corresponding to the portion 18 'indicated above may be doped with impurities of the same type of conductivity

that the n-type substrate.

  The basic structure is identical to that of an enrichment type n-channel MOSFET manufactured by the LOCOS isolation method and its manufacturing method

  is identical to the well known method of n-channel MOSFET.

  the isolation of the elements may be done by any method of isolation other than isolation

  LOCOS if the elements can thus be isolated.

  If the gate electrode was made of n + type polycrystalline silicon, it would be a MOSFET with

  channel n of the usual enrichment type.

  One of the features of the present invention resides in the fact that the gate electrode is not made of n + type polycrystalline silicon.

  but in a material having a small work function.

  The material for the door electrode needs to have a lower working function than about 4eV and it is desirable that the working function be as low as possible. Simple metals such as Mg, Sc, Y, Ba, La, Ce, -Pr, Nd, Er etc., and compounds such as LaB6, etc. can be used for this purpose. Among them, it is desirable to use La, Mg or LaB6 because they are suitable for the conventional silicon process and have a high melting point and high workability. In particular, LaB6 has a work function of about 2.5eV and it belongs to the group with the smallest work function among the materials described above. Moreover, its melting point is greater than 800 C and it is chemically stable. In addition, since a thin film of LaB6 can easily be formed by the well-known method of evaporation of an electron beam and the crystallographic orientation can be controlled by selecting the evaporation condition,

  LaB6 is one of the most desirable materials.

  In the embodiment according to the present invention, Mg, La and LaB6 have been used for the gate electrode 17. However, other materials may be used if they have a lower working function than about 4eV, if they are chemically stable and if they

  have a melting point greater than 800 C.

  When a material having a work function lower than 3.5 eV is used for the gate electrode, the band gap in the surface portion Just below the gate oxide film is bent by the working function difference between the material and the p-type conductivity Si and the surface portion is reversed to the n-type conductivity. Indeed, it is possible to form the n-type channel mouth in the surface portion Just below the gate oxide film without intentionally forming the n-type region by implanting P or As ions, which are impurities of a conductivity type opposite to the conductivity type of the substrate, by the implantation of ions in the channel portion 18 'of the p-type conductivity Si substrate just below the oxide film

door 16.

  FIG. 2 is a graph showing an example of the measurements of the high frequency CV curve of a MIS diode between the gate electrode 17 and the p-type conductivity Si substrate 7 for a frequency of about 1 MHz to a temperature of 27 C, for example, when the impurity concentration in the p-type conductivity Si substrate is 1x10 6 cm 3; the gate oxide film is about 20 nm thick; and the LaB6 gate electrode is about 500 nm thick. The threshold voltage, at which the surface portion of the p-type conductivity Si substrate of the MIS diode was inverted, was about -1.6V. The C-V curve obtained at the temperature of the liquid nitrogen was approximately equal to that obtained at ambient temperature and the threshold voltage was also equal to that obtained at the temperature

  ambient, that is, about -1.6V.

  In the current drain (ID) gate-voltage characteristics (VG) of the enrichment-type MOSFET having a channel length of about 1pm, D was about -1.6V as well at ambient Vtb On the other hand, in the case where the dimensions previously described and a gate electrode made of Mg were used, the threshold voltage was approximately -0.9V both at room temperature and at room temperature.

-196 C.

  As explained in the above embodiment, it is possible to transform the threshold voltage to a negative value by using a material having a small working function for the gate electrode without intentionally doping the portion of the gate. p-type conductivity Si substrate just below the gate oxide film by impurities (P, As, etc.) of a conductivity type opposite to that of the

substrate.

  The condition at which the threshold voltage is converted to a negative value depends mainly on the resistivity of the p-type conductivity Si substrate and the thickness of the gate oxide film and not on the thickness of the gate oxide film. door electrode. In the case where LaB6 is used, the threshold voltage also depends slightly on the orientation of the crystallographic surface of the LaB6 film and changes approximately

0.3V depending on the orientation.

  For example, in the case where the impurity concentration in the p-type conductivity Si substrate is about 1 × 10 17 cm -3 (resistivity about 1.52% cm), when LaB6 is used for gate electrode and the thickness of the gate oxide film is lower than about 40 nm, the threshold voltage is negative. Figure 3 shows the relationship between the impurity concentration NA in the p-type conductivity Si substrate whose threshold voltage has turned into a negative value using LaB6 and Mg for the gate electrode and the thickness H of the gate oxide film. For example, when the thickness of the gate oxide film and the impurity concentration are in a region below the respective line (hatched region) of Figure 3, the threshold voltage is

  negative. The MIS diode, for which the characteristics

  FIGS. 2 and 3 are a sample, where the density at the interfacial level is, for example, from 1 to 2 × 10 10 cm -3. In the case of the n-channel MOSFET, if the density at the interfacial level is high, as the threshold voltage increases in the negative direction, an interfacial density greater than 2x101 cm 3

can also be used.

  For MIS diodes having different densities at the interfacial level, the characteristics shown in FIGS. 2 and 3 are different. In any case, in order to transform the threshold value to a negative value, it was necessary to use a material having a small work function for

the door electrode.

  As described above, although the threshold voltage is negative for the n-type MOSFET, for the E / D structure inverter, the magnitude of the threshold voltage is a problem. For the E / D structure inverter, the threshold voltage VINV of the inverter is defined as a voltage for which the output voltage Vsor is equal to the input voltage Ven in the

  inverter characteristics shown in Figure 7B.

  By a well known method of design, the threshold voltage of the inverter is set at -0.6 VDD so the switching speed remains close to equal to the switching on and off of the input voltage at about half the source voltage VDD of the inverter. Accordingly, in the case where the source voltage VDD is 5V, the threshold voltage of the MOSFET of the

  depletion type is about -3V.

  In the high-speed, high-speed, MOSFET logic circuit which is the subject of the present invention, as it consists of precise MOSFETs, whose channel length is smaller than about 0.5 μm, the voltage threshold is about 3.3V, when the channel length is about 0.5pm, and 1.5V when it is about 0.1 plm. Therefore, the threshold voltage of the depletion type MOSFET should be set to about -2V, when the channel length is about 0.5 μm and -0.6 to -0.6V when it is 0,1.m. As shown in the examples shown in FIGS. 2 and 3, a threshold voltage of about -1.7V could be obtained in the embodiment of the depletion type MOSFET according to the present invention. On the other hand, it is possible to control the gate voltage in a region from -2V to OV in implantation B, etc., which are impurities of the same conductivity type as the p-type substrate, in the channel portion. , even if the door oxide film has a certain thickness. In the depletion type MOSFET according to the present invention, the lower limit of the threshold threshold voltage, when using a gate made of LaB6 and when the impurity concentration in the p-type conductivity substrate is used. For example, it only reaches 1x105cm-3 and the gate oxide film is as thin as 5 nm, is about -2V. Accordingly, the depletion type MOSFET according to the present invention can be used for the E / D structure inverter using precise MOSFETs, whose channel length is smaller than 0.5 μm, where the oxide film the gate should be as thin as about 5 to 20 nm and the

  Source voltage should only reach about 1 to 3.3V.

  One embodiment of the E / D structure inverter using a gate electrode made of

  LaB6 or Mg is shown in Figure 4.

  In the figure, reference numerals identical to those shown in FIG. 1 represent identical or corresponding articles and 26 is the channel portion of the depletion type MOSFET, which is not doped with impurities of a type of conductivity opposite to that of the substrate. The basic structure is

as following.

  An integrated circuit comprising the E / D structure inverter indicated in FIG. 4 comprises a p or n type semiconductor substrate 7; a source region of an enhancement type MOSFET and a drain region of a depletion type MOSFET at a distance on the main surface of the semiconductor substrate; a stream-like common region 11 serving as the MOSFET drain region of the

  enrichment and source region of the MOSFET type.

  depleting between the source region of the enrichment type MOSFET and the depletion type MOSFET drain region; a gate insulation film 16 for the depletion type MOSFET formed on the surface portion 15 of the semiconductor substrate between the depletion type MOSFET drain region and the common region, which portion is not doped impurities of a conductivity type which is opposite to that of the semiconductor substrate; and a gate electrode 17 for the depletion type MOSFET which is formed on the gate isolation film for the depletion type MOSFET; an electrode 20 formed on the common region and electrically connected to the gate electrode for the depletion type MOSFET; a gate insulation film 13 for the enrichment type MOSFET formed on the surface portion 26 of the semiconductor substrate between the source region of the enrichment-type MOSFET and the common region, which portion is not doped impurities of a conductivity type which is opposite to that of the semiconductor substrate; and a gate electrode 14 for the enrichment type MOSFET which is formed on the enrichment-type MOSFET gate insulation film; at least one gate electrode for the depletion type MOSFET at a working function which is lower than that of the p-type semiconductor substrate in the case where the semiconductor substrate is of p-type conductivity greater than that of the substrate type n semiconductor in the case where the semiconductor substrate is

n-type conductivity.

  As a manufacturing method of the embodiment described above, the method MOS using

  the well-known LOCOS isolation technique was used.

  Isolation can be done using any method other than the LOCOS isolation method. You just have to be able to isolate different elements. However, in contrast to the well-known MOS method, the p-type portion of the p-type Si 26 which lies just below the gate oxide film 16 in the depletion type n-channel MOSFET is not doped with implantation of ions etc ..., by means of impurities such as As and P having an opposite type of conductivity. On the other hand, LaB6 or Mg is used for the gate electrode 17 of the depletion type n-channel MOSFET. The gate made of LaB6 was formed using the well known method of electron beam evaporation. That made of Mg was formed using the well known method of electron beam evaporation or the spraying method. The source and drain region of the depletion type n-channel MOSFET was formed by P ion implantation after

the LaB6 door electrode.

  On the other hand, for the gate electrode 14 of the enrichment type MOSFET, Si

  conventional polycrystalline n + type.

  For example, the LaB6 gate electrode 17 is not formed by a single layer as shown in FIG. 4 but may have a two-layer structure consisting of a polycrystalline or n + type silicide layer which is formed on the layer

from LaB6.

  In order to control the threshold voltage of the enrichment-type MOSFET, ions of B, which are impurities of the same conductivity type as the p-type conductivity Si, were implanted in the channel portion prior to forming the film. 13. The ions of B have been implanted so that the threshold voltage Vth E is about 0.7V for a MOSFET having a channel length of about 0.5 pn and that the threshold voltage Vt E is about + 0.3V for a MOSFET with a th

channel length of 0.1) lm.

  Furthermore, in order to control the threshold voltage of the depletion type MOSFET, ions of B, which are impurities of the same conductivity type as the p-type conductivity Si substrate, have been implanted in the channel portion. prior to formation of the gate oxide film 2. The B ions were implanted so that the threshold voltage Vth D is about -2V for a MOSFET having a channel length of 0.5 μm and the threshold Vth D is about -1V for a MOSFET

  having a channel length of 0.1 μm.

  Although in the present embodiment impurities of the same deconductivity type as the p-type conductivity Si have been implanted for controlling the threshold voltage, ion implantation is not necessarily performed if the voltages the enrichment-type MOSFET threshold and the depletion-type MOSFET are approximately 0.2VDD and about -O, SVDD, respectively, relative to

VDD source of the inverter E / D.

  If P or As ions, which are impurities of a type of conductivity opposite to that of p-type Si, were implanted in the channel portion in the manufacture of the depletion type MOSFET according to the technique of the art former, although an n-type channel is formed, performing the room-temperature depletion type operation at the liquid nitrogen temperature (-196 ° C), such as impurities of P or As implanted as n-type conductivity impurities would be exhausted, n-type channel layer would not form and depletion-type operation could not be accomplished. However, in the case where the channel portion is doped with p-type conductivity impurities with respect to p-type conductivity Si only in order to change the concentration, as there is no gel, this previously described gel It has no influence either at ambient temperature or at -196 C. Therefore, the inverter E / D according to the present invention makes it possible to perform a normal inverter operation both at

room temperature at -196C.

  Figs. 5B and 6B show the input / output characteristics of the E / D inverters shown in Figs. 1A and 6A using MOSFETs having a channel length of about 0.5 μm and a channel length of about 0.1. Fm, respectively. The source voltage VDD is about 3.3V for an inverter and has a channel length of about 0.5 pn and about 1.5V for an inverter having a channel length of about 0.1 pm . The input / output characteristics shown in FIGS. 5B and 6B were obtained at both room temperature and -196 C. In contrast to the fact that the E / D inverter using conventional depletion-type MOSFETs did not perform operating normal to -196 C, the inverter E / D according to the present invention performs normal operation

  both at room temperature and at -196 C.

  An annular oscillator was constructed by connecting the E / D inverters described above in several stages and the delay time per gate was measured at room temperature and at -196 C. It was found that it was shortened by about 0.7 to 0.5 times at -196 C compared to

  that obtained at room temperature.

  Although in the embodiment described above, for the substrate, Si of the conductivity type p has been used, in the case where n-type Si is used for the substrate, it is possible to construct a depletion type p-channel MOSFET and an E / D structure inverter without doping the channel portion of the B-depletion type MOSFET, which is a

  impurity of a type of conductivity opposed to Si of the type n.

  For the gate electrode of the depletion-type p-channel MOSFET, among the materials having a larger working function than the n-type conductivity Si, it is possible to use Se, Ir, Pt, etc. which are materials with a larger work function than about 5.5eV. However, Pt is preferably used which can easily be formed by the electron beam evaporation method.

  etc ... and whose melting point is about 1770 C.

  By using a door electrode made of platinum, it

  It has been possible to obtain an impoverished type MOSFET

  performing its depletion operation both at room temperature and at low temperature, and

  to obtain a p-channel inverter of structure E / D.

  The depletion type MOSFET according to the present invention can operate at both room temperature and liquid nitrogen temperature and also the E / D structure inverter can operate at both room temperature and at room temperature.

temperature of the liquid nitrogen.

  A MOSFET integrated circuit using depletion type MOSFETs and E / D structure inverters can produce a high density, very fast integrated circuit having both the high speed of the integrated circuit using bipolar transistors and the high degree of efficiency. integration of the MOSFET by attacking it at

temperature of the liquid nitrogen.

  Moreover, unlike the CMOS structured inverter, the E / D structure inverter can give a high speed and high density integrated circuit using a simple manufacturing process and a small

number of MOSFETs.

  Furthermore, since the MOSFET integrated circuit according to the present invention can operate both at room temperature and liquid nitrogen temperature, during the construction of a system, it is possible to verify its operation at the same time. room temperature for the exchange of defective pellets and boards, to check the normal operation of the system and then to derive the system having the highest performance of operation at the temperature of

liquid nitrogen.

Claims (7)

  An integrated circuit of the type comprising depletion field effect transistors, characterized in that it comprises: a p-type conductivity semiconductor substrate (7); a source region (10) formed on the major surface of said semiconductor substrate; a drain region (12) formed near said source region on the major surface of said semiconductor substrate; a gate insulating film (16) formed on the surface portion of said semiconductor substrate, between said source region and said drain region,   which portion is not doped with impurities.   n-type conductivity; and a gate electrode (17) formed on said gate insulating film, having a working function - similar to that of said p-type conductivity semiconductor substrate. Integrated circuit according to Claim 1, characterized in that the surface portion of the semiconductor substrate between the source region and the drain region, which is not doped with n-type conductivity impurities, is not doped with impurities of the same type   conductivity as the semiconductor substrate.   An integrated circuit of the type comprising depletion field effect transistors characterized in that it comprises: a semiconductor substrate (7) of n-type conductivity; a source region (10) formed on the major surface of said semiconductor substrate; a drain region (12) formed near said source region on the major surface of said semiconductor substrate; a gate isolation film (16) formed on the surface portion of said semiconductor substrate, between said source region and said drain region, which portion is not doped with p-type conductivity impurities; and a gate electrode (17) formed on said gate insulating film, having a larger working function than said semiconductor substrate conductivity type n.   An integrated circuit according to claim 3, characterized in that the surface portion of the semiconductor substrate between the source region and the drain region, which is not doped with p-type conductivity impurities, is not doped with impurities of the same type   conductivity as the conductive substrate.   5. Integrated circuit of the type comprising at least one inverter E / D, characterized in that it comprises: a semiconductor substrate (7) conductivity of the p or n type; a source region (10) of an enhancement type MOSFET and a drain region of a depletion type MOSFET at a distance on the main surface of said semiconductor substrate; a stream-like common region (11) serving as a drain region of said enhancement type and source region MOSFET of said depletion type MOSFET between said source region of said enhancement MOSFET and said drain region; Depletion MOSFET; a gate isolation film (16) for said depletion type MOSFET formed on the surface portion of the semiconductor substrate between the depletion type MOSFET drain region and the common region, which portion is not doped with impurities of a conductivity type that is opposite to the conductivity type of the semiconductor substrate; a gate electrode (17) of the depletion type MOSFET formed on the depletion type MOSFET gate insulation film; an electrode (20) formed on the common region and electrically connected to the gate electrode of the depletion type MOSFET; an enhancement type MOSFET gate-insulating film (13) formed at the surface portion of the semiconductor substrate between the source region of the enrichment-type MOSFET and the common region, which portion is not doped with impurities of a conductivity type which is opposite to the conductivity type of the semiconductor substrate; and a gate electrode (14) for said enhancement type MOSFET formed on the gate isolation film for said enrichment type MOSFET; at least the bearing electrode of the MOSFET of the   depletion type has a work function that is-   lower than that of the p-type semiconductor conductivity substrate in the case where said semiconductor substrate is of p-type conductivity and greater than that of the n-type conductivity semiconductor substrate in the case where said substrate   semiconductor is of n-type conductivity.   6. Integrated circuit according to any one of   1, 3 or 5, characterized in that the   distance between the source region and the drain region at the surface of the semiconductor substrate is smaller than 0.5 μm.   7. Integrated circuit according to any one of   1, 3 or 5, characterized in that the   source-drain voltage of the single depletion-type field effect transistor, or the voltage between the enrichment / depletion-type inverter ground and the depletion-type field effect transistor drain, or the supplied voltage to the semiconductor integrated circuit is less than 50 V DC.