FR2637098B1 - Dispositif generateur d'adresse logique pour une instruction specifiant deux mots, divises chacun en deux parties - Google Patents

Dispositif generateur d'adresse logique pour une instruction specifiant deux mots, divises chacun en deux parties

Info

Publication number
FR2637098B1
FR2637098B1 FR898912582A FR8912582A FR2637098B1 FR 2637098 B1 FR2637098 B1 FR 2637098B1 FR 898912582 A FR898912582 A FR 898912582A FR 8912582 A FR8912582 A FR 8912582A FR 2637098 B1 FR2637098 B1 FR 2637098B1
Authority
FR
France
Prior art keywords
words
divided
parts
generating device
logical address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR898912582A
Other languages
English (en)
Other versions
FR2637098A1 (fr
Inventor
Yasushi Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of FR2637098A1 publication Critical patent/FR2637098A1/fr
Application granted granted Critical
Publication of FR2637098B1 publication Critical patent/FR2637098B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System (AREA)
FR898912582A 1988-09-26 1989-09-26 Dispositif generateur d'adresse logique pour une instruction specifiant deux mots, divises chacun en deux parties Expired - Fee Related FR2637098B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63238861A JPH0289132A (ja) 1988-09-26 1988-09-26 論理アドレス生成方式

Publications (2)

Publication Number Publication Date
FR2637098A1 FR2637098A1 (fr) 1990-03-30
FR2637098B1 true FR2637098B1 (fr) 1992-08-21

Family

ID=17036352

Family Applications (1)

Application Number Title Priority Date Filing Date
FR898912582A Expired - Fee Related FR2637098B1 (fr) 1988-09-26 1989-09-26 Dispositif generateur d'adresse logique pour une instruction specifiant deux mots, divises chacun en deux parties

Country Status (3)

Country Link
US (1) US5136699A (fr)
JP (1) JPH0289132A (fr)
FR (1) FR2637098B1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08241325A (ja) * 1995-03-03 1996-09-17 Matsushita Electric Ind Co Ltd 電子辞書及びその製造方法並びにインデックス圧縮・伸長装置
US5765220A (en) * 1996-06-18 1998-06-09 Hewlett-Packard Company Apparatus and method to reduce instruction address storage in a super-scaler processor
US6687806B1 (en) * 2000-06-15 2004-02-03 Advanced Micro Devices, Inc. Apparatus and method for generating 64 bit displacement and immediate values
US7299338B2 (en) * 2002-12-04 2007-11-20 Agere Systems Inc. Vector indexed memory unit and method
US20060004316A1 (en) * 2004-07-02 2006-01-05 Difiore Attilio E Reduction of recirculation in catheters
US9081657B2 (en) * 2011-10-13 2015-07-14 Conexant Systems, Inc. Apparatus and method for abstract memory addressing
US8850109B2 (en) * 2011-12-22 2014-09-30 Avago Technologies General Ip (Singapore) Pte. Ltd. Content addressable memory data clustering block architecture
US11693800B2 (en) * 2020-07-13 2023-07-04 EMC IP Holding Company LLC Managing IO path bandwidth

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2230258A5 (fr) * 1973-05-16 1974-12-13 Honeywell Bull Soc Ind
FR122199A (fr) * 1973-12-17
US3949378A (en) * 1974-12-09 1976-04-06 The United States Of America As Represented By The Secretary Of The Navy Computer memory addressing employing base and index registers
US3976978A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Method of generating addresses to a paged memory
US4240139A (en) * 1977-09-22 1980-12-16 Tokyo Shibaura Denki Kabushiki Kaisha Address generating system
US4206503A (en) * 1978-01-10 1980-06-03 Honeywell Information Systems Inc. Multiple length address formation in a microprogrammed data processing system
NL7807314A (nl) * 1978-07-06 1980-01-08 Philips Nv Inrichting voor het vergroten van de lengte van een logisch computeradres.
US4373182A (en) * 1980-08-19 1983-02-08 Sperry Corporation Indirect address computation circuit
JPS58214947A (ja) * 1982-06-09 1983-12-14 Nec Corp 情報処理装置
EP0148478B1 (fr) * 1983-12-23 1989-08-09 Hitachi, Ltd. Processeur de données avec commande de longueur de bit significative de registres généraux
JPS63147229A (ja) * 1986-12-10 1988-06-20 Nec Corp マイクロプログラム制御装置

Also Published As

Publication number Publication date
JPH0289132A (ja) 1990-03-29
FR2637098A1 (fr) 1990-03-30
US5136699A (en) 1992-08-04

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Legal Events

Date Code Title Description
ST Notification of lapse