FR2626421A1 - DECIMATED DIGITAL FILTER, ANALOG / DIGITAL CONVERTER INCLUDING APPLICATION AND ANALOG / DIGITAL CONVERSION METHOD - Google Patents

Abstract

The digital decimating filter receives a stream of input digital samples and provides an output stream corresponding to a lower frequency. The filter 10 has a register 16, which stores several input samples xi and derives therefrom samples yi of the output stream. It makes an output sample yi available at all times, so that the phase of that sample is selectable. The high rate stream can be generated by a delta-sigma modulator to form an analog-to-digital converter. It is also possible to constitute a multi-mode modem intended to be used in connection with a transport channel of a modular carrier according to two possible modulation schemes. By using a circuit comprising an analog / digital converter of the above type feeding a programmable digital filter having a selectable filtering function, it is possible to avoid having to provide several different input filters.

Description

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  VF: R T f ANAl i '. IF IlmAN TF DII The present invention relates generally

the field of digital filtering.

  It has already been proposed to place a digital low-pass filter with decimation (or subsampling) at the output of an analog / digital converter (ADC) to give the ADC a resolution in increased amplitude.

  by oversampling the analog signal, i.e.

  say by sampling at a multiple of the Nyquist frequency. In a digital decimation filter, the output sampling frequency is lower (for example 100 times lower) than the frequency of the

input samples.

  Candy's article "Decimation for Sigma Delta Modulation" in IEEE Trans. on Comm., January 1986, shows that, for ADCs which use second order sigma-delta modulation, a frequency response close to the optimum for the decimation filter is: H (f) = sin3 (Nf / f ) / sin3 (, f / f5) ss

  o N is the decimation rate (ratio between the

  input sampling rate --f5-- and frequency

output sampling).

  The article by Huber et al., "FIR Lowpass Filter for Signal Decimation ...", ICASSP. 1986, Tokyo, describes a decimation filter which does not require explicit multiplication and makes it possible to obtain the desired response for use with a delta-sigma modulator using a finite impulse response filter (abbreviated FIR) followed by cascading accumulators. The decimation is

  performed by a separate block that follows the filter.

  Analog to digital converters are used, for example, in modems to convert the analog line signal into a digital signal. In representative echo cancellation modems, both echo cancellation and resampling are performed in the analog domain and are followed by a con-

  analog / digital version with relatively low reso-

  lution. Modems which must work with other communication schemes, for example in multiplexing with

  frequency division, require other filter filters

  ception. We can make a multimode modem with

  multiple analog receive filters, selectable

by program.

  According to one aspect of the invention, a naked filter

  decimation meric intended to receive a flow of sample

  digital input tillons at a sampling frequency

  input tillons and providing a corresponding stream of digital output samples at a different frequency of output samples includes means for storing the digital input samples; the output stream samples are generated from the stored digital input samples; and one

  output sample is made available to be in-

  clus in the output stream at any time, so that the output sample can be pointed with a phase

selectable.

  Specific modes of carrying out the

  vention have one or more of the following characteristics. Filtering can be done by a stage of

  filtering without decimation followed by a decimation stage.

  integration and "emptying" or restitution. An exchange

  output pin can be made available at any time

  ment by providing a pair of integration and restitution circuits operating in such a way that. when

  one of the integrated circuits, the most recent sample

  ment created by the other integration and restitution circuit

  tution is available to be inserted into the output stream. According to another general aspect of the invention, a DAC has a sigma-delta modulator intended to generate a high-speed stream of digital samples of an analog signal at a frequency substantially higher than the Nyquist frequency and a digital filter to decimation for receiving the high bit rate stream and providing a corresponding stream of filtered digital output samples at a lower bit rate, the decimation ratio

being selectable.

  Specific modes of carrying out the

  vention incorporate one or more of the

  following questions. The digital decimation filter includes

  carries a finite impulse response filter having successive storage elements for storing digital samples at high frequency and a cartographic element for converting a set of signals taken from only part of the storage elements into a value stream, l being a cartographic element

  configured to get the desired impulse response

  rée. The cartographic element does not perform multi-

  explicit plications. The particular storage elements

  liers from which the signal set is taken are selected according to the desired decimation ratio, using a multiplexer having inputs

  connected to several of the storage elements.

  Yet another general aspect of the invention

  relates to a multi-mode modem intended to be used

  reads with a channel on which a carrier can be mo-

  dule according to at least two possible modulation schemes

  different, the channel being of a type which causes echoes and the modulation schemes incorporating

  means to avoid the effects of echoes: the

  modulated teuse from the channel is converted to a

  corresponding flow of digital samples by a cir-

  receiving bake which has a CAN supplying a bare filter

  meric programmable so as to provide, at will, filtering functions applicable respectively to the two different modulation schemes with echo cancellation, so that it is not necessary to provide,

  at the head of the CAN, different reception filters

  applicable to the different modulation schemes. In

  particular embodiments, the modula-

  tion involves echo cancellation or multiplexing

frequency distribution.

  The invention makes it possible to produce a digital filter.

  that which is simple, requires only a small volume of met

  moire, has a selectable decimation ratio and has a selectable output phase: the filter does not require

  no compute or store prime coefficients

  get explicit. It does not require explicit multiplication

  quote. A filter-based ADC can have a resolution

  high tion and a variable decimation ratio, while remaining moderately priced. Multiple modes can

  be processed using a single digital filter

  grammable. The invention will be better understood on reading

  the following description of particular modes of realization

  sation, given by way of nonlimiting examples. The

  description refers to the accompanying drawings, in

which:

  - Figure 1 is a block diagram of a nu-

  decimation meric: - Figure 2 is a block diagram of a modem: - Figure 3 is a block diagram of a possible embodiment of parts of the modem of Figure 2: and - Figure 4 is a block diagram of a fraction

a multi-mode modem.

  The digital decimation filter 10 shows in

  Figure 1 receives a stream of digital input samples.

  ques to a single bit xi (with i = 0, 1, ...), to a fre

  quence of fs input samples, on an input line

  trée 12. It provides a corresponding stream of digital output samples yi (with i = 0. 1, ...) on an output line 14 at a frequency selected from K different output frequencies fk less than fs

  with a selectable output phase.

  The samples xi on the input line 12 are introduced into a serial shift register 16 and shifted at the rate of input clock pulse on a line 18. The shift register 16 has 2N + 1 elements, N being the desired maximum decimation ratio (for example fs / fmin where fmin is the lowest desired output frequency) x0 is the element which retains the most recently loaded sample and x_2N retains

the oldest sample.

  At each clock pulse on line 18, three of the samples in the shift register are applied to the three address input lines 22. 24 and 26 of a map element 28 (for example a

  consultation table). The sample applied to the li-

  addressing gene 22 is always taken from element x0 of the shift register 16. The sample applied to the address line 24 is taken from one of the K different elements of the shift register (where the K elements

  different include the element x N and the elements ad-

  adjacent) via a K: i multiplexer

  hindered by 30, under the control of a control signal from the

  decimation report, applies on line 32. The if-

  general command also governs a second multiple-

  34 type K: 1 xer, that is to say to select

  one of K different samples (taken from

  element x_2N and adjacent elements) for the application

line 26.

  The cartographic element gives a map of each

  that possible combination of the three address bits to constitute a corresponding output value intended to carry out the impulse response function which will be described later. The successive output values of the element 28 are supplied at the frequency of the input clock 18 to two cascade integrators 36 and 38 which each include a summator 40. 42 and a

  delay delay element 44, 46 (providing a re-

  late equal to a clock pulse duration) also

  triggered by input clock pulses at fre-

  quence f coming from line 18. The output of the lnté-

s

  grator 38 is supplied simultaneously to a pair of

  integration and restitution cooked 48 and 50 assembled in

  parallel. Each integration and restitution circuit

  tion comprises an adder 52, 54 and a loop delay element 56, 58. The delay elements are clocked by input clock pulses at frequency f (coming from line 18) and are set respectively

  zero by pulses "Even reset" and "Odd reset" four-

  nies (like even and odd control signals) by

  an output control circuit 60 from the pulses

  input sampling clock on line 64. The pulses "Even reset" and "Odd reset" are alternated and both appear at the same frequency fs / 2Nk, where Nk is the decimation rate or ratio actually selected. The "even" and "odd" control signals from the output control circuit 60 also include "even" and "odd" carry signals which are applied during the

  even and odd output sample periods.

  The outputs of the two integration circuits and

  are provided alternatively, by the ln-

  through a 2: 1 multiplexer designated by 62 (com-

  ordered by an even / odd signal on line 64, appears

  falling at the frequency fs / 2Nk and coming from the clock divider 60) on an output line 14. Since there are two integration and restitution circuits operating alternately and a multiplexer, there is always a sample available, and this sample can be used at any time to authorize a continuation, for example the pursuit of a clock presenting

possibly a jitter.

  The element 28 is produced in such a way that the overall frequency response of the filter 10 is close to the optimum for the use downstream of a second order delta-sigma modulator (not shown in FIG. 1). i.e. having the transfer function H (f) = sin3 (fNkf / fs) / sin3 (if / fs)

  Filter 10 has a cor- rect impulse response.

  corresponding, based on the following principles.

  First, the two-stage filter without

  decimation including the shift register 16, the element

  ment 28 and two integrators 36 and 38. supplied in its

  together the frequency response required for a module-

  delta-sigma of the first order: H (f) = sin2 (wNkf / fs) / sin2 (wf / fs) k s s The impulse response of this part without decimation is:

h (i) = s (i) * s (i).

  o * denotes the convolution operator and: S (1) = 1, for n = O, 1, 2 .... Nk-l,

= O. otherwise.

  and o the frequency response of the filter whose impulse response is s (i) is: S (f) = sin (vNkf / fs) / sin (wf / fS) Then: of (i) = d (i) * s (i) * d (i) * s (i) d (i) = x (i) - x (i-1), and d (i) * I (i) = 1, for i = 1 = O, if not

  We see that d (i) and I (i) are inverse operations.

  We can therefore implement h (i) using a fil-

  tre having the answer f (i) followed by a cascade of two

  Integrating floors. By calculation from equations

  tions above, we can show that: f (i) = 1, for i = O -2, for i = Nk 1, for i = 2Nk

O, in other cases.

  The impulse response represented by f (i) is implemented by providing element 28 so that it

  provide, during the i-th sampling interval,

  ge, an output (zi) determined by the equation: zi = xi - 2xi-N + Xi-2n

  The two-stage filter without decimation is followed

  vi by an integration and restitution filter, with decima-

  tion, whose frequency response is H (f) = sin (1 * Nk * f / fs) / sin (w * f / f5) We can implement the integration filter and

  restitution by resetting an accumulator and ac-

  accumulating N samples of input data for calculation

a single output sample.

  To modify the decimation rate, simply change the locations of the sockets using the multiplexers 30 and 34 according to the above equations and change the divider in the control circuit of

exit 60.

  We will use for example the sockets O. 65 and 130 for a decimation rate of 65. In general, we

  will use the 0, Nk and 2Nk sockets for a deci-

mation Nk.

  In an example application shown in Figure 2, the digital filter 10 (Figure 1) is part of a CAN 110 high resolution (15 bit) in a modem 112 full duplex and echo cancellation operating according to the CCITT recommendation

  V.32. In modem 112, the digital data to be transmitted-

  be from data terminal equipment (DTE) 114 go through a modulator / demodulator 115, a CAN

  116 has delta-sigma modulation on 14 bits, a step filter

  se-bas analog 120, a transmission gain block

  122, a continuous analog low-pass filter 124, a circ

  CUlt hybrid 133, and a line interface 126 to a two-wire telephone line 128. The incoming analog signal, received on line 128, also passes through

  the interface 126. The hybrid circuit 133 isolates it and in-

  channel, through a continuous analog low-pass filter

  134, a reception gain block 130, a pass filter

  broadband analog band 132, CAN 110 of 15

  bits, a programmable reception filter (

  echo) 111 and modulator / demodulator 115 to

  DTE 114. Filters 124, 120. 132 and 134 are confi

  guré to model the band in a way adapted to the telephone line 128, but they are specific to any mode of communication on the line 128 (for example suppression

  frequency division multiplexing). Thread-

  Communication mode specific trage (in this case echo cancellation) is performed in the reception filter 111.

  FIG. 3 shows a possible embodiment

  ble of the modem of figure 2. The functions, in the do-

  analog main, from the CAN 116 low pass filtering part, the 120 low pass filter, the gain block

  122, low-pass filter 124, low-pass filter

  below 134. of the reception gain block 130, of the filter

  bandpass 132, and the sigma-del- modulation function

  the analog of CAN 110 on 15 bits (Figure 2) are all made by a micro-wafer or "chip" of programmable analog head (ANAFEC) 150 using a switching capacitor technology. Figure 2

  shows that the line interface 126 and the hybri-

  of 133 are discrete analog components. The mid-

  ANAFEC 150 key plate transmits emission data

  analog and accepts analog reception data

  ques, through data access arrangements

  nees (DAA) 152 and 154 which respectively serve a

  two-wire line 128 and four-wire line 156.

  The ANAFEC 150 also communicates with a micro-plate

  head or digital chip or chip in CMOS technology.

  or DFE, 158 by serial lines 160, 162, 164, 166, 168 which respectively transport: emission data modulated in sigma-delta (TxD) to ANAFEC 150: reception data modulated in sigma-delta ( RxD) to DFE 158: a 1,152 MHz sampling clock signal to the ANAFEC 150: command bytes (CSD) to the ANAFEC 150 (each in the form of a data byte and a one 3-bit pointing address

  six registers in the ANAFEC): and a data frame

  command data (CDF) which surrounds the 11-bit command word. The ANAFEC 150 also implements the generation

  from the eye chart, the loudspeaker gain control

  their HP and loopback functions for control

modem functions.

  The DFE 158 is advantageously constituted by a programmable chip which performs: (a) the digital base pass filtering function

  of decimation of the receiving CAN 110 on 15 bits (fig.

  re 2) according to the diagram in FIG. 1:

  (b) the sigma-delta nu modulation functions

  of the transmitting DAC 116 (figure 2), (c) the locking loop functions of

  phase with programmable programmable synchronization

  mission and reception and parallel / serial interfaces,

  for communication on lines 160 to 168.

  The DFE 158 also ensures communication

  between two signal processors 170 and 172 in technology

  CMOS (which will be described later), the DFE 158, and the ANAFEC 150, via the serial interface

  represented by lines 180 to 192.

  The DFE 158 also includes a buffer queue (FIFO) which acts as a buffer for digital transmission data and a digital interpolator to perform resampling in order to reduce band noise.

  on the phone line. Samples re-sample

  data are then supplied to the delta- digital modulator

  sigma. The functions of the modulator / demodulator 115 (FIG. 2) are fulfilled by the pair of processors

  signal 170, 172, between which the tasks are shared

  managed as described in US patent application No. 586,681 of March 6, 1984 (Qureshi). Processors 170 and

  172 constitute "maltre" and "slave" respectively.

  Processors 170 and 172 communicate with each other

  be through the 180-192 serial interface of the DFE.

  The host microprocessor 198 communicates with the

  processors 170, 172 and with the input-output processor

  tie (I / O) 176, in CMOS technology, by the data bus

born host 164.

  Data is transferred back and forth between the I / O processor 176 and the DTE

  114 on the line interface 178 to 15 lines.

  The DFE 158 sends the data to the "maltre" and "slave" processors 170 and 172 by a serial line 184 marked "D OUT". The "maltre" and "slave" processors

  send data to the DFE via the separate data line

  rie 186, designated by "D IN". The DFE generates the frame synchronization signals on 180, 182, 190 and 192 to control the data flow on the serial lines 184 and 186 and transmits on 188 a constant clock signal

  at 2.308 MHz "S CLK" uses to synchronize the

  data and command signals passing through 180, 182,

184, 186, 190 and 192.

  Serial line 186 "D IN" transfers data

  14 bit transmission CAN, trans-

  control for the other signal processor, DFE control data (sampling frequency, sample phase, etc.), ANAFEC control data (loopback, reception gain, transmission gain, etc.) .)

  and eye chart data.

  The D OUT 184 serial line carries data

  analog / digital reception on 15 bits, data

  born transferred from the other signal processor and

  DFE status information (sampling phase.

  frequency offset, error states, test).

  Signal processors "maltre" and "slave"

  and 172 are respectively served by memos,

  res vives (RAM) 194 and 196. These memories can be

  discharged from the host processor through

  diary of the host data bus 164.

  The circuits constituting the host processor 198

  have a programmed microprocessor (such as Moto-

  rola 868HC09), living memories, read-only memories

  electrically programmable. erased memories

  electrically cabled. and a network of doors. It is connected to the host data bus 164. The input / output processor 176 and the host processor 198 receive synchronization CLK clock signals 200, 206 and 208 from the transmission modem (marked by Tn) and reception (indicated by Tx). Signal 210 is a constant clock signal at 9.216 MHz for the input / output processor

176 in CMOS technology.

  The host processor 198 controls the DFE by the

  signal line line (RUN) 204 which

* is locked by the chip validation line 202.

  The host processor communicates with the DFE 158 and with the ANAFEC 150 through the processors 170 and 172 via the host data bus 164 and the lines

  data series 184 and 186. The conversion series / paral-

  This is done in signal processors 170 and 172. Figure 4 shows that, because the digital decimation filter of Figure 1 achieves

  high resolution ,. you can equip the receiver filter

  Programmable digital tion 111 of filter programs

  echo suppression 200, or multiple filtering-

  frequency division xing 202, or we can set

  other modes, each of the modes being selected-

  enabled by a mode selection signal. We can then configure the analog bandpass filter 132 to specifically suit the telephone line, but

  as well adapted to any other mode of communication

  information on the telephone line. He was therefore no longer born

  stop providing multiple analog filters 132. The invention is susceptible of many other variations and in particular makes it possible to produce drift filters from the previous one, for example intended for

  third order delta-sigma modulators.

Claims (17)

  1. Digital decimation filter for   receive a stream of digital input samples (xi) at an input sampling frequency and provide a corresponding stream of digital output samples   (yi) at a different output sampling frequency   annuity, characterized in that it comprises means (16) having a set of elements (20) for storing several   digital input samples and a circuit for   derive the samples of the output stream from the   stored digital input samples, said circuit   cooked having means (48.50) to make an output sample available for inclusion in the output stream at any time, so that one can give to   the output sample a selectable phase.   2. Filter according to claim 1, characterized in that the circuit comprises a pair of   integration and restitution circuits (48.50) function   operating in such a way that, when one of the circuits integrates, the most recently generated sample by   the other integration and restitution circuit is   ponible to be included in the output stream.   3. Filter according to claim 1, characterized in that the circuit comprises a filter stage without decimation (16,28,36,38) followed by a stage   integration and restitution, decimation.   4. Filter according to claim 1, 2 or 3, characterized in that the circuit further comprises means (30,32,34) for selecting a decimation ratio between the frequency of input samples   and the frequency of the output samples.   5. Analog / digital converter, compression   nant a delta-sigma modulator to provide a stream, at high frequency, of digital samples of an analog signal, the frequency being appreciably higher than the Nyquist frequency,   characterized in that it further comprises a digital filter   decimation risk for receiving the high bit rate flow and providing a corresponding bit rate of filtered digital output samples at a lower frequency, the decimation ratio between the high frequency and the   low frequency being selectable.   6. Converter according to claim 5, characterized in that the digital decimation filter comprises a finite impulse response filter having   successive storage elements (20) for memorizing   riser digital samples arriving at high frequency, and a cartographic element (28) to convert   a set of signals taken from a single part-   ment of said storage elements (20) in a stream of   values, said cartographic element (28) being confi   shaped so as to have the desired impulse response.   7. Converter according to claim 6, characterized in that the mapping element (28)   does not perform explicit multiplication.   8. Converter according to claim 5, 6 or 7, characterized in that the storage elements (20)   from which the signals are taken are selected   born according to the desired decimation ratio.   9. Converter according to claim 8, characterized in that it comprises a multiplexer (30.34) having inputs connected to several of the storage elements (20), said multiplexer being controlled by a signal (32) corresponding to the desired decimation ratio . 10. Converter according to claim 5, characterized in that the digital decimation filter comprises a circuit intended to generate samples of the output stream from the stored digital input samples, said circuit comprising means (48.50) for make an output sample available   to be included in the output stream during fishing   which will not be limited to a single instant, so that each of the output samples can be provided with a selectable phase.   11. Multi-mode modem, intended to be used   read in association with a channel on which you can   duler a carrier following at least two patterns of mo-   different dulation possible, said channel being of a type which causes an echo of the signal transmitted on the channel of the received signal, said modulation schemes implementing techniques for suppressing the effects of echo, characterized in that it comprises : a reception circuit intended to receive the modulated carrier coming from the channel and to convert it into   a corresponding stream of digital samples, the   receiving bake having an analog / digital converter   meric (110) feeding a programmed digital filter   ble (111) for providing filtering functions   selectable, respectively applicable to two schedules   modulation mas with different echo cancellation, so it is not necessary to provide, upstream of the   analog / digital converter, filter filters   different concept for different modu-   lation. 12. Modem according to claim 11,   characterized in that the analog / digital converter   risk includes a delta-sigma modulator to provide a   high frequency flow of digital samples of the   said carrier at a significantly higher frequency   on the Nyquist frequency and a digital filter with   cimation to receive the high frequency flow and   to provide a corresponding stream of digital samples   filtered output risks, at lower frequency.   13. Modem according to claim 11, characterized in that one of said modulation schemes is echo cancellation or frequency division multiplexing. 14. Modem according to claim 11, characterized in that the programmable digital filter   includes a set of storage elements (20) for memory   moriser several digital input samples from the   modulated carrier and circuits to generate the exchangers   tillons of the converted stream of digital samples from the stored digital input samples,   said circuits comprising means (48.50) for connecting   dre a generated sample available for in-   clusion in the converted stream for periods which are not limited to a single instant, so that the generated sample can be provided with a selectable phase. 15. Modem according to claim 11,   characterized in that said analog / digital converter   merica includes a delta-sigma modulator to generate a high frequency stream of digital samples of an analog signal at a significantly higher frequency   higher than the Nyquist frequency and a digital filter   than decimation intended to receive the stream at high frequency and to provide a corresponding stream of samples   digital outputs filtered at a lower frequency   ble, the decimation ratio between high frequency   and the low frequency being selectable.   16. Decimation digital filtering method making it possible to receive a stream of digital input samples at an input sampling frequency and   to provide a corresponding stream of digital samples   output ques filtered at a sampling frequency different exit age.   characterized in that several samples are stored   digital input and we generate, from the samples   stored digital input logs, samples of   output flow, making an output sample available   available for inclusion in the output stream at any time, so that each output sample   can be supplied with a selectable phase.   17. Analog-to-digital conversion method in which a high frequency stream of digital samples of an analog signal is generated, at a   frequency significantly higher than the frequency of Ny-   quist, by delta-sigma modulation, and we receive this stream at high frequency characterized in that we transform the stream at frequency   raised to a corresponding stream of digital samples   output output filtered at lower frequency, the ratio   decimation port between high frequency and frequency   low quence being selectable.