CA1336342C - Multiple-mode modem with digital filtering - Google Patents

Abstract

A digital decimation filter for receiving a stream of input digital samples at an input sample rate, and for delivering a corresponding stream of output digital samples at a different output sample rate stores a plurality of input digital samples, derives samples of the output stream from the stored input digital samples, and makes an output sample available for inclusion in the output stream at all times, whereby the output sample may be delivered with a selectable phase. In other aspects, an analog-to-digital converter has a sigma-delta modulator for generating a high rate stream of digital samples of an analog signal at a rate substantially higher than the Nyquist rate, and a digital decimation filter for receiving the high rate stream and delivering a corresponding stream of filtered output digital samples at a lower rate, the decimation ratio being selectable; and a multiple-mode modem for use with a channel on which a carrier may be modulated in accordance with at least two different possible modulation schemes (the channel being of the kind that induces echo signals, the modulation schemes comprising techniques for avoiding the effects of the echo signals), receives the modulated carrier from the channel and converts it to a corresponding stream of digital samples, using receive circuitry that has an analog-to-digital converter feeding a programmable digital filter for selectively providing filtering functions applicable respectively to the two different modulation schemes, whereby different receive filters applicable to different modulation schemes need not be provided ahead of the analog-to-digital converter.

Description

Iul~)plQ ~ ~od ~ 3 3 6 3 4 2 Diqital Filterinq Backqround of the Invention This invention relates to digital filters.
It is known to provide a decimating digital low-pass filter at the output of an analog-to-digital (A-to-D) converter to enable the A-to-D converter to achieve increased amplitude resolution by oversampling the analog signal ~i.e., at a multiple of the Nyquist rate)~ In a decimating digital filter, the output sample rate is lower (e.g., 100 times lower) than the input sample rate.
Candy, "Decimation for Sigma Delta Modulation," IEEE
Trans. on Comm., Jan., 1986, shows that for A-to-D converters using second-order sigma-delta modulation, a near optimal frequency response for the decimation filter is H(f) = sin3(~Nf/fs)/sin3(~f/fs) where N is the decimation ratio (between the input sampling rate --fs-- and the output sampling rate).
Huber et al., FIR Lowpass Filter for Signal Decimation ..., ICASSP, 1986, Tokyo, describe a decimation filter that does not require any explicit multiplication and achieves the desired response for use with a sigma-delta modulator by an FIR
filter followed by cascaded accumulators. Decimation is performed by a separate unit that follows the filter.
A-to-D converters are used, for example, in modems to convert the analog line signal to digital. In typical echo cancellation modems, echo cancellation and resampling are both performed in the analog domain and are follow~d by a relatively low-resolution analog-to-digital converter. Modems that must serve other co~unication schemes, e.g., frequency division multiplexing, require alternative receive filters; a multi-mode modem may be provided with multiple analog receive filters that can be program selected.

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~ - 2 - 1336342 Summary of the Invention One general feature of the invention provides a digital decimation filter for receiving a stream of input digital samples at an input sample rate, and for delivering a corresponding stream of output digital samples at a different output sample rate; in the filter, input digital samples are stored; samples of the output stream are derived from the stored input digital samples; and an output sam~le is made available for inclusion in the output stream at all times, whereby the output sample may be pointed with a selectable phase.
Preferred embodiments of the invention include the following features. The filtering is done by a non-decimating filter stage followed by a decimating integrate and dump stage. An output sample is made available at all times by providing a pair of integrate and dump circuits operated so that as one circuit is integrating, the sample most recently generated by the other integrate and dump circuit is available for inclusion in the output stream.
Another general feature of the invention provides an analog-to-digital converter having a sigma-delta modulator for generating a high rate stream of digital samples of an analog signal at a rate substantially higher than the Nyquist rate, and a digital decimation filter for receiving the high rate stream and delivering a corresponding stream of filtered output digital samples at a lower rate, and in which the decimation ratio is selectable.
Preferred e~od_ments of the inventicn include the following features. The digital decimation filter includes an FIR filter having successive storage elements for storing the high rate digital samples, and a mapping element for converting a set of signals tapped from fewer than all of the storage elements into a stream of values, the mapping element being 4~ 1 336342 conflgured to achieve a deslred lmpulse response. The mapplng element performs no expliclt multlpllcatlon. The particular storage elements from which the set of signals are tapped are selected based on the deslred declmatlon ratlo, using a multlplexer having inputs connected to a plurality of the storage elements.
Another general feature of the lnventlon provldes a multlple-mode modem for use wlth a channel on whlch a carrier may be modulated in accordance with at least two different possible modulation schemes, the channel belng of the kind that induces echo slgnals, the modulatlon schemes comprising techniques for avoldlng the effects of the echo slgnals; the modulated carrler ls recelved from the channel and converted to a correspondlng stream of digital samples by recelve circuity that has an analog-to-digital converter feedlng a programmable dlgltal fllter for selectively providing filtering functlons applicable respectively to the two dlfferent echo avoldlng modulation schemes, whereby different recelve fllters appllcable to dlfferent modulatlon schemes need not be provlded ahead of the analog-to-dlgital converter. In preferred embodlments, the modulatlon scheme lncludes echo cancellation, or frequency dlvlslon multlplexlng.
The dlgltal fllter of the lnvention ls slmple, requlres only a small amount of storage, has a selectable declmatlon ratlo and a selectable output phase, does not requlre e~pllclt tap coefflcients to be stored or computed, and does not requlre expllclt multlpllcatlon. An A-to-D converter based on the fllter ~, 3a 60412-1890 can have a high resolution and a variable decimation ratio, while remalning relatlvely low ln cost. Multlple modes may be served b~
a slngle programmable dlgltal fllter.
Accordlng to a broad aspect of the lnvention there is provlded a multiple-mode modem for use wlth a channel on which a carrier may be modulated in accordance wlth at least two different possible communlcation modesl said channel belng of the kind that lnduces echo of the transmltted slgnal ln the recelved signal path, two of sald communicatlon modes each comprlslng a dlfferent technlque for avolding the effects of sald echo, the modem comprising receive circuitry for receiving sald modulated carrier from said channel and convertlng it to a correspondlng stream of dlgital samples, said receive circuitry having an analog-to-digital converter feeding a programmable digital fllter for selectlvely providlng filtering functions appllcable respectively to two different said echo avoidance techniques, sald analog-to-dlgital converter comprislng a sigma-delta modulator for generating a high rate stream of digital samples of an analog slgnal at a rate substantlally higher than the Nyqulst rate, and a dlgital declmatlon fllter for recelvlng sald hlgh rate stream and deliverlng a correspondlng stream of flltered output dlgltal ~
samples at a lower rate, the decimation ratlo of sald hlgher rate to sald lower rate belng selectable, sald dlgital declmation fllter comprlslng a flnlte lmpulse response fllter havlng successlve storage elements for storlng sald hlgh rate digltal samples, and a mapplng element for convertlng a set of slgnals tapped from fewer than all of said storage elements lnto a stream . ~ ~

~ 1 336342 3b 60~12-1890 of values, said mapplng element being configured to achieve a deslred lmpulse response.
According to another broad aspect of the lnventlon there ls provlded a multlple-mode modem for use with a channel on whlch a carrler may be modulated ln accordance with at least two dlfferent possible communlcation modes, said channel being of the kind that induces echo of the transmitted signal in the recelved slgnal path, two of sald communlcatlon modes each comprlsing a different technlque for avoldlng the effects of said echo, the 0 modem comprislng receive circultry for receiving said modulated carrier from said channel and converting it to a corresponding stream of digital samples, said recelve circuitry having an analog-to-digltal converter feedlng a programmable digital filter for selectlvely provldlng fllterlng functlons appllcable respectlvely to two dlfferent sald echo avoidance technl~ues, sald controllable dlgltal fllter lncludlng a set of storage elements for storlng a plurality of lnput dlgltal samples of sald modulated carrier, and clrcultry for derlvlng samples of sald converted stream of dlgital samples from sald stored lnput digltal samples, sald clrcultry including means for making a derived sample avallable for inclusion in said converted stream at all times whereby sald derlved sample may be dellvered wlth a selectable phase, sald clrcuitry comprlslng a palr of lntegrate and dump clrcults operated so that as one clrcult ls lntegratlng, the sample most recently generated by the other lntegrate and dump clrcult is available for lncluslon ln sald stream.
Accordlng to another broad a~pect of the inventlon there ,~ .

~ 1 336342 3c 60412-1890 is provided a multiple-mode modem for use with a channel on which a carrier may be modulated in accordance with at least two dlfferent posslble communication modes, said channel being of the kind that induces echo of the transmitted slgnal in the received signal path, two of said communication modes each comprising a different technique for avoiding the effects of said echo, the modem comprising receive circuitry for receiving said modulated carrier from said channel and convertlng it to a corresponding stream of digital samples, sald recelve clrcuitry havlng an analog-to-digital converter feedlng a programmable digital filter for selectively providing filtering functions applicable respectively to two different sald echo avoidance techniques, said controllable digital filter lncluding a set of storage elements for storing a plurality of input digltal samples of said modulated carrier, and clrcuitry for derivlng samples of sald converted ~tream of dlgltal samples from sald stored lnput dlgltal samples, sald clrcuitry includlng means for maklng a derlved sample avallable for lncluslon ln sald converted stream at all tlmes whereby said derlved sample may be dellvered wlth a selectable phase, sald clrcultry comprislng a non-declmatlng filter stage followed by a decimatlng integrate-and-dump stage.
Other advantages and features wlll become apparent from the followlng descrlptlon of the preferred embodlment, and the clalms.

~. ,=, Description of the Preferred Em~odiment We first briefly describe the drawings.
Drawinqs.
Fig. 1 is a block diagram of a digital decimation filter.
Fig. 2 is a block diagram of a modem.
Fig. 3 is a block diagram of one implementation of portions of the modem of Fig. 2.
Fig. 4 is a block diagram of a portion of a multiple-mode modem.
Structure and Operation Referring to Fig. 1, a digital decimation filter 10 receives a stream of one-bit digital input samples xi, i=o, 1, . . ., at an input sample rate fs on an input line 12, and delivers a corresponding stream of digital output samples Yi, i=0,1,..,, on output line 14 at a selected one of K
different output rates fk, lower than f5 and with a selectable output phase.
The samples xi on input line 12 are shifted into a serial shift register 16 by input clock pulses on line 18.
Shift register 16 has 2N+1 elements 20, where N is the maximum desired decimation ratio (i.e., fs/fmin where fmin is the smallest desired output rate); x0 is the element holding the most recently loaded sample, X_2N holds the oldest sample.
For each clock pulse on line 18, three of the samples in the shift register are applied to the three address input lines 22, 24, 26 of a mapping element 28 (e.g., a looking-up table). The sample applied to address line 22 is always tapped from the x0 element of shift register 16. The sample applied to address line 24 is tapped from 1 of K different elements of the shift register (where the K different elements include element x_N and adjacent elements), via a K:l multiplexer 30 under control of a decimation rate control signal on line 32.

~ - 5 - l 336342 That control signal also governs a second K:l multiplexer 34 to select one of K different samples (tapped from element X_2N
and adjacent elements) to be applied to line 26.
Mapping element 28 maEs each possible combination of the three address bits into a corresponding output value to implement an impulse response function to be described below.
The successive output values of element 28 are delivered at the same rate as input clock 18 to two cascaded integrators 36, 38 each including a summer 40, 42 and a feedback delay element 44, 46 (one clock pulse delay) also clocked by input clock pulses at rate fs from line 18. The output of integrator 38 is fed simultaneously to a parallel pair of integrate and dump circuits 48, 50. Each integrate and dump circuit includes a summer 52, 54 and a feedback delay element 56, 58. The delay elements are clocked by input clock pulses at rate fs (from line 18) and are zeroed respectively by even clear and odd clear pulses delivered (as even control and odd control signals) by output control circuit 60 based on input A/D sample clock pulses on line 64. The even clear and odd clear pulses alternate and both appear at the same rate fS/2Nk, where Nk is the presently selected decimation ratio. The even control and odd control signals ~rom output control circuit 60 also include even hold and odd hold signals which are asserted during even and odd output sample periods.
The outputs of the two integrate and dump circuits are delivered alternately via a 2:1 multiplexer 62 (controlled by an odd/even signal on line 64 appearing at rate fS/2Nk from clock divider 6C) to an output line 14. Because there are two alternating integrate and dump circuits and a multiplexer, a sample is always available and may be used at any time in order to track, e.g., a possibly jittering clock.
Element 28 is designed in such a way that the overall frequency response of filter 10 is nearly optimum for use following a second order sigma delta modulator (not shown in Fig. 1), i.e., H(f) = sin3(~Nkf/fs)/sin3(~f/fs) Filter 10 implements a corresponding impulse response based on the following principles.
First, the two-stage, non-decimation filter comprising the shift register 16, element 28, and two integrators 36, 38, together provide the frequency response required for a first order sigma delta modulator:
H(f) = sin (~Nkf/fs)/sin (~f/f5) The impulse response of this non-decimating portion is h(i) = s(i)*s(i), where * is the convolution operator, and s(i) = 1, for n = 0, 1, 2,..., Nk-l, = 0, otherwise, and where the frequency response of the filter whose impulse response is s(i) is S(f) = sin(~Nkf/fs)/sin(~f/fs).
Then h(i) = f(i)I(i)I(i), (where f(i) = d(i)*s(i)*d(i)*s(i), d(i) = x(i) - x(i-l), and d(i)*I~i) = 1, for i = 1 = 0, otherwise, i.e., d(i) and I~i) are inverse operations).
Thus, h(i) may be implemented by a filter with response f(i) followed by a cascade of two integrator stages. By computation 0 from the above equations, it can be shown that f(i) = 1, for i = 0 -2, for i = Nk 1, for i = 2Nk o, otherwise The impulse response represented by f(i) is implemented by arranging for element 28 to deliver in the ith sampling interval an output (Zi) determined by the equation zi=xi - 2Xi-N + Xi-2N
Following the two-stage non-decimation filter is a decimating integrate and dump fLlter whose frequency response is H(f) = sin (~*Nk*f/fs)/sin (~*f/fs) Implementation of an integrate and dump filter is achieved by clearing an accumulator, and accumulating N input data samples to compute one output sample.
To change the decimation ratio merely requires changing the tap locations using the multiplexers 30, 34, in accordance with the above equations, and changing the divisor in output control circuit 60. For example, for a decimation ratio of 65, use taps 0, 65, and 130. In general, for a decimation ratio of Nk, use taps, 0, Nk, and 2Nk.
Referring to Fig. 2, in one application, digital filter 10 (Fig. 1) is part of a high-resolution (15 bit) A/D
converter 110 in a full duplex, echo cancelling modem 112 operating in accordance with CCITT standard V.32. In modem 112, digital data to be transmitted from a data terminal-equipment (DTE) 114 passes via a modulator/demodulator 115, a 14-bit sigma-delta modulation D/A converter 116, an analog low pass filter (LPF) 120, a transmit gain unit 122, a continuous analog low-pass filter 124, a hybrid 133, and a line interface 126 to a two-wire telephone line 128. The incoming analog receive signal on line 128 also passes through interface 126, is separated by hybrid 133 and sent via a continuous analog low-pass filter 134, a receiver gain unit 130, an analog broad-band band-pass filter (BPF) 132, the 15-bit A/D 110, programmable receive filter (echo cancellation) 111, and modulator/demodulator 115, to DTE 114. Filters 124, 120, 132, 134 are configured for band-shaping appropriate to the . ~ - 8 ~ 1336342 telephone` line 128, but are suitable for any mode of communication (e.g., echo cancellation, or frequency division multiplexing) on line 128, Filtering specific to the communication mode (in this case echo cancellation) is achieved in receive filter 111.
Referring to Fig. 3, in one implementation of the modem of Fig. 2, the analog domain functions of the low-pass filter portion of D/A 116, LPF 120, transmit gain 122, LPF 124, LPF 134, receive gain 130, BPF 132, and the analog sigma-delta modulation function of 15-bit A/D 110 (Fig. 2) are all performed by a programmable analog front-end chip (ANAFEC) 150 using switch capacitor technology. (Note in Fig. 2 that line interface 126 and hybrid 133 are discrete analog components).
ANAFEC 150 sends analog transmit data and accepts analog receive data, via data access arrangements (DAA) 152, 154, which respectively serve two-wire line 128 and four-wire line 156, ANAFEC 150 also communicates with a C~OS digital front-end chip (DFE) 158 via serial lines 160, 162, 164, 166, 168 which respectively carry sigma-delta modulated transmit data (TXD) to ANAFEC 150; sigma delta modulated receive data (RXD) to DFE 158; a 1.152 MHz sample clock to ANAFEC 150;
control bytes (CSD~ to ANAFEC 150 (each in the form of an 8-bit data byte and a 3-bit address pointing to one of six register in ANAFEC); and a control data frame (CDF) that frames the eleven bit control word~ ANAFEC 150 also implements eye pattern generation, speaker gain control, a~d loop backs for modem ch~ck functions.
DFE 158 is a progra~mable chip that performs (a) the decimating digital low-pass filter function of 15 bit receive A/D 110 (Fig. 2), in accordance with the scheme of Fig. l; (b) the digital sigma delta modulator functions of transmit D/A 116 (Fig. 2); as well as (c) transmit and receive programmable timing tracker phase lock loop functions, and parallel-to-~ 1 336342 serial interfacing for communication on lines 160-168. DFE 158 also provides communication between two CMOS signal processors 170, 172 (discussed below), DFE 158, and ANAFEC 150, via the serial interface represented by lines 180-192. DFE 158 also includes a FIFO buffer that buffers digital transmit data, and a digital interpolator to accomplish resampling for purposes of reducing out of band noise on the telephone line. The resampled samples are then delivered to the digital sigma-delta modulator.
The functions of modulator/demodulator 115 (Fig. 2) are performed by a pair of CMOS signal processors 170, 172, which share the task in a manner described in Qureshi, European Patent No. 85301542.8, filed on March 6, 1985 and publicly disclosed on September 11, 1985. Processor 170 serves as a master, processor 172 as a slave. Processors 170, 172 communicate with each other via DFE serial interface 180 through 192.
The host microprocessor 198 communicates with processors 170, 172, and CMOS input\output (I\O) processor 176 via host data bus 164.
Data passes both ways between I/O processor 176 and DFE
114 on a 15 line interface 178.
DFE 158 sends data to master and slave processors 170, 172 via serial line 184 (DOUT). Master and slave processors send data to the DFE via serial data line 186 (DIN). The DFE generates frame sync signals 180, 182, 190, and 192 to control data flow over serial lines 184 and 186 and SCLK 188 which is a constant 2.308 MHz clock used to clock data and control signals 180, 182, 184, 186, 190, and 192.

~ ~r 9a 1 336342 60412-1890 Serial line DIN 186 carriers 14 bit transmit DAC data, pass through data for the other signal processor unit, DFE control data (sample rate, sample phase, etc.), ANAFEC control data (loop backs, receive gain, transmit gain, etc.), and eye pattern data.

.~ . , ~ lo - 1 336342 Serial line DOUT 184 carries 15 bit receive A/D data, pass through data from the other signal processor unit, and DFE
status information (sampling phase, frequency offset, error conditions, test).
Master and slave signal processors 170, 172, are respectively served by RAMS 194, and 196, which may be down loaded from host processor via host data bus 164.
-7 ~ Host processor circuitry 198 includes a programmed ~ microprocessor (Motorola 68HC0 ~, RAM, EPROM, EEPROM, and a gate array and is connected to host data bus 164. I/O
processor 176 and host processor 198 receive transmit and receive modem timing signals 200, 206, and 208. Signal 210 is a constant 9.216 MHz clock for CMOS I/O processor 176.
Host processor 198 controls the DFE through RUN signal line 204 which is latched by chip enable line 202. The host processor communicates with DFE 158 and ANAFEC 150 through CMOS
processors 170 and 172 via host data bus 164 and serial data lines 184 and 186. Serial-to-parallel conversion is implemented in CMOS signal processors 170, 172.
Referring to Fig. 4, because the digital decimation filter of Fig. 1 enables A-to-D 110 to provide high resolution, it is possible for digital programmable receive filter 111 to be provided with programs for echo cancellation filtering 200, or freguency division multiplex filtering 202, or other modes, each of which is selectable by a mode selection signal 204.
Then analog band-pass filter 132 can be configured in a manner specifically suitable for the telephone line, but equally suitable for any mode of telephone line communication. Thus it is unecessary to provide multiple analog filters 132.
Other embodiments of the filter may be derived for use with, e.g., third-order sigma-delta modulators.

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Claims (6)

1. A multiple-mode modem for use with a channel on which a carrier may be modulated in accordance with at least two different possible communication modes, said channel being of the kind that induces echo of the transmitted signal in the received signal path, two of said communication modes each comprising a different technique for avoiding the effects of said echo, the modem comprising receive circuitry for receiving said modulated carrier from said channel and converting it to a corresponding stream of digital samples, said receive circuitry having an analog-to-digital converter feeding a programmable digital filter for selectively providing filtering functions applicable respectively to two different said echo avoidance techniques, said analog-to-digital converter comprising a sigma-delta modulator for generating a high rate stream of digital samples of an analog signal at a rate substantially higher than the Nyquist rate, and a digital decimation filter for receiving said high rate stream and delivering a corresponding stream of filtered output digital samples at a lower rate, the decimation ratio of said higher rate to said lower rate being selectable, said digital decimation filter comprising a finite impulse response filter having successive storage elements for storing said high rate digital samples, and a mapping element for converting a set of signals tapped from fewer than all of said storage elements into a stream of values, said mapping element being configured to achieve a desired impulse response.

2. The modem of claim 1 wherein said mapping element comprises a look-up table.

3. The modem of claim 1, wherein the storage elements from which said set of signals are tapped is selected based on the desired said decimation ratio.

4. The modem of claim 3, further comprising a multiplexer having inputs connected to a plurality of said storage elements, said multiplexer being controlled by a signal corresponding to said desired decimation ratio.

5. A multiple-mode modem for use with a channel on which a carrier may be modulated in accordance with at least two different possible communication modes, said channel being of the kind that induces echo of the transmitted signal in the received signal path, two of said communication modes each comprising a different technique for avoiding the effects of said echo, the modem comprising receive circuitry for receiving said modulated carrier from said channel and converting it to a corresponding stream of digital samples, said receive circuitry having an analog-to-digital converter feeding a programmable digital filter for selectively providing filtering functions applicable respectively to two different said echo avoidance techniques, said controllable digital filter including a set of storage elements for storing a plurality of input digital samples of said modulated carrier, and circuitry for deriving samples of said converted stream of digital samples from said stored input digital samples, said circuitry including means for making a derived sample available for inclusion in said converted stream at all times whereby said derived sample may be delivered with a selectable phase, said circuitry comprising a pair of integrate and dump circuits operated so that as one circuit is integrating, the sample most recently generated by the other integrate and dump circuit is available for inclusion in said stream.

6. A multiple-mode modem for use with a channel on which a carrier may be modulated in accordance with at least two different possible communication modes, said channel being of the kind that induces echo of the transmitted signal in the received signal path, two of said communication modes each comprising a different technique for avoiding the effects of said echo, the modem comprising receive circuitry for receiving said modulated carrier from said channel and converting it to a corresponding stream of digital samples, said receive circuitry having an analog-to-digital converter feeding a programmable digital filter for selectively providing filtering functions applicable respectively to two different said echo avoidance techniques, said controllable digital filter including a set of storage elements for storing a plurality of input digital samples of said modulated carrier, and circuitry for deriving samples of said converted stream of digital samples from said stored input digital samples, said circuitry including means for making a derived sample available for inclusion in said converted stream at all times whereby said derived sample may be delivered with a selectable phase, said circuitry comprising a non-decimating filter stage followed by a decimating integrate-and-dump stage.