FR2615062A1 - Processor for stereoscopic presentation of video images - Google Patents

Abstract

Device whose purpose is to allow comfortable observation of stereoscopic video images which are transmitted or recorded according to the alternate views technique and are presented by means of electro-optical switches, at twice the frequency of reception. This device includes memories 11 to 14 to which are written the two successive complete images, even and odd, each being composed of the two views, left and right. With each integrated memory circuit there is associated a multiplexer which places it successively in communication with the common data bus to be written to, and with one of the two parallel data buses read out both to an even frame memory and to an odd frame memory. These parallel buses communicate with circuits effecting interpolations with the respective ratios 1/2 for the left frames, or 1/4 and 3/4, for the right frames, between the digital data extracted from two memories containing, for each view, left or right, the half-frames received during the cycles of even and odd order.

Description

 The purpose of the processor presented here is to improve the presentation of stereoscopic television images, in the hypotheses where the stereoscopic presentation is obtained by electro-optical light switches, where the television or the monitor is provided with a memory of images, and where to avoid eyestrain of the spectator the complete image is presented to him entirely at the recurrence frequency of 50 or 60 Hz, while the signal is recorded on a video recorder or transmitted on a normal television channel, in which , by the effect of line spacing, the complete image is transmitted at a recurrence frequency of only 25 or 30 Hz.

 It is known that, if the delay between the shooting and the restitution of the image does not have the same value for the respective images of left and right, there appears a defect called spatio-temporal distortion: any object which moves laterally at high angular speed is seen as if it were closer, or more distant, depending on the direction of its displacement and whether the view of the left or right is more delayed, and to any object in vertical movement correspond right and left images shifted in the height direction, which prevents the restitution of the relief.

 As, in the hypothesis indicated above, the frequencies of recurrence of the shooting and the restitution of the image are different, it is not possible to strictly respect the equality of the delays on both sides: a artifice is necessary; the proposed device performs this device.

 It is known that the threshold of human sensitivity to deviations from "proximity" (that is to say, inverses of distances) is lower than the resolution limit of the images. - So the introduction of a gradual transition on the edge of an object, fixed or moving, does not affect the accuracy of the relief rendering, at least on condition that the transition corresponding to this edge is, on average , conforms to the theoretically exact position. The object proposed is to represent an edge by a gradual transition, the average position of which is exact. This device leaves perfect clarity to objects that are not in rapid motion.

The means proposed according to the present invention for making this device is as follows:
The signals received from transmission or recording are first separated, as is usually done, into three parts:
- or the three color components;
- or else two chrominance signals and one of luminance.

 It is the latter case which is chosen for the description of the present invention, although the latter is also applicable in the other case.

These signals are recorded, during each successive cycle corresponding to the transmission of two complete images, alternately on four groups of digital memories, assigned respectively to the following frames:
- left odd frame (left view transmitted by the odd lines of an odd order image) on the memory (11);
- right odd frame (right view transmitted by the even lines of an odd order image) on the memory (12);
- left pair frame (left view transmitted by the odd lines of an even order image) on the memory (13);
- straight even frame (right view transmitted by the even lines of an even order image) on the memory (14).

 This complete cycle lasts 80 milliseconds according to European standards which are used as a hypothesis in the description of the present invention, although the latter is also applicable to the case of the American NTSC standards and to future digital transmission standards D2-XAC. After this cycle, the new coded signals are recorded again in the same memories, the previous content of which is no longer of interest.

 To restore the image, this cycle is first delayed by about five milliseconds, then divided into eight successive parts, each lasting ten milliseconds.

 During each of the cycle parts, each of the three luminance and chrominance signals are respectively read at the same time on two of the memories on which the even and odd frames are respectively recorded. Two successive left fields, or two successive right fields, are read at once. The frames on one side, for example left, are interpolated in the 3/4 and 1/4 ratios, while the frames on the other side are interpolated equally, or transmitted without interpolation, depending on the part of the cycle.

 Interpolation takes place in real time by interpolation devices, and the resulting signal is transmitted to a decoder specific to each type of signal, but which remains the same throughout the cycle.

 Such interpolation devices operate on both the luminance signals and the chrominance signals of each pixel.

They carry out, during each part of the cycle, interpolations between the contents of the memories of even frames and odd frames, according to the ratios indicated in the following table:
Left odd Right odd Left pair Right pair
Nemoire (11) Memory (12) Xémoire (13) Xémoire (14) 1 1/2 1/2 2 1/4 3/4 3 0 1 4 3/4 1/4 5 1/2 1/2 6 3 / 4 1/4 7 1 0 8 1/4 - 3/4
To avoid that the same integrated memory circuit can be simultaneously written and read, the memories (11), (12), (13) and (14) are each divided into several separate integrated circuits, for example three dedicated circuits respectively at the upper, middle and lower parts of the corresponding frame.

 A division of each memory into two, or into four integrated circuits, is also possible according to the invention.

 For example, the memory (11), reserved for the left odd frame, is divided into three integrated memory circuits, typically of one "megabitN each, (15), (16), (17), organized in words of 16 bits; the memory (13) in three integrated circuits (18), (19), (20). Similarly, the memories (12) and (14) are each divided into three integrated circuits (25), (26), (27) and (28), (29), (30).

 Thus for example, during the period identified on the time scale of FIG. I between 13.3 and 20 ms, the signals. received are stored in the circuit (17), but it is the circuits (15) and (18), and partially (16) and (19) which are read. The fact that no memory can be both written and read can also be seen.

Figure 1 shows,
- on line a, the time scale common to the cycles of writing and reading memories, in milliseconds;
- on line b, the succession of frames received;
- On line c, the sequence of distribution of the registration of these frames on the memories (11) to (14);
- on line d, the sequence for distributing the writing of memories (15) to (20) and (25) to (30);
- on line e, parts 1 to 8 of the memory read cycle;
- on line f, the respective shares of the frames read in the memories (11) to (14) in the interpolation, for each part of the reading cycle;
- on line g, the sequence of integrated memory circuits read during each part of the read cycle.

- on line h, the signal C1 for controlling the interpolators
- on line i, the C2 signal for controlling the interpolators
- on line j, the signal C3 for controlling the interpolators
X1gure 2 represents all of the circuits according to the invention. There are detailed memories in twelve integrated circuits (15), (16), (17), (18), (19), (20), (25), (26), (27), (28), (29), (30) where the digital signals of the successive frames are temporarily retained. In this figure are also mentioned the video decoder (10) which extracts after detection the luminance and chrominance signals as well as the line synchronization signals and weft; the coders (21), (22), (23) which each transform the luminance or chrominance signals into digital; finally the decoders (31), (32), (33), which finally transform these digital signals into analog control signals for the intensity of the beams of the cathode ray tube (34) of the television set.

 The elements mentioned above will form part of the digital televisions which will soon supplant the current analog televisions: they are not part of the invention.

 The rest is all of the means (24) necessary for the management of the memories and for the interpolation of the digital signals, means which constitute the invention, and which are represented in this figure in a frame in dotted lines.

 The processor includes a central controller (39) which will be described later in more detail.

 The processor (24) also includes circuits which are identical to each other, in a number equal to that of the integrated memory circuits, called "multiplexers" and designated in the figure by. same reference (35).

Each memory circuit communicates with the other processor circuits (24) only via a multiplexer (35). Each multiplexer (35) communicates with the other circuit elements by sets of conductors commonly called "buses": the control bus (40), the data bus to be written (38), and the two read data buses (36 ) and (37).

 Figure 3 shows in more detail the diagram of the central controller (39). We find there the video decoder (10) and its encoders (21), (22), (23), as well as the decoders (31), (32), (33) and the cathode ray tube (34) and some of the memories and communication buses.

 All these buses communicate with the central controller (39), with the exception of the data bus to be entered (38), in which the results of the three digital encodings are directly collected by the encoders (21), (22), (23 ). The two read data buses (36) and (37) terminate at the input terminals of the three interpolators (43), (44), (45). The output terminals of the interpolators are connected to the input terminals of the decoders (31), (32), (33).

 The other important element of the central controller (39) is the set (41) of the synchronization signal counters. The assembly includes a counter (46) for line synchronization signals, a counter (47) for frame synchronization signals, and a generator (48) for sampling orders.

 Such a generator will exist anyway in digital televisions, it has no particular originality. The other counters are produced by known methods. The assembly (41) transmits in particular to the control bus (40) periodic signals indicating the changes of memories to be recorded, at times multiple of 20 milliseconds according to the time diagram in FIG. 1, and the instructions for reading the memories, also according to this diagram.

This set (41) also transmits to the interpolators (43), <44), (45) signals at the instants represented in milliseconds, during the cycle of 80 milliseconds, by the respective values:
- 10 + multiples of 40, change of state of the signal called C1;
- multiples of 20, change of state of the so-called C2 signal;
- 5 + multiples of 10, change of signal state called C3.

 These signals are shown in the diagram in Figure 1.

 The signal C3 is also directed to the electro-optical switches (42) by which each of the spectator's eyes sees only the views from the corresponding side. These switches are made by any known method: liquid crystals on the screen or in glasses, or glasses with "P.L, Z.T." for example.

 Figure 4 shows in more detail how the multiplexers are inserted between their integrated memory circuit and the general processor circuits (24). The multiplexer (35) shown, corresponding to the integrated memory circuit (18) chosen by way of example, is connected to the read bus (37) alone, while the other multiplexer corresponding to the same parity image part opposite is connected to the read bus (36). The data of the two integrated memory circuits (15) and (18), the only one shown here, are therefore read simultaneously.

 This multiplexer communicates with its associated memory by a data bus (55), an address bus (56), and conductors (53) and (54) carrying the read and write order signals in good time. of memory. The multiplexer communicates, on the other side, with the data bus to be written (38) by the input terminals (58) and with the read data bus (37) by the output terminals (57). It also receives the synchronization signals from the control bus (40). The input terminals (50) are permanently connected, in a different manner for each of the multiplexers (35), each to one or the other of two conductors (51) and (52) carrying the two voltages respectively positive and negative supply.

The multiplexer (35) is a simple logic circuit defined for the following functions:
- calculate, as a function of the signals transmitted by the control bus (40) and of the identification of the multiplexer by the terminals (50), at what moments its associated memory is in write, read or passive;
- calculate, at each moment, the address of the word to be entered or read in its associated memory and indicate this address by the bus (56);
- connecting, at the appropriate times, the data bus (55) of the memory with one of the buses (37) or (38);
- give the appropriate reading or writing orders on the. conductors (53) or (54).

 The internal structure of the multiplexer is fixed according to the functions set out above and has no other particular originality.

 FIG. 5 shows in more detail an embodiment of one of the interpolators, in this case and by way of example the interpolator (43).

 The three interpolators are not strictly identical, since the interpolator of the luminance signals operates on eight-bit words and each of the interpolators of the chrominance signals operates on four-bit words. However, all of them can be produced according to the diagram in FIG. 5.

 The interpolator shown here has two adders (61) and (62), with four or eight bits depending on the type of signal considered, but in all cases the least significant bit of the total is not retained.

The adder (61) receives as operands the data from the two read data buses (36) and (37), and presents its result on an intermediate bus (63). It calculates the average of the data of the two buses (36) and (37). The adder (62) receives as operands the data from an intermediate bus (64) and the result of the first addition which is on the intermediate bus (63). The intermediate bus (64) receives, according to the state of the signal C1, the content of the read data bus (36) or (37), selected by a switch (68) actuated by the signal C1.

 Another switch (69), actuated by the signal C2, addresses the content of one of the two intermediate buses (63) or (64) on the intermediate bus (66), according to the state of this signal C2. Another switch (70), actuated by the signal C3, addresses the content of one of the intermediate buses (66) on the output bus (65) of the interpolator, to the digital-analog converter (21). (67). This intermediate bus (67) is the one which contains the result of the adder (62), which receives on its inputs the operands contained in the intermediate buses (63) and (64>.

 Thus for example, during the period extending between 15 and 20 ms on the time scale of FIG. 1, the signal C1 sends the content of the bus (36) on the bus (64), the signal C2 sends on the bus (66) the result of the first addition found on the bus (61), the signal C3 sends to the output bus (65) the result of the second addition found on the bus (67). At this time, the content of the bus (66) is not used. The output bus then finds a value equal to the sum of three quarters of the content of the bus (36) and a quarter of the content of the bus (37).

 Analogous reasoning shows that at any period of the cycle this diagram gives as a result a transmission to the digital-analog converters in accordance with the diagram in FIG. 1.

 The circuit diagrams may be the subject of variants preserving the spirit of the invention, in particular when circuits with a higher degree of integration are industrially available, comprising in a single integrated circuit all the functions of the processor (24). and memories (11), (12), (13) and (14).

The multiplexers (35) will then have disappeared as separate integrated circuits, but they will be replaced by equivalent circuit elements.

 Similarly, if dual data bus memories appear, one for the data to be written and the other for the read data, possibly with separate address buses for the write and read functions, the multiplexers ( 35) can be partially replaced by circuit elements internal to the memories, and performing the same functions.

 Other diagrams can be chosen for the interpolators, consisting for example of replacing each of them by an interpolator with fixed ratios 1/4 and 3/4, and an interpolator with fixed ratio 1/2, and otherwise arranging the switches .

 The invention is also compatible with so-called "CCD" analog memories; in this case, or else analog-digital converters are inserted between the buses (36) and (37), on the one hand, and on the other hand the input of the interpolators (43) ,. (44), (45), or else the interpolators are produced in analog version according to the same diagram in FIG. 5, and in this case the converters (31), (32) and (33) are not useful.

 Between each of the interpolators and the associated analog-to-digital converter, temporary memory devices for the signals can be inserted, using flip-flops or capacitors, as well as filtering, sampling devices, etc.

Claims (6)

1 Device for improving relief television images, the object of which is to eliminate a "spatio-temporal distortion" by which to any moving object corresponds an undesirable shift in the relative positions of its left and right images, this device being used in the following hypotheses ::  - the signals representing the images come from a transmission on a normal television broadcasting channel or from a normal video recording;  - the respective views on the left and on the right come from the frames of even and odd order respectively received from the transmission or from the recording;  - These views of left and right are presented to each of the spectator's eyes by means of electro-optical switches operating at double frequency, that is to say having two frames for the duration of the reception of only one;  this device being characterized in that it comprises four memory subsets (11), (12), (13) and (14) in which two complete images are recorded in succession, each of which is composed of the left and right views received successively. 2 Device according to claim 1, characterized in that it comprises two sets (36) and (37) of conductors by which the data read simultaneously are routed in two of the memory subsets (11) and (13), or (12) and (14), these data corresponding to the same point of view on the same side of two images received successively from the transmission or from the recording. 3 Device according to claims 1 and 2, characterized in that it comprises means called "interpolators" (43), (44), and (45) by which the digital values of the data, routed simultaneously by the sets of conductors ( 36) and (37), are interpolated, depending on the moment in the memory reading cycle (11) to (14), in the ratios 1/4 and 3/4 for views from one side, and interpolated equally or not interpolated for views on the other side.  4 Device according to claims 1, 2 and 3, characterized in that it comprises a counter (46) of line synchronization signals, by which the reading cycle of the memories (11) to (14) is delayed by a constant time by the writing cycle of the same memories, the value of this delay, counted from the start of the writing of the data in one of the memories (11) to (14), being between two and eight thousandths of a second. 5 Device according to claims 1, 2 and 3, characterized in that it comprises, at the interface between on the one hand each of the integrated circuits constituting the memory subsets (11) to (14) and on the other hand the sets of conductors (36) and (37) by which the data read in the memories (11) to (14) and (38) are routed by which the data written in these memories are routed, so-called "multiplexer" integrated circuits ( 35) identical to each other and in equal number to the integrated circuits constituting the memories (11) to (14), these multiplexers (35) each comprising a set (50) of input terminals, connected differently for each of these circuits to the positive and negative supply conductors of these integrated circuits. 6 Device according to claims 1, 2 and 3, caractrjsb in that each of the interpolators (43), (44) and (45) comprises two adders (61) and (62) and three switches (68), (69) and (70), arranged so that the output of the adder (61) communicates with the input of the adder (62), and that the chain connecting the sets of conductors (36) and (37) to the output of the interpolator via the two adders (61) and (62), also passes through one of the switches, the operation of which is synchronous with the control of the electro-optical switches (42).