FR2623680A1 - Processor for stereoscopic presentation of video images - Google Patents

Abstract

Device for the viewing of stereoscopic video images transmitted or recorded by the alternate views technique. This device, which calls upon electro-optical switches at twice the frequency of reception, includes digital memories whose capacity allows temporary recording of three successive frames, two of which correspond to the views from one side and one to the views from the other side. The memory sub-units 11 and 13 dedicated to the views from the first side simultaneously communicate the data read to two buses 36 and 37. These data are, during two of the phases of an eight-frame presentation cycle, interpolated in real time, pixel by pixel, by three interpolators 43, 44, 45 whilst the data communicated to the bus 36 by the memory sub-unit 12 are repeated twice in succession. This device allows comfortable viewing, free from spatio-temporal distortions, of stereoscopic video images.

Description

The object of the processor of the present invention is to improve the presentation of stereoscopic television images, according to the alternating left and right image method, where the stereoscopic presentation is obtained by means of electro-optical light switches. . In this process, the television is provided with an image memory. To avoid eye strain on the viewer,
The complete image is presented to it at the recurrence frequency of 50 or 60 Hz, while the signal is recorded on a video recorder or transmitted on a normal television channel, at half the frequency. In fact, because of the leading, the complete image is transmitted there at a recurrence frequency of only 25 or 30 Hz.

 In this case, it is essential that the delay, between the shooting and the restitution of the image, have the same value for the respective images of left and right. Otherwise there would appear a defect called spatio-temporal distortion: any object which moves laterally at high angular speed would be seen as if it were closer, or more distant, depending on the direction of its movement and whether the view from the left or from right is more delayed; to any object in vertical movement would correspond right and left images shifted in the direction of the height, which would prevent the comfortable restitution of the relief.

 As, in the hypothesis indicated above, the frequencies of recurrence of the shooting and the restitution of the image are different, it is not possible to strictly respect the obligation of equality of delays of the two sides. It is the object of the present invention to remedy this drawback.

 A method to remedy this drawback has already been proposed in French patent application no. 87 06499 filed on May 7, 198 ?.

This application described a processor which comprises memories whose capacity corresponds to four complete frames. The present method uses a digital memory of more limited capacity.

 In its foundation, the invention relates to a processor, which uses circuits performing for the views of one of the sides, right or left, interpolations between the successive views of the same side, and which alternately presents, for this side, unaltered frames and interpolated frames, while the views on the other side are repeated twice in succession without alteration.

The invention will be better understood with the aid of the description below, based on the appended figures, where:
FIG. 1 represents, in schematic form, the essential elements of the circuit according to the invention.

 FIG. 2 shows, in the form of a diagram, which memories are respectively written and read during a long cycle.

 Figure 3 shows in schematic form, with more detail, the organization of the circuit according to the invention.

 Figure 4 shows, in schematic form, one of the interpolator circuits included in the invention.

 Figure 5 shows, in schematic form, the essential elements of a synchronization signal generator circuit included in the invention.

 FIG. 6 shows, in diagram form, the memories respectively written and read, and said synchronization signals during said long cycle, according to two modes of operation.

 FIG. 7 represents, in schematic form, the main elements of a so-called multiplexer circuit included in the invention.

 FIG. 8 shows, in the form of a diagram, the succession of the data respectively written and read from the memories, according to a so-called short cycle.

 FIG. 1 represents, in schematic form, the essential elements of the circuit according to the invention.

The signals received from transmission or recording are first separated, as is usually done, into three parts:
- or the three color components;
- or else two chrominance signals and one of luminance.

 It is the latter case which is chosen for the description of the present invention, although the latter is also applicable in the other case.

These signals are recorded, during each successive cycle corresponding to the transmission of two complete images, and known as long cycle ", alternately on three subsets of digital memories, assigned respectively to the following frames:
- left odd frame (left view transmitted by the odd lines of an odd order image> on the tell memory subset);
- right odd frame (right view transmitted by the even lines of an odd order image) on the memory subset (12);
- left pair frame (left view transmitted by the odd lines of an even order image) on the memory subset (13);
- straight even frame (right view transmitted by the even lines of an even order image) on the memory subset (12>.

This long cycle lasts 80 milliseconds according to European standards which are used as a hypothesis in the description of the present invention, although the latter is also applicable to the case of the American NTSC standards and to future digital transmission standards D2.
MAC. After this cycle, the signals are recorded again in the same memories, the previous content of which is no longer of interest.

 To restore the image, this cycle is divided into eight successive parts, each lasting ten milliseconds.

 During each of the cycle parts, each of the three luminance and chrominance signals is read, either from the memory subset (12) or from both the memory subset (11) and (13) on which are recorded even and odd frame data respectively.

 The data read are routed simultaneously by two sets of conductors or "buses" (36), which receives the data from the memory subsets (11) and (12), and (37), which receives the data from the memory subset. (13) only.

 Two successive left (or right) frames are read at once.

The frames on one side, for example left, are alternately interpolated equally and transmitted without interpolation, while the frames on the other side are transmitted without interpolation.

 The interpolation takes place in real time by three interpolation devices C43), which operates on the luminance signal, and (44) and (45), at the same time on the chrominance signals of each pixel.

The signals resulting from the interpolators are transmitted to a decoder which reproduces the analog control signals of the cathode-ray tube.

 FIG. 2 shows, in the form of a diagram, which memories are respectively written and read during a long cycle.

 Line a of this figure 2 shows the time scale during this 80 millisecond long cycle.

Line b shows on which memory subset each successive frame is saved
Line c shows which memory subsets are transmitted or interpolated during each phase of the cycle.

 Figure 3 shows in schematic form, with more detail, the organization of the circuit according to the invention.

 There are detailed memories in twelve integrated circuits six of a megabit (71), (72), (73), (74), (75), (76), which together constitute the memory subsets (11 ) and (12), and six of five hundred kilobits (81), (82), (83), (84), (85), (86), which constitute the subset (13).

 Thus the sub-assembly (11) consists of a part of the memory elements of each of the integrated circuits or modules (71), (72), (73), (74), (75) and (76), and the sub-assembly (12) consists of the other part of the memory elements of each of these same modules.

 The distribution of each integrated circuit between the two subsets (11) and (12) can be defined in various ways, as here for example by the most significant bit of the address, which corresponds, according to the most structure current of current memory integrated circuits, to two distinct regions on integrated circuits.

 The device also includes circuits which are identical to each other, in a number equal to that of the integrated memory circuits, called "multiplexers" and designated in the figure by the same reference (77).

Each memory circuit communicates with the central logic unit (39) only via a multiplexer (77) and by sets of conductors or "buses": the control bus (40), the data bus to write (38), and the two data buses read (36) and (37).

 Each of the integrated circuits or memory modules is connected to the data bus (38) to be written, coming from the encoders (21), (22), (23), each receiving a luminance or chrominance component of the video signal (49) , and to one of the data buses (36) and (37) read.

 The central unit (39) comprises, in addition to various synchronization generators, the three interpolators (43), (44), (45) which define the signals which the decoders (31), (32), (33) transform into commands analog of the beams of the cathode ray tube (34).

 FIG. 4 represents, in schematic form, one of the interpolator circuits included in the invention, in this case and by way of example the interpolator (43).

 This interpolator performs this interpolation equally between the signals received on the buses (36) and (37), or, if the switch ((69) is in the high position, it transmits without interpolation one or the other of the signals of the bus (36) and (3?) depending on the position of the switch (68). It thus comprises, in addition to these two switches (68) and (69) actuated respectively by the signals C1 and C2, an adder (61).

 The switch (69) introduced to the converter (33), via its output bus (65), or the interpolation result found on the intermediate bus (63), that is to say the half-sum of the data read from the bus (36) and (37), or the data selected by the switch (68) from that of the buses (36) or (37) and which is located at the output of this switch (68) on the intermediate bus (64) .

 The three interpolators are not strictly identical, since the interpolator of the luminance signals operates on eight-bit words and each of the interpolators of the chrominance signals operates on four-bit words. However, all of them can be made according to the diagram in FIG. 4.

 FIG. 5 represents, in schematic form, the essential elements of a circuit generating synchronization signals included in the invention.

The control signals C1 and C2 of the interpolator are established as simple logical combinations of signals of respective periods 10, 20, 40 and 80 milliseconds, by a generator (95) which receives as inputs synchronization signals (98) start of cycle and (99) start of frame. This generator also establishes the signal
C3 for controlling the electro-optical device (42), produced by known techniques, for separating the views from the left and from the right.

 The spectator may not want to see in relief the program he receives in relief. To this end, the generator (95) is connected to a command or a remote control, symbolically represented by a switch (96), accessible to the viewer, by which the signals C1 and C2 can be modified.

 FIG. 6 shows, in diagram form, the memories respectively written and read, and said synchronization signals during said long cycle, according to two modes of operation. It shows, on lines a and b as in Figure 2, the time scale and what memory is recorded during each phase of the cycle; on lines dl, el, fl, examples of signals C1, C2, oe corresponding to the normal case of observation in relief; on the line gl, the frames presented directly or interpolated, during each phase of the cycle.

 The control signals C1 and C2 can be maintained in the case where the program received is without relief: the images presented are then partially smoothed, more pleasant. Other diagrams of these signals are also possible.

 The lines d2 and e2 represent the signals C1 and C2 modified in the case where the spectator does not want to see in relief, and the line g2 shows, the frames then presented during each phase of the cycle.

 In FIGS. 2 and 6, the much shorter duration of the vertical scanning return has not been taken into account.

 Ligure 7 shows, in schematic form, the main elements of a so-called multiplexer circuit included in the invention.

The multiplexer (77) is a simple logic circuit defined for the following functions:
- calculating, as a function of the synchronization signals and of the identification of the multiplexer by the terminals (50), at which times its associated memory is in write, read or passive;
- calculate, at each moment, the address of the word to write or read in its associated memory and indicate this address by the bus (56);
- connecting, at the appropriate times, the data bus (55) of the memory with one of the data buses 9 to write or read;
- give the opportune times the reading or writing orders to the associated memory.

 FIG. 7 thus schematically shows, in one of the multiplexers (77) connected to one of the memories (71) to (76), the elements necessary for separately counting the addresses in writing and in reading, and for communicating the data read with the bus (36) when this bus can route them.

 This multiplexer communicates with its associated memory by a data bus (55), an address bus (56), and conductors carrying the read and write order signals from the memory in good time.

The multiplexer communicates, on the other side, with the data bus to be entered and with the read data bus (36). The input terminals (50) are permanently connected, differently for each of the multiplexers (77), each to one or the other of the two positive and negative supply voltages.

 Thus multiplexers, manufactured as identical circuits, can manage memories whose active periods are different.

 The multiplexer (77) comprises a timer register (79) with 16-bit words processed in parallel, which temporarily stores the data before transmitting it on the bus (36).

 The multiplexer (77) also has two counters: (88) for. the addresses in registration, and (89) for the addresses in reading. It also includes a switching circuit (90).

At suitable times, this circuit (90) switches the address bus (56) respectively from one to the other of the values indicated by the counters (88) and (89). These moments are those when the memory changes from the registration mode to the reading mode and vice versa, according to a cycle during six times the period of the data bus to be registered, as will be specified below.
The register (79) comprises, in the described embodiment, two outputs (91) and (92), switched alternately, and a permanent input, selected from the six inputs (101), (102), (103>, (104), (105), (106), by means of a simple logic circuit <93) as a function of the signals permanently received on the identification terminals (50) of the multiplexer (77).

 A switching circuit (94> alternately connects the data of the outputs (91) and (92) of the register (79), to the bus (36) at each instant when it is a data transmitted by this multiplexer which is transmitted.

 A shift register comprising two entries, receiving in turn the data read from memory, would be equivalent.

 The multiplexer (77) also includes simple logic circuits, not described, the effect of which is to connect the data bus (55) of the associated memory, depending on the period in the cycle, either to the data bus to be written, or at the input of the logic circuit (93).

 The same description can also apply to multiplexers connected on the one hand to the memory sub-assembly (13) and on the other hand to the read data bus (37).

 Variants with six switchable register outputs (79) instead of inputs (101) å (106), or with two inputs instead of outputs (91) and (92), would be equivalent.

 Other variants with a delay in storing the data received in memory would also be equivalent.

 It is because of this distribution of each of the memory subsets into several memory modules, each of these modules being in writing or reading regime at different periods, that each of these memory subsets ( 11), <11>, (12X, (13), can, during certain phases of the cycle, be both in writing and reading mode. In fact, the memory concerned is then successively written and read, at a rate as high as its access time allows.

 FIG. 8 shows, in the form of a diagram, the succession of the data respectively written and read from the memories, according to a so-called short cycle.

 This figure shows in particular the times suitable for switching the data buses of the memories and that of the address buses between the counters (88) and (89) by the switch (90).

There is, with a very different time scale, defining this short cycle, of a duration equal to six times the sampling time interval of the video signal received, that is to say approximately 400 to 500 nanoseconds, a time diagram. representing, on lines b, c, d, e, f, g, the writing regimes, noted E, or reading regimes, noted L, on the memories constituting the subsets (11) and (12), according to the time scale of line a,
This figure also shows the flow of data on buses (36) or (37), on line h, and (38), on line j. Each data is numbered, the data read from L1, the data to be entered from E101. The counts of the data and their addresses are independent of each other. The serial numbers of the data recorded and read from the memories are also indicated on lines b, c, d, e, f, g of the figure 8.

 During this short cycle, each of the memory modules or integrated circuits undergoes two reading phases and a writing phase.

 Data writing, like reading, is carried out on each memory module in the order of reception on the bus (38). In the hypothesis represented in FIG. 8, the data received from the bus (38) and shown on line j, are recorded without delay.

 On the other hand, the data read, as shown on line h, are kept for a certain time, indicated on line i, before being put into communication with the bus (36).

 The figures of line i are indicated in units equal to the transmission period (approximately 35 to 40 nanoseconds) of the data read on the buses (36) and (37).

 This figure clearly shows that the time available to write or read each data in memory is equal to four times the period of transmission of a word on the bus (36) of read data, that is to say approximately 150 nanoseconds.

 The exact times of writing and reading in this cycle, and of keeping data in the timer register, may be slightly different from what is shown in FIG. 8, depending on the exact characteristics of the integrated memory circuits used.

 The cycle of FIG. 8 is not strictly permanent, because it is interrupted during the line scan returns of the received signal, to allow the refreshment of the memories in the case where they are dynamic memories, and during the return until the synchronization signal returns.

 The central logic unit (39) further comprises elements for triggering the sampling of the video signal, counting the sampling lines and periods and transmitting various other synchronization signals. These elements are not original, and for this reason they are not described.

 The above presentation of the invention implements existing memory integrated circuits. The diagrams can be the subject of variants preserving the spirit of the invention, in particular when circuits with a higher degree of integration will be available, comprising in a single integrated circuit all the functions of the logic unit (39) , multiplexers (77) and memories (11), <12> (12) and (13), or dual address or data bus memories, one for registration and the other for reading.

 Between each of the interpolators and the associated analog-to-digital converter, devices for temporary storage of signals, filtering, sampling, etc. can be inserted.

Furthermore, the sequences of signals C1 and C2 shown in FIG. 6 are given by way of example. Indeed, other sequences are equivalent, because, by the structure of the interpolators, if
C2 is zero, the value of C1 is indifferent.

 Finally, another variant, comprising in each of the multiplexers (71), programmable read-only memory elements, produced and used according to known techniques, also makes it possible to differentiate the multiplexers (77) although they are manufactured as identical elements, so that each one defines for its associated memory different periods of writing and reading.

 The interpolators could be replaced by circuits otherwise performing the same function consisting in creating, from two successive views, a view perceived by the spectator as if it had been taken at an intermediate instant.

 The processor according to the invention may be included in the television, or constitute additional equipment, connected to the latter and to the video recorder by connectors comparable to the NPeritel socket ".

Claims (8)

1 Stereoscopic video image processor,  used in the following hypotheses:  - the signals representing the images come from a transmission on a normal television broadcasting channel or from a normal video recording;  - the respective views on each side, on the left and on the right come from the frames of even and odd order respectively received from the transmission or from the recording;  - these views of left and right are presented to each of the spectator's eyes by means of electro-optical switches operating at double frequency, that is to say having two frames for the duration of the reception of a single  the object of which is to eliminate a "spatiotemporal distortion" by which, because of the above conditions, to any object in lateral movement corresponds an undesirable shift of the relative positions of its left and right images  characterized in that it comprises three subsets (11), (12), (13) of digital memories, the capacity of which makes it possible to record in all three successive frames, two of which (11) and (13) correspond to views from one side and the other (12) to a view from the other side. 2 Device according to claim 1, characterized in that it comprises two sets of conductors or buses (36), through which the data read in the memory subsets (11) or (12) are routed, and (37> , through which the data read at the same time are routed in the memory subset (13). 3 Device according to claim 1, carecfise in that it comprises means (43>, (44), (45), by which the data read from the memory subsets (11) and (13), routed simultaneously on buses (36) and (37), can be interpolated in real time, and each of these interpolators (43), (44) and (45) includes an adder (61) which does not keep the most significant bit weak and two switches (68) and (69) <69> whose object is respectively to select the data of one of the buses (36) and (37), and to connect to the output, that is to say the data chosen by the first switch, the data resulting from the addition. 4 - Device according to claim 1, c2taa7fsrfsb in that each of the memory subsets (11) and (12) consists of only part of the integrated circuits or memory modules (it) to (76), each of these memory modules being able to record, for half of the addresses, data of the left views corresponding to the subset (11), and for the other half of the addresses, data of the right views corresponding to the subset (12), and that the modules (81) to (86) constitute the sub-assembly (13). 5 Device according to claim 4, caractErlsF in that it comprises, on the interface between on the one hand each of the integrated circuits or modules (71) å (76) or (81) to (86) constituting the frame memories, and on the other hand, the sets of conductors or buses (36) or (37) by which the data read in these memories are routed, and (38) by which the data to be written in these memories are routed, multiplexers (77), made as identical to each other and differentiated by input terminals (50) each connected to a positive or negative supply blade. 6 Device according to claim 4, ceractérisé in that it comprises, in interface between on the one hand each of the memory modules, and on the other hand the buses (36) or (37) by which the data read in these memories, and (38) of data to be written, multiplexers (77), produced as identical to each other and differentiated by programmable read-only memory elements. 7 Device according to claim 4, characterized in that each of the multiplexers (77) comprises two address counters: (88), for the addresses in registration, and (89) for the addresses in reading, and a switching circuit ( 90) which, at suitable times, switches the address bus (56) of its associated memory respectively from one to the other of the addresses of the counters (88) and (89>. 8 Device according to claim 7, curzssbErtsf in that each of the multiplexers (77) comprises means for retaining the data read in memory, before communicating it to the bus (36) or (37), for a variable number of transmission periods on this bus, and among these means a delay register (79) comprising several inputs or several switchable outputs.