EP0329717A1

EP0329717A1 - Processor for stereoscopic presentation of video images

Info

Publication number: EP0329717A1
Application number: EP88904235A
Authority: EP
Inventors: Olivier Cahen
Original assignee: SIGRID
Current assignee: SIGRID
Priority date: 1987-05-07
Filing date: 1988-05-04
Publication date: 1989-08-30
Also published as: WO1988009103A1

Abstract

Dispositif dont l'objet est de permettre une observation confortable, exempte de distorsions spatio-temporelles, d'images vidéo stéréoscopiques, transmises ou enregistrées selon la technique des vues alternées, et présentées au moyen de commutateurs électro-optiques, à la fréquence double de celle des signaux reçus. Ce dispositif comporte quatre sous-ensembles de mémoire (11, 12, 13, et 14), dans chacun desquels est respectivement enregistrée chaque trame reçue successivement. Il comporte également deux ensembles de conducteurs (36 et 37) par lesquels les points correspondants de deux trames successives du même côté sont lus simultanément, et des moyens (9) pour interpoler ces données en temps réel, selon un cycle traitant de façon différente les vues de gauche et les vues de droite. L'invention est applicable aux téléviseurs.Device the object of which is to allow comfortable observation, free of space-time distortions, of stereoscopic video images, transmitted or recorded according to the technique of alternating views, and presented by means of electro-optical switches, at a frequency double of that of the signals received. This device comprises four memory subsets (11, 12, 13, and 14), in each of which is recorded each frame received successively. It also comprises two sets of conductors (36 and 37) by which the corresponding points of two successive frames on the same side are read simultaneously, and means (9) for interpolating this data in real time, according to a cycle treating differently the left views and right views. The invention is applicable to televisions.

Description

PROCESSOR FOR STEREOSCOPIC PRESENTATION OF VIDEO IMAGES The subject of the invention is a device to be incorporated or connected to a television receiver to enable it to present raised images in good conditions. The invention involves the following hypotheses: - the stereoscopic presentation is obtained by electro-optical light switches, for example with liquid crystals;

- the television set or the monitor is equipped with an image memory;

- to avoid eyestrain of the spectator, the image is presented to him entirely at the recurrence frequency of 50 or 60 Hz, while the signal is recorded on a video recorder or transmitted on a television channel, in which, by Interlining effect, the complete image is transmitted to it at a recurrence frequency of only 25 or 30 Hz.

It is known that, if the delay between the taking of images and the restitution of the image does not have the same value for the respective images of left and right, there appears a defect called space-time distortion: any object which moves laterally at high angular speed is seen as if it were closer, or more distant, depending on the direction of its movement and whether the view of the left or right is more delayed, and to any object in vertical movement correspond images right and left shifted in the direction of the height, which prevents the restitution of the relief.

This harmful effect appears spontaneously, due to the doubling of the frequency of presentation of the images by repetition of the frames, regardless of the order in which the frames are repeated. The processor, object of the invention, remedies this defect by dynamic processing, in real time, and not degrading the image.

The effect of this processing is to present frames each calculated as an intermediary between two successive frames on the corresponding side, previously stored in memory as soon as they are received, then read simultaneously in these memories.

The left and right frames are processed according to different algorithms. The processing leaves the fixed position images unchanged, and replaces the edges of moving objects with progressive transitions, such that each object is seen at its correct distance. The treatment therefore only results, for the spectator, in a fleeting effect constituted by the loss of sharpness of the edges of the moving objects. On the other hand, it compensates for the significant defects in the appreciation of the distance of objects in rapid lateral movement. The principle of compensating for space-time distortions, which is the subject of the present invention, consists in presenting frames interpolated between two successively received frames I (x, y, t) and I (x, y, t + T), where T represents the time interval which separates two frames on the same side successively received, ie 40 milliseconds according to the standards in use in Europe.

The frames presented on the screen are defined, according to the principle of the invention, as I (x, y, t + KT), where the value of the coefficient K varies from one frame to another, these values being chosen. so that the time interval, between the taking of photographs and the restitution of a point of the image, is the same for all the successive frames.

This condition implies that the successive values of K are different for the left and right views. a first method to achieve this would be to calculate each frame by the equation.

I (x, y, t + KT) = I (x + KP, y, t) where P denotes the value chosen to best approximate the expression 1 (x + P, y, t) = I (x, y , t + T).

The variable P represents the horizontal component of the displacement of the neighboring objects of the position (x, y) between the two frames defined at times t and t + T.

This method assumes the availability of successive values of the variable P, transmitted at the same time as the images or calculated in real time by the receiver. In the absence of knowledge of this variable, the means included in the invention allow an estimation of the frames to be presented, according to the following equation:

I (x, y, t + K T) = (l - K) I (x, y, t) + K I (x, y, t + T). The method proposed according to the present invention, for carrying out this calculation of the frames, is the following:

The signals received from transmission or recording are first separated, as is usually done, into two or three parts:

- or the three color components; - or the luminance and an alternating chrominance signal;

- or else two chrominance signals and one of luminance. It is the latter case which is first chosen for the description of the present invention, although the latter is also applicable in other cases.

These signals are stored in memory, during each of the successive cycles corresponding to the transmission of two complete images, alternately in four subsets of digital memories, assigned respectively to the following frames:

- left odd frame (left view transmitted by the odd lines of an odd order image) in the subset (11); - right odd frame (right view transmitted by the even lines of an odd order image) in the subset (12);

- left even frame (left view transmitted by the odd lines of an even order image) in the subset (13);

- straight even frame (right view transmitted by the even lines of an even order image) in the subset (14).

This complete cycle lasts 80 milliseconds according to the standards in use in Europe which are used as an assumption for the present description, but the invention also applies to the case of STSC standards by which the corresponding cycle lasts 67 milliseconds. After this cycle, the new coded signals are recorded again in the same memories, the previous content of which is no longer of interest.

To restore the image, this cycle is divided into eight successive parts, each lasting ten milliseconds. During each of these parts of the cycle, each of the luminance and chrominance signals is read respectively from both of two of the memory subsets in which the frames of the even and odd images have been recorded respectively. Two successive left fields, or two successive right fields, are read at once. The calculation of the frames to be presented takes place in real time by interpolation devices, which operate so that the apparent delay of each frame is balanced between the views on the left and the views on the right. The resulting signals are transmitted to each of the decoders specific to these signals.

For example, according to one of the embodiments described below, the frames read simultaneously are interpolated according to the ratios indicated in the following table, where each line represents a restored frame, and each column one of the frames recorded in memory, and where each box indicates the part of the recorded frame corresponding to each restored frame: Weft Odd Odd Pair Pair left right left right

Memory (11) Memory (12) Memory (13) Memory (14)

1 _ 1/2 - 1/2 2 1/4 3/4 - 3 - 0 - 1 4 3/4 1/4 - 5 - 1/2 - 1/2 6 3/4 1/4 - 7 - 1 - 0 8 1/4 - 3/4 -

Other examples of frame restitution cycles will be explained later.

The invention will be better understood with the aid of the description below, based on the appended figures, where: FIG. 1 represents, in schematic form, the main elements of the set of the television set comprising the invention ; FIG. 2 represents, in the form of a diagram, an example of a succession of the memories stored, of control signals of the interpolator circuits, and of the interpolation result, of the memories read; FIG. 3 represents, in more detailed schematic form, a first embodiment of all the circuits according to the invention; FIG. 4 represents, in schematic form, a second embodiment of all of the circuits according to the invention; FIG. 5 represents, in schematic form, the main elements of the processor which performs the processing mentioned above; Figure 6 shows, in schematic form, another embodiment of the main elements of this processor; FIG. 7 represents, in more detailed schematic form, the main circuits for accessing the frame memories; FIG. 8 represents, in schematic form, an exemplary embodiment of an interpolator carrying out the processing; FIG. 9 represents, in schematic form, a simplified variant of the interpolator which allows a simpler but almost satisfactory processing; FIG. 10 represents, in schematic form, a complement by which side effects of the treatment can be avoided; FIG. 11 represents, in the form of a diagram, the succession of the data respectively written and read in one of the subsets of memories, during a "short" cycle, in the case of the second embodiment of the invention according to the figure 4; FIG. 12 represents, in diagrammatic form, the main elements of a multiplexer circuit according to this same embodiment; FIG. 13 represents, in schematic form, the essential elements which characterize the use of a pulse generator according to the invention; FIG. 14 represents, in schematic form, an improvement to the interpolators for the case of a spectator who wishes to observe without relief a program broadcast in relief; Figures 15, 16 and 17 show, in schematic form, the main variant elements of the circuit shown in Figure 6; FIGS. 18 and 19 represent, in the form of diagrams, the successions of the memories written and read, as well as the control signals of the interpolators, and the interpolation of the data read, according to various operating modes, according to two embodiments of the invention corresponding to Figures 3 and 4 respectively; FIGS. 20 and 21 likewise represent these various signals according to simplified embodiments of the invention, using the interpolators represented in FIG. 9.

Figure 1 recalls the main elements of the television comprising the invention. There are: - gathered in a sub-assembly (8), the circuits for receiving, demodulating and digitizing the video signal received;

- the memory subsets (11), (12), (13), (14);

- the sub-assembly (41) of the synchronization generators;

- the cathode ray tube or display screen (34); - gathered in sub-assembly (9), the circuits which transform the data read into memory to compensate for space-time distortions, and which include in particular the interpolators and the digital-analog converters.

- the sets of conductors or "buses" which respectively carry the following data:

- bus (36) and (37): data read from memory, simultaneously in the subsets (11) and (13), or (12) and (14);

- bus (38): data to be written into memory; - bus (40): control, identification, synchronization signals. FIG. 2 represents, in the form of a diagram, an example of a succession of the memories stored, of control signals of the interpolator circuits, and of the result of interpolation of the memories read, according to a "long cycle of duration 80 milliseconds:

- on line a, the time scale;

- on line b, the succession of memories entered;

- on lines d, e, f, an example of a timing diagram of the three signals C1, C2, C3 for controlling the interpolators; - on line g, the memories read during each part of the cycle, with the corresponding interpolation reports.

This figure thus gives an example of the operating mode of the circuits according to the invention. Other operating modes, linked to architectural variants, will be indicated in FIGS. 18 to 21. FIG. 3 represents all of the circuits according to a first embodiment of the invention. We find the memory subsets (11) to (14), detailed in twelve integrated circuits (15), (16), (17), (18), (19), (20), (25), (26), (27), (28), (29), (30). Also shown in this figure is the video decoder (10) which extracts after detection the luminance and chrominance signals, as well as the line and frame synchronization signals; the coders (21), (22), (23) which each transform the digital luminance signals to chrominance signals; finally the digital-analog converters (31), (32), (33) which finally transform these signals into analog control of intensity of the beams of the cathode-ray tube (34) of the television set.

The elements mentioned above will form part of the digital televisions which will soon supplant the current analog televisions: they are not part of the invention.

The rest is all of the means (24) necessary for the management of the memories and for the interpolation of the digital signals, means which constitute the invention, and which are summarily represented in this figure in a frame in dotted lines. The central controller (39), in particular, will be described later in more detail.

To avoid that the same memory circuit can be simultaneously written and read, the memory subsets (11), (12), (13) and (14) are each divided into several separate integrated circuits, each for example dedicated to the upper, or middle, or lower part of the frame. A division into two or four integrated circuits is also possible. In this example, each frame is memorized on three integrated circuits of each one a "megabit", organized in words of 16 bits.

In this case, the reading cycle is offset from the writing cycle by about 5 milliseconds, as it appears for example in Figures 18 and 20.

The buses (36) and (37) respectively route in parallel the data read simultaneously in two integrated memory circuits; the bus (38) routes the data to be entered; the bus (40) carries various control and synchronization signals.

The processor (24) also comprises circuits (35) arranged at the interface between the transmission buses (36), (37), (38) and (40) on the one hand, and on the other hand each of the integrated circuits of memory.

Figure 4 shows, in schematic form, another embodiment of the same set of circuits. In this embodiment, the processor _^ can be achieved through integrated memory circuits of less efficient in terms of speed, so a priori less expensive.

Indeed, the memory subsets (11), (12), (13) and (14) are not, as above, each divided into several integrated circuits, but distributed together between several modules or integrated circuits.

The subsets (11) and (12) form, as previously, a first group dedicated to the odd frames, the subsets (13) and (14) a second group dedicated to the even frames.

Each of the integrated circuits (71), (72), (73), (74), (75), (76) has a part constituting the sub-assembly (11), the other half of each constitutes the sub-assembly (12); similarly integrated circuits

(81), (82), (83), (84), (85) and (86) are each divided into a part of the sub-assembly (13) and a part of the sub-assembly (14).

The distribution of each integrated circuit between two subsets can be defined in various ways, such as for example according to the most significant bit of the address, which generally corresponds to two distinct areas of the memory.

As before, each of the integrated circuits is connected, via a multiplexer (77), on one side to the bus (38) which routes the data to be recorded coming from the transformation of the composite video signal (49) by the converters (21), (22), (23), on the other side to the control bus (40), and finally to one or the other of the read data buses (36) or (37). The multiplexers (77) perform the same interface functions as the multiplexers (35) mentioned above, but they also have other functions, in particular consisting in synchronizing the successive write and read phases on each of the memory modules, and to temporarily retain, on delay registers, the data received on the bus (38) respectively until the memory is ready to record these data, or on the contrary the data read too early on the memory so that a bus (36) or (37) is able to transmit them.

In the embodiment described, the data to be entered transmitted by the bus (38) are immediately memorized, so there is no delay register upstream.

It is because of this distribution of each of the memory subsets into several memory modules that each of the subsets (11), (12), (13) or (14) can, during certain phases of the cycle. shown in Figure 2, be in both registration and reading. In fact, the memory concerned is then successively written and read, at a rate as fast as its access time allows.

If the memories are organized according to this variant, the offset of five milliseconds between the start of the periods of registration and reading of the frames, mentioned above, is no longer necessary. The corresponding cycles are shown in this case in Figures 19 and 21.

As above, the data buses (36) and (37) read this data to the interpolators (43) to (45), each dedicated to a luminance or chrominance component, which are part of the central logic unit. (39). The interpolated signals are sent to the converters (31) to (33) which establish the analog control signals of the cathode-ray tube (34). The central logic unit also transmits the control and synchronization signals on the bus (40).

Figure 5 shows more details of the central controller (39). We find there the video decoder (10) and its converters (21) to (23), as well as on the other side the converters (31) to (33) and the cathode ray tube (34) provided with at least one switch electro-optics (42), and part of the memories and communication buses. All these buses communicate with the central controller (39), except the data bus (38) to be entered, where the results of the digital codings are directly collected by the converters (21) to (23). The data buses (36) and (37) terminate at the input terminals of the interpolators (43) to (45), the output terminals of which supply the converters (31) to (33).

The other element of the central controller is the set (41) of synchronization signal counters, which includes a line synchronization counter (46), a frame synchronization signal counter (47), and a generator (48 ) sampling orders

Such a generator will exist anyway in all digital televisions, it has no particular originality. On the other hand, it also transmits to the interpolators (43) to (45) signals C1, C2 and C3 for controlling these interpolators, of respective periods 80, 40 and 20 milliseconds, represented in the diagrams of FIGS. 2 and 18 to 21.

The signal C3 is also directed to the electro-optical switches (42) by which each of the spectator's eyes sees only the views from the corresponding side. These switches are made by any known method: liquid crystals in front of the screen or in glasses, "PLZT", etc.

The realization of the processor has been described so far in the case where each point of the image is defined by three components (red, green, blue, or luminance and two color differences) and where each component is simultaneously memorized, then read and routed by buses (36) and

(37), then processed in real time by the interpolators.

Other memory organizations can be retained, and variants can be adapted to these. The variant described below more specifically relates to the case where only two, and not three components of the signal, are simultaneously stored in each word of the memories (11) to (14) and transmitted by the buses (36) and (37 ).

FIG. 6 shows an exemplary embodiment of the sub-assembly (9) according to the invention, on the assumption that the signal received and stored in memory consists of two simultaneous components: on the one hand the luminance signal, on the other hand a unique chrominance signal, alternately representing differences in blue and red color.

There is mentioned for the record the central logic unit (39) defined above, which includes the synchronization generator (41) and the interpolators (43 to 45), but not the converters (31) to (33).

In the case described here, the sub-assembly (9) comprises only two interpolators (43) and (44). These are respectively connected, upstream, in the example considered, to the first eight and to the last eight conductors of each of the data buses read (36) and (37). The luminance signal from the interpolator (44) is directly transmitted to the input of the converter (33).

The alternating chrominance signal, at the output of the interpolator (43), is sent alternately, by means of a switching circuit (59), controlled by a synchronization signal emitted by the generator (41), and acting simultaneously on all the conductors of the output bus of this interpolator, to the two converters (31) and (32).

The converter (33) establishes, as before, the luminance signal Y directed towards the control of the cathode-ray tube (34). The converters (31) and (32) likewise establish the chrominance signals Q1 and Q2 for controlling the cathode ray tube (34). Figure 7 shows in more detail how the multiplexers

(35), at (77), are inserted between their integrated memory circuit and the processor transmission buses. The multiplexer (35) shown here, corresponding to the integrated memory circuit (18) chosen by way of example, is connected to the read bus (37) alone, while the other multiplexer dedicated to the same part of the image of opposite parity is connected to the read bus (36). The data of the two integrated circuits (15) and (18) are therefore thus read simultaneously.

This multiplexer communicates with its associated memory by a data bus (55), an address bus (56), and conductors (53) and (54) carrying the read and write order signals in good time. from memory. The multiplexer (35) communicates, on the other side, with the data bus to be written (38) by its input terminals (58) and with the read data bus (37) by its output terminals (57) .

It also receives the synchronization signals from the control bus (40). The input terminals (50) are permanently connected, but in a different way for each of the multiplexers (35), each one with the other with the conductors (51) and (52) respectively carrying the two voltages d positive and negative food.

The multiplexer (35) is a simple logic circuit defined and produced according to the rules of the art for the following functions:

- calculate, as a function of the signals transmitted by the bus (40) and of the identification of the multiplexer by its terminals (50), at which times its associated memory is passive or in read or write mode; - calculate, at all times, the address of the word to be entered or read in its associated memory, and indicate this address by the bus (56);

- connecting, at the appropriate times, the data bus (55) of the memory with one of the buses (37) or (38); - give read or write orders in good time by the conductors (53) or (54).

Figure 8 shows in more detail the embodiment of one of the interpolators, by way of example the interpolator (43).

The interpolators are not necessarily identical, if the numbers of bits representing each of the luminance or chrominance signals are not the same. But all the interpolators can be produced according to this model of FIG. 8.

The interpolator (43) has two adders (61) and (62), in which the least significant bit of the result is not kept, and three switches (68), (69) and (70), operating each on the same number of bits in parallel. The adder (61) gives the intermediate bus (63) the half-sum of the contents of the buses (36) and (37). A switch (68) gives, depending on the state of its control signal C1, on the intermediate bus (64), one or the other of the contents of the buses (36) and (37). The adder (62) gives the intermediate bus (67) the half-sum of the contents of the intermediate buses (63) and (64). The switch (69) gives, according to the state of its control signal C2, on the intermediate bus (66), the content of one or the other of the intermediate buses (63) and (64). The switch (70) gives, according to the state of its control signal C3, on the output bus (65), the content of one or the other of the intermediate buses (66) and (67).

This interpolator thus performs the interpolation between the contents of the frames read simultaneously, according to the ratio given by the relation: K = (C2 / 2) + (C3 / 4). Simplified interpolators can also be used.

With these interpolators which have only one adder and two switches, and an example of which is shown in FIG. 9, it is possible to obtain compensation, less exact but which may be acceptable, for space-time distortions; the control signals and the corresponding interpolation ratios are then shown on the diagrams of FIGS. 20 and 21. respectively in the case of the memory structures corresponding to FIGS. 3 and 4. The interpolation between points of the same position of successive frames can, in the case of objects in rapid and regular movement, reveal transitions in staircase, which can be annoying. To remedy this, the result of the interpolation can be filtered in the areas of the image in significant movement.

FIG. 10 thus shows, in schematic form, an exemplary embodiment of such a device. This uses a motion detector, which has two shift registers (116) and (117), each processing the four most significant bits of the luminance signal in parallel. The register (116) is traversed by the signals from the bus

(36), the register (117) by those of the bus (37).

The motion detector also includes a correlator (118), a combinational logic circuit according to techniques considered to be known, which aims to determine whether the two sequences of values present simultaneously in the registers (116) and (117) are, if not , similar with an offset that does not exceed a given number of elements.

For example, to verify an offset with two elements, the correlator examines the signals present on a box on two of these registers; to check for an offset to the nearest four elements, it processes the signals from one cell out of four. Such a motion detector is insufficient to calculate the parameter P defined above, but acceptable to define whether this parameter P is lower or not, in the vicinity of a given point of the image, at a given threshold.

The output signal of the correlating logic circuit (118), possibly composed of several pieces of information in parallel, signifying the results of comparison of the offset with several given thresholds, controls a switch (119) which switches to each digital-analog converter, here the converter (31), the signal delivered by the corresponding interpolator (45), corrected by one of the digital filters (120), (121), or (122).

These digital filters have a function of low-pass filters, the effect of which is to smooth the values representing the successive points of the line represented in the image if the movement is rapid. They can be produced according to any known technique. In a device similar to that of FIG. 10, the digital filters can be replaced by analog filters, each consisting for example of a resistor, a capacitor and an amplification and decoupling stage. In this case, the switch (119) and its filters are placed downstream of the digital-analog converter (31).

Filters of the same type are also inserted on the path of the chrominance signals, or of the color components. They are controlled by the same signal defined by the correlator (118).

The filter system described above can also operate without the motion detector, in the case where sufficient motion information is transmitted at the same time as the image, by known methods such as for example the AHTIOPE signal transmission system. digital data during head-off, or the D2-MAC system which leaves space for a few bytes per line in the channel reserved for digital sound and various data.

According to the embodiment of the memories presented in FIG. 4, the same memory circuits could be found, during certain phases of the cycle of FIG. 2, in read and write mode. To avoid this situation, in the case where this structure of the memories is retained, the invention includes means for alternating the periods of writing and reading on each of the integrated memory circuits.

FIG. 11 represents, in the form of a diagram, the succession of the data recorded and read on a part of the memories, during a representative cycle of a duration of approximately half a microsecond. Line a represents the timescale. Lines b, c, d, e, f and g show the writing phases, denoted E, and reading, denoted L, of the respective data of the memories (71), (72), (73), (74) , (75) and (76). The numbers assigned to the data, in this figure, and indicated by way of example on lines b to g, are arbitrary, insofar as the data are successive only for reading, or for writing, but the counts write and read addresses are independent.

Line h shows the succession of data transmitted by the bus (36). Only the data of even numbers are identified, the scale of the figure being insufficient to represent everything. In fact, the data follow each other in the order of their numbers. It appears, by comparison of the instants of reading the data, on the lines b to g, and of the instants when they are routed by the bus (36), on the line h, a certain delay in the transmission of these data on the bus (36).

This delay is indicated on line i, in units equal to the period of this data on the bus (36), knows approximately 35 to 40 nanoseconds. This delay varies periodically, according to the cycle represented on the figurell, and whose period is equal to twelve units, that is to say between 400 and 500 nanoseconds. During this cycle, each of the integrated memory circuits undergoes two reading phases and a writing phase. Line j shows the succession of data on the data bus (38) to be entered. In the case shown, the data is stored as soon as it arrives by the bus (38).

It appears that the time available for writing or reading data in the memories is equal to four units, or approximately 150 nanoseconds in the example described.

The cycle of Figure 11 is not strictly permanent. It stops during the sweep returns. This interrupt can be used to refresh dynamic memories.

This cycle is carried out thanks to a particular structure of the multiplexers (77), the essential elements of which are shown, in schematic form, in FIG. 12.

The multiplexer (77) shown comprises, among other circuits, two address counters, (88) for writing and (89) for reading, and a switching circuit (90) which, at suitable times, switches the address bus (56) alternately from one to the other of the two values indicated by the counters (88) and (89), according to the cycle described in FIG. 11.

The multiplexer (77) also includes a delay register (79) which temporarily stores the data before transmitting it on the bus (37). This register has several inputs and outputs to produce a variable delay. In the example described, it has two outputs (91) and (92), switched alternately, and a permanent input selected from six inputs (101), (102), (103), (104), (105) and ( 106) by means of a simple logic circuit (93) as a function of the signals permanently received on the identification terminals (50) of the multiplexer (77).

A switching circuit (94) alternately connects the output terminals (91) and (92) of the register (79) to the bus (37), each time that data coming from this register must be transmitted.

The multiplexer (77) also includes the circuits necessary to connect the data bus (55) of its associated memory, depending on the period in the cycle, either to the bus (38) or to the input of the logic circuit (93) . The same description also applies to the multiplexers connected on the one hand to the memories of the subsets (11) and (12), and on the other hand to the other bus (36) of data read.

FIG. 13 represents, in a very simplified schematic way, the essential elements which characterize the signal generator C1, C2, C3 according to the invention, so that it can deliver at the spectator's choice the signals corresponding to one of these three options: see in relief a program in relief, see without relief a program in relief, see a broadcast program without relief. In fact, it can be observed in FIGS. 18, 19, 20, 21 that the signals C1, C2, C3 differ according to these cases.

The television set then comprises two controls accessible to the spectator, symbolically represented as the switches (96) and (97), but which can in fact be combinations of keys on the remote control keyboard. These commands act, according to known techniques, on the circuits of the generator (95). This operates on the basis of two signals at the start of the cycle, of period 80 milliseconds, and of the start of presentation of a frame, of period 10 milliseconds, presented on the input terminals (98) and (99) of the generator. (95).

Another object of the present addition relates to means for improving the appearance of video images recorded or transmitted in relief, for a spectator who wishes not to observe them in relief.

Indeed, the means described above would give the following result in this case: only frames on the same side would be presented, and the viewer would see them on both the odd and even lines. Stationary objects would be split, as if each line was repeated.

This could give the oblique lines a staircase appearance, possibly annoying. This effect is prevented by the following means:

FIG. 14 represents a sub-assembly (100) which can be inserted between each of the buses (36) and (37), on the one hand, and on the other hand each of the interpolators (43) to (45). The processor then comprises twice as many of these subsets (100) as components of the video signal read simultaneously from memory.

The sub-assembly (100) comprises according to the described embodiment: - two memories (107) and (108), of the type known as "cache memory" and each of sufficient capacity for two image lines, and of time access less than half the reading period of the data on the buses (36) and (37), ie 17 nanoseconds in this example; - a memory controller (110), which successively addresses the data received from the bus (36), line by line:

- on the odd addresses of the memory (107);

- on the even addresses of the memory (107); - on the odd addresses of the memory (108);

- on the even addresses of the memory (108); and endlessly repeats the above cycle;

an interpolator (109), of the same type as the simplified interpolator (60) shown in FIG. 9. The control terminals of this interpolator (109) are supplied, by non-original means therefore not described, so that it interpolates the data read in the memories (107) and (108) only when the odd lines are read.

When reading the even lines, the interpolator (109) transmits to the interpolator (43) alternately the data coming from the memory (107) and from the memory (108).

Thus every other line on the screen is obtained by interpolation between two superimposed lines, and the image has a more continuous appearance.

FIG. 6 above represented an exemplary embodiment of the sub-assembly (9) in the case where the memories are organized to retain in a mast two components of the digitized video signal.

Figure 15 shows another embodiment of the same sub-assembly (9). The interpolated digital signals, at the output of the interpolators (43) and (44), are directly transmitted to the digital-analog converters (31) and (33). Analog switching circuit

(78) alternately distributes the analog signal from the converter (31) to the two channels Q1 and Q2 for output of the chrominance signals.

FIG. 16 represents an exemplary embodiment of the sub-assembly

(9) in the event that the memory is organized into eight-bit mats, which contain only one component of the signal; this then alternately represents luminance and chrominance, the latter being alternately composed of color differences in red and blue.

The sub-assembly (9) then comprises a single interpolator (43), at the output of which a digital switching circuit (80) alternately distributes either the luminance signal to the converter (33) or the alternating chrominance signals to the second digital switch (59). This has the same role as above according to Figure 6. FIG. 17 shows another embodiment of the subassembly (9) on the same assumption as FIG. 16. At the output of the interpolator (43), a single converter (31) transforms all the interpolated digital signals into analog . At the output of this converter, a first analog switching circuit (87) alternately distributes the signals to the luminance channel Y and to the input of a second analog switching circuit (78) of the chrominance signals.

This has the same role as previously according to Figure 15. Finally Figures 18, 19, 20, 21, already cited, show in more detail the timing diagram of Figure 2, including the cases of other modes d 'observation of programs.

FIGS. 18 and 19 relate to the case where the interpolators have the structure described in FIG. 8, FIGS. 20 and 21 in the case where these interpolators have the simplified structure described in FIG. 10.

FIGS. 18 and 20 relate to the case where the organization of the memories conforms to the description corresponding to FIG. 3, FIGS. 19 and 21 to the case of the organization of the memories according to FIG. 4.

In each of these figures, line a represents the time scale during an 80 millisecond cycle, line b the succession of memory subsets where the data is recorded.

The lines d, e, f represent the control signals C1, C2, C3. The lines g represent, according to the same conventions as previously in FIG. 2, the memories read during each phase of the cycle and the proportion of their data calculated by the interpolators.

These lines d, e, f, g are repeated three times with indices which respectively represent the following cases:

1 the relief observation of relief programs;

2 observing a program without relief; 3 observation without relief of a program in relief.

In these figures, the much shorter duration of the vertical scan return has not been taken into account.

In these figures, the signal C3, whose role is to control the third switch of the interpolators and the electro-optical switching device (42), is used in certain cases to control only one of these two elements. The circuits described above may be subject to variants preserving the spirit of the invention, in particular when circuits with a higher degree of integration will be available: in this case, certain integrated circuits presented above as distinct will be replaced by a single integrated circuit, in which the functions described above will be carried out respectively by elements of the same integrated circuit, having equivalent roles.

If there are dual data bus memory circuits, or

"double port", or with separate address buses for writing and for reading, functions which, in the description above, are carried out by elements of the multiplexers, will be carried out by elements of the memories themselves. Multiplexers can become useless.

Certain elements described here may be absent from certain embodiments, such as for example the converters in the case where the data would be recorded in analog state in memories of the "CCD" type. The interpolators would then be produced in the form of resistance networks.

The "CCD" memories being sequential access, the above case is only envisaged in the structure of the memories according to FIG. 3. Various elements can also be added to the circuits described, such as for example contrast intensifier circuits, correctors colors, digital or analog mixers, etc.

The processor according to the invention can be included in the television set, or on the contrary constitute additional equipment, connected to the television set and to the video recorder by connectors of functions comparable to the currently standardized socket for "scart television".

Claims

R E V E N D I C A T I O N S

1 Device for improving video images in relief, the object of which is to eliminate a "spatio-temporal distortion", by which to any moving object corresponds an undesirable shift in the relative positions of its left and right images, this device being used in the following hypotheses:

- the signals representing the images come from a transmission on a normal television channel or from a normal video recording;

- the respective views on the left and on the right come from the frames of even and odd order respectively received from the transmission or from the recording;

- These views of left and right are presented to each of the spectator's eyes by means of electro-optical switches operating at the double frequency, that is to say having two frames during the reception period of only one; this device being characterized in that it comprises four memory subsets (11), (12), (13) and (14), in which are recorded successively four frames constituting two complete images, each of which is composed of views left and right received successively, and two sets (36) and (37) of conductors by which the data read simultaneously are routed respectively in two of the memory subsets (11) and (13) or (12) and (14) , these data corresponding to the same point of view on the same side of two images received successively from the transmission or from the recording.

2 Device according to claim 1, characterized in that it comprises means called "interpolators" (43) to (45), by which the data values, routed simultaneously by the sets of conductors (36) and (37), are interpolated in real time in a different way depending on whether it is data representing the left or right views.

3 Device according to claims 1 and 2, characterized in that the sub-assembly (9) of signal processing circuits comprises as many interpolators (43) to (45) as components of the video signal routed simultaneously by the sets of conductors (36) and (37), and switching means (59), (78), (80) or (87), in a number complementary to three of the number of interpolators, by which the interpolated signals are successively directed to the three output channels for the luminance and chrominance signals. 4 Device according to claims 1 and 2, characterized in that each of the interpolators (43) to (45) comprises two adders (61) and (62) and three switches (68), (69) and (70), arranged so that the output of the adder (61) communicates with an input of the adder (62), and that the chain connecting the sets (36) and (37) of conductors to the output of the interpolator via of the two adders (61) and (62), also passes through one of the switches, the operation of which is synchronous with the control of at least one electro-optical device (42) used for restoring the relief. 5 Device according to claims 1 and 2, characterized in that it comprises a generator (95) which establishes the control signals of the interpolators (43) to (45) and of the electro-optical switching device (42), from periodic synchronization signals (98) at the start of the cycle and (99) at the start of each of the frames restored during this cycle, and that this generator (95) is connected to one or two commands (96) and (97), accessible to the user, and being able to modify the control signals of the interpolators and of the electro-optical switching device (42), on the one hand for the observation of programs without relief, and on the other hand for the observation without relief of programs in relief. 6 Device according to claim 1, characterized in that it comprises, on the interface between on the one hand each of the integrated circuits constituting the memory subsets (11) to (14), and on the other hand the sets of conductors (36) and (37), by which the data read in memory are routed, and (38) by which the data to be written are routed, so-called "multiplexer" integrated circuits (35) identical to each other and in number equal to that integrated circuits constituting the memory subsets (11) to (14).

7 Device according to claim 1, characterized in that each of the memory subsets (11), (12), (13) and (14) consists of only part of the integrated circuits or modules (71) to ( 76) or (81) to

(86) of memory, each of these integrated circuits or memory modules being able to record, for a part of the addresses, data from the left views corresponding to the subset (11) in the case of the modules

(71) to (76), or in the case of the modules (81) to (86) in the subset (13), and for the other part of the addresses, data of the views on the right corresponding to the subset ( 12) in the case of modules (71) to (76), to for modules (81) to (86) to the sub-assembly (14). 8 Device according to claims 1 and 7, characterized in that it comprises, at the interface between the sets of conductors (36), (37) and (38) on the one hand, and the integrated memory circuits, multiplexers ( 77) each of which comprises two address counters (88), for the addresses of the data to be entered, and (89), for the addresses of the data to be read, and a switching circuit (90) which, at the appropriate times, makes switch the address bus (56) of its associated memory respectively from one to the other of the addresses of the counters (88) and (89), and that each multiplexer also includes means for temporarily retaining the data read from the memory , before communicating them to the bus (36) to (37), for a variable number of transmission periods on this bus, and among these means a delay register (79) comprising several inputs or several switchable outputs.

9 Device according to claims 1 and 2, characterized in that it comprises, inserted between on the one hand each of the sets of conductors

(36) and (37), and on the other hand each of the interpolators (43) to (45), memory circuits (107) and (108) capable of temporarily retaining the data conveyed by said sets (36) and (37 ), before transmitting them to the corresponding interpolators, each of these memory circuits (107) and (108) having sufficient capacity for the data of two lines of the image.

10 Device according to claims 1 and 2, characterized in that it comprises two shift registers (116) and (117), each capable of processing several signals in parallel, which accumulate several successive values of signals transmitted respectively by the buses (36 ) and (37), and a correlating logic circuit (118), receiving on its input terminals signals from various stages of each of these registers § (117) and (117), and the output signal of which controls the operation of filters (120) to (122), so that the signal representing a point of the image, coming from each interpolator (43) to (45), is filtered with a bandwidth the narrower the movement near this point of the image is faster.

11 Frame memory television, by which successive video frames from a transmission on a normal television channel or from a video recording, can be presented at twice the reception frequency, the television can also be used to observe video images in relief by the alternating views method by means of electro-optical switching devices, characterized in that it comprises four memory subsets (11), (12), (13) and (14) in which are recorded successively four frames constituting two complete images, each of which is made up of received left and right views and two sets (36) and (37) of conductors through which the data read simultaneously in two of the memory subsets are routed, these data corresponding to the same points of view on the same side of two images received successively from the transmission or recording.