FR2587544B1 - Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede - Google Patents

Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede

Info

Publication number
FR2587544B1
FR2587544B1 FR8513633A FR8513633A FR2587544B1 FR 2587544 B1 FR2587544 B1 FR 2587544B1 FR 8513633 A FR8513633 A FR 8513633A FR 8513633 A FR8513633 A FR 8513633A FR 2587544 B1 FR2587544 B1 FR 2587544B1
Authority
FR
France
Prior art keywords
circuits
mask
manufacturing integrated
integrated circuits
programmable options
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8513633A
Other languages
English (en)
Other versions
FR2587544A1 (fr
Inventor
Yves Gaudronneau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eurotechnique SA
Original Assignee
Eurotechnique SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eurotechnique SA filed Critical Eurotechnique SA
Priority to FR8513633A priority Critical patent/FR2587544B1/fr
Publication of FR2587544A1 publication Critical patent/FR2587544A1/fr
Application granted granted Critical
Publication of FR2587544B1 publication Critical patent/FR2587544B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0883—Combination of depletion and enhancement field effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/383—Channel doping programmed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
FR8513633A 1985-09-13 1985-09-13 Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede Expired FR2587544B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8513633A FR2587544B1 (fr) 1985-09-13 1985-09-13 Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8513633A FR2587544B1 (fr) 1985-09-13 1985-09-13 Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede

Publications (2)

Publication Number Publication Date
FR2587544A1 FR2587544A1 (fr) 1987-03-20
FR2587544B1 true FR2587544B1 (fr) 1987-11-20

Family

ID=9322900

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8513633A Expired FR2587544B1 (fr) 1985-09-13 1985-09-13 Procede de fabrication de circuits integres avec options programmables par masque et circuits obtenus par ce procede

Country Status (1)

Country Link
FR (1) FR2587544B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3995172A (en) * 1975-06-05 1976-11-30 International Business Machines Corporation Enhancement-and depletion-type field effect transistors connected in parallel
DE2633557A1 (de) * 1976-07-26 1978-02-02 Siemens Ag Verfahren zur herstellung von integrierten schaltungen mit feldeffekttransistoren vom anreicherungs- und verarmungstyp
US4138782A (en) * 1976-09-16 1979-02-13 International Business Machines Corporation Inverter with improved load line characteristic
US4315781A (en) * 1980-04-23 1982-02-16 Hughes Aircraft Company Method of controlling MOSFET threshold voltage with self-aligned channel stop

Also Published As

Publication number Publication date
FR2587544A1 (fr) 1987-03-20

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Legal Events

Date Code Title Description
ST Notification of lapse