FR2582883A1 - CIRCUIT ARRANGEMENT AND METHOD FOR CONVERTING DIGITAL SIGNAL VALUES INTO AN ANALOGUE SIGNAL. - Google Patents

Abstract

CIRCUIT ARRANGEMENT FOR CONVERTING DIGITAL SIGNAL VALUES TO AN ANALOGUE SIGNAL, INCLUDING A DIGITAL-TO-ANALOGUE CONVERTER AND A DOWN PASS FILTER. UPSTREAM OF THE DIGITAL-ANALOGUE CONVERTER18, A CODING CIRCUIT12 TRANSFORMS THE NUMERIQUEY (K) SIGNAL VALUES INTO PULSE PACKETS22 COMPOSED OF SEVERAL PULSES THAT SUCCEED UNINTERRUPTED AND WHICH HAVE A REPEAT FREQUENCY AT A MULTIPLE FREQUENCY REPEATF OF SIGNAL VALUES. THE PULSE PACKETS22 HAVE A SHAPE THAT IS SENSITIVELY SYMMETRICAL WITH RESPECT TO EQUIDISTANT MIDDLE LINES. A PULSE LOCATED ON EACH SIDE OF THE MIDDLE LINE OF THE PULSE PACKET 22 HAS AN AMPLITUDEN. (K), N. (K) LESS THAN OR EQUAL TO A MAXIMUM VALUE, WHILE ALL OTHER PULSES IN THE PULSE PACKET 22 HAVE THE MAXIMUM VALUE. THE INTEGRAL VERSUS TIME ON A PULSE PACKET22 CORRESPONDS TO THE NUMERIQUE SIGNAL VALUEY (K).

Description

The present invention relates to an arrangement of circuits

  for converting digital signal values to an analog signal

  logic, including a digital-to-analog converter and a wire-

  be low-pass mounted downstream, and a method for converting a digital signal, in particular an audio signal, into an analog signal. Using this circuit arrangement and method, initially analog signals, for example audio signals which

  have been digitized - for example by pulse modulation and co-

  dage - to improve their transmission in a telecommunication network

  indication, can be reconverted at the receiver level into signals

  necessary for reproduction.

  In the planned Integrated Broadband Digital Network (BISDN), high quality stereophonic signals must be transmitted. To digitize signals of this type, it is

  necessary to provide finer levels of quantification,

  deny that each transmitted sample value has, for example, a 15 bit word length. To reconvert the signal values

  digital to analog audio signals before they are reproduced at

  receiver calf, it is necessary to provide converters

  15-bit digital-to-analog (D / A) capable of meeting requirements

  strict linearity gences. However, D / A converters of this

  type are of a very high cost price.

  In a known D / A converter (English patent 1,444,216), the sampling frequency of the digital input values is

  therefore increased, and the word length of the signal values is reduced

  pick. A pulse flow is produced, the average density of which is

  proportional to the signal amplitude. From this impulse flow-

  sions, the analog signal can be reconstituted by means of a wire-

  be low pass. However, to process stereophonic signals from

  high quality, it is necessary to use a sampling frequency

  32 kHz lonnage which, in the known converter, results in very high pulse repetition frequencies (8 to 16 MHz) and therefore in a system clock frequency which is also high if amplitude quantization is used of 15 bits. In addition, a very high precision pulse shaping circuit must -2-

  be provided upstream of the analog post-filtration to maintain

  aunt the pulse surface, taking into account the front and rear flanks. However, the design and construction of a circuit

  pulses of this type are complex.

  The object of the present invention is to convert digitized signals into an analog signal by means of a reduced implementation of technical means and so as to allow reproduction of

high quality.

  According to the invention, this object is achieved by arranging

  circuit management in which there is provided, upstream of the digital-analog converter, a coding circuit in which the digital signal values are transformed into packets of pulses composed of several pulses which follow one another without interruption and which

  have a repetition frequency equal to a multiple of the frequency

  repetition quence of signal values, in which packets

  of pulses have a shape which is substantially symmetrical with respect to

  port to equidistant midlines, in which a pulse located on either side of the midline of the pulse packet has an amplitude less than or equal to a value

  maximum, while all other pulses in the pulse packet

  sions have the maximum value, and in which the integral with respect to time on a packet of pulses corresponds to the value of

  digital signal, and by the method in which the repetition frequency

  tition of the input signal values is increased by interpolati-

  on, in which the word length of the signal values, whose repetition frequency is increased, is reduced, in which a

  error signal is derived from the difference between the values of si-

  general, whose repetition frequency is increased, and the signal values comprising a reduced number of bits, in which the bandwidth of the error signal is limited by a digital filter and the

  error signal is added to the signal values whose frequency

  this repetition is increased, in which the signal values, the repetition frequency of which is increased, are converted into an analog signal, in which the clock frequency components are suppressed by analog post-filtering, in which the values -3-

  signal, whose repetition frequency is increased, are con-

  vertices in packets of pulses which have a repeating frequency

  identical tition and which are symmetrical with respect to successive moments at the increased repetition frequency, and in which the integrals with respect to time of the amplitudes of the different packets

  of pulses correspond to the amplitudes of the digital signal values

entry risk.

  One of the main advantages of the invention is that

  that the circuit lends itself to integration. Clock frequencies born

  about 512 kHz to 2,058 MHz are easily achievable in MOS technique. The necessary D / A converter, provided for a

  maximum word length of 8 bits, is also achievable in tech-

  MOS because it is not subject to strict linearity requirements. The implementation of the means necessary for post-filtration

  analog is extremely reduced due to oversampling.

  The various objects and characteristics of the invention are-

  will now be detailed in the description which follows, made to

  by way of nonlimiting example, with reference to the appended figures which represent:

  - Figure 1, a block diagram of a circuit arrangement

  cooked according to the invention, - Figure 2, the relative power density of the noise signal, minus a quantization error feedback, in the case of a quadruple oversampling, - Figure 3, the density of relative power of the noise signal, minus a quantization error feedback, in the case of an eightfold oversampling, - Figure 4, three embodiments of the error filter used in the circuit arrangement of the figure 1, figure 5, a first form of signal pulses provided by the circuit arrangement of figure 1, - figure 6, details of the signal pulses of figure 5, - figure 7, diagrams illustrating the improvement in linearity obtained with the invention, -4 - - Figure 8, a second form of signal pulses provided by the circuit arrangement of Figure 1, - Figure 9, a third form of signal pulses provided by the circuit arrangement of Figure 1, - Figure 10, a variant of part of the arrangement

of circuits in Figure 1.

  - Via a transmission line 1 - forming part, for example, of a BISDN network -, stereophonic signals

  coded MIC are transmitted to a circuit arrangement in accordance with the

  vention, in which they are converted to analog signals (fig-

  re 1). The circuit arrangement forms part of a terminal which is connected to the network and by means of which the stereophonic signals received

  are reproduced through speakers.

  The sample or signal digital values that arrive

  wind in series on line 1 are sent to a serial converter-

  parallel 2 in which they are converted to parallel form with a word length of q bits. In this embodiment,

  q = 15; transmission line 1 therefore has q parallel conductors

  The islands. In Figure 1, the sequence of input sample values

  is denoted P (N), N being the sequence index.

  Sample values P (N) are received at a repetition frequency of fC = 32 kHz. In an interpolation filter 3, they are converted into a sequence of interpolated signal values Q (K) with the same quantization q. but at a repetition frequency f0 increased by an oversampling factor U. The output of the interpolation filter 3 is connected to the input

  a quantization circuit 6 via an additional stage

  in the quantization circuit 6, the word length of the signal values S (K) coming from the adder stage 4, which arrive in the form of parallel words containing q = 15 bits and which will be explained later, is reduced, so that parallel words of r bits (for example, r = 11) are provided at the output. In a subtractor circuit 8, a quantization error sequence D (K) is formed by subtracting the output signals -5 Y (K) from the quantization circuit 6 from the input signals S (K). In this embodiment, the quantization error values consist of the least significant bits separated from S (K). In an error filter-10, feedback values F (K) are derived from the quantization error values D (K). They are added, in the adder stage 4, to the output signal values Q (K)

  from the interpolation filter 3 to obtain the values of si-

  input S (K) for the quantization circuit 6. If the

  error filter 10 has an appropriate time response, the re-

  quantification error, which is known, has the effect of

  shift the component of the quantization noise spectrum of the

  general output Y (K) of the quantization circuit 6, which is in the audible range, towards higher frequencies, i.e.

  outside the audible range.

  As a first approximation, we can assume that the quantization noise of a D / A converter corresponds to white noise and that it is not correlated with the input signal. The quantization produces a noise signal YSt which is added to the useful signal YNutz at the output of the quantization circuit. By error feedback

  quantization at the input of the quantization circuit 6, we obtain

  holds: = yNutz + t1 - GCZ)] * Yst o Z = eJ2Tt = cos (2Tt) + j.sin (2 f-) f = noise frequency f0 = U * fC = flow rate of Y (K) Amplitude relative noise is -y - YNtiz - = t 1 - G (Z) YSt YSt - 6 -

  If a simple delay element (Z-1) is used for the er-

ror, we then have A-t = 1-z-1 YSt

  We can, for example, use an error filter of degree M in po-

health

1-G (Z) - [1-Z-1] M

  It can be shown that the relative power density D of the corrected noise signal is then obtained using = i.22,., D = 1 * 22 "* sin (1--) {max In Figures 2 and 3 , the relative power density D of the corrected noise signal is represented as a function of the frequency,

  the degree of filter M being taken as a parameter. Figure 2 corres-

  pond to an oversampling factor Ui = 4, and Figure 3 to an oversampling factor - 8. The scale factor 1 / fmax of the ordinate corresponds to the noise signal of a D / A converter without feedback from quantification error. In Figure 3, this value

  is outside the graph because the scale of the

given is enlarged.

  It can be seen in Figures 2 and 3 that the area between

  below the curves and, therefore, the signal power density of

  noise decreases rapidly as the oversampling factor

  and that the degree of filter M increases.

  For M = 4 and U = 4, the improvement in the signal-to-noise ratio obtained

  held thanks to the processing of quantification errors and over-

  sampling amounts to 18.6 dB + 6 dB = 24.6 dB. For M = 2 and U-8, the improvement is already 23.3 dB + 9 dB = 32 dB. The word length of the sample values can be reduced by one bit per improvement -7-

  6 dB. In the first case, the reduced word length is only-

  11 bits instead of 15 bits, and in the second case only

10 bits.

  In accordance with the power density spectrum shown in FIGS. 2 and 3, a much greater reduction in word length could be achieved. However, by deriving the density of

  power, it was assumed that the quantization noise is not cor-

  connected with the useful signal. However, this assumption is only true under certain conditions. Particularly at a noise level

  very low, there is a correlation of this type which limits the reduction

  word length. The curves of Figures 2 and 3 and the diagrams

  improvements in signal-to-noise ratio derived therefrom can therefore only be considered as rough estimates. They

  can only serve to illustrate the trend.

  If M = 4, the equation corresponding to the type of filter proposed is 1-G (Z) = [l-Z-1] 4

= 1-4Z-1 + 6Z-2-4Z-3 + Z-4

or G (Z) 4Z-1-6Z-2 + 4Z-3-Z-4.

  FIG. 4 shows three embodiments of error filters of this type, namely a filter of degree 1 at the top, a filter

  level 2 in the middle, and a level 4 filter at the bottom.

  The sequence of sample values Y (K) supplied to the output of the quantization circuit 6 (FIG. 1) could be obtained via a commercially available D / A converter with a corresponding reduction in quantization, but it would be

  this D / A converter has to have a very large linear

  you. D / A converters of this type are very cost effective

  high and do not lend themselves to MOS or CMOS integration.

  The invention makes it possible to use D / A converters present

  both lower linearity and lower resolution.

  The output of the quantization circuit 6 is connected to the

  entry of a coding circuit 12. In the latter, the sequence of

  their signal Y (K) is transformed into a sequence of values W (U) which is increased by the factor 2P and which, after being converted from

  the digital form in analog form and processed by the step filter

  below, forms the analog output signal NF.

  The coding circuit 12 contains a read only memory (ROM) 14,

  in which a code conversion is carried out according to a procedure

  re explained below, and a counter 16 which provides the addresses for the ROM 14. The counter 16 has a word length of p bits, that is to say that it has p parallel outputs. In the embodiment, p 3 or 4. If the word length of the signal values Y (K) is r bits, it is reduced, in the coding circuit 12, to

s bits, with s = r-p.

  Counter 16 is operated at a frequency fl = 2P * f0 = 2P * U * fc

  and it is reset at frequency fC.

  The signal values supplied to the output of the co-

  12 are transferred to a D / A converter 18. The output of the latter provides packets of pulses 22 which are shown in

Figures 5 and 6.

  The pulse packets 22 consist of voltage pulses 23 of frequency f1. Each packet of pulses is symmetrical about a vertical center line ML. The spacing between the midlines is

T = 1

  2 iU * fC The packet repetition frequency is therefore equal to the

  frequency of repetition of the sample values Y (K), and the integral

  the with respect to the time of the voltage pulses - represented in FIGS. 5 and 6 in the form of the voltage-time surface of a packet of pulses - corresponds exactly to the digital signal value

Y (K).

  -9- The pulse packets shown 22 correspond to a

  oversampling factor U = 4. The period corresponding to the

  input repeat frequency fc is therefore

T 4 * T2

  The low-pass filter 20 provided downstream of the output of the converter

  weaver N / A 18 suppresses the sampling frequency = 128 kHz T2 In accordance with the invention, the output pulses of the

  D / A converter respond to a mixed pulse modulation system

  amplitude and pulse width modulation, the pulse duration also being quantified. Figure 5 shows

  packets of pulses 22 whose area increases from left to right.

  Only the two external pulses Ni (K) and N2 (K) of a packet of pulses (Figure 6) are amplitude modulated, while the

  23 pulses have a maximum amplitude. The number of pulses

  Inner regions of the pulse packet are 2 * P (K).

  The signal value Y (K) is represented by the values 0 to 10. Y (K) = YlOYg9y8y7y6y5y4y3y2ylY0 P (K) Nl (K)

  that is, P (K) is represented by the three most si-

  significant Ylo to Y8, and N1 (K) by bits Y7 to Y1.

  If, for example, a pulse consists of 27 = 128 subsurface and if the maximum number of pulses of a packet is 2P = 16, the geometry of the packet of pulses can be represented in a simple way:

- 10 -

  Nmax - 128 P (K) = Yo10Y9Y8 (of the three most significant bits)

N1 (K) = Y7Y6. '' Y1

  N2 (K) - N1 (K) if To = O N2 (K) = Nj (K) + 1 if YO = 1

  In the ROM 14 of the coding circuit 12, the heights of

  pulses corresponding to the signal values Y (K) are stored in locations 0 to 15 whose addresses are formed by the counter 16. As indicated above, the latter is actuated at the frequency f1 and reset to zero at the frequency fc 'Being given that with such a simple law of formation of the different amplitude values

  signal W (U), the ROM 14 code table has a redundancy

  important dance, ROM 14 can be replaced by a PLA device

  (programmable logic network) which requires much less space-

ment.

  Figure 7a shows the linearity error A of a convert-

  conventional N / A, this error having the shape of a curve showing

  cracked. In the case of a circuit arrangement in accordance with the invention

  tion, when the amplitude LF increases, this curve is repeated several times as the pairs of outer bars of the pulse packets 22 grow. This gives rise to a repetition of the curves of the

  Figure 7a, as illustrated in Figure 7b. Compared to the value fi-

  nal Ymax, the linearity error for this form of signal output is reduced to

AI A

  2p-1 o p = number of bits of counter 16

  2P-1 = maximum number of pairs of bars per package

  impulses. FIG. 7c shows an additional non-linearity A2 in the form of a step error which, in accordance with the law of formation i l -

  explained above, is due to the fact that, for example in a conver-

  weaver N / A with n bits, a bar has n no height but only-

  ment n-l subsurface between pitch steps.

  Table 1 below illustrates this problem in the binary digital system.

Table 1

  Y (K) P (K) Nl (K) YloY9Y8 Y7 --- Y Yo 257 001 000000 i

256 001 000000 (

255,000 1111111i

254,000 1,111,111

253,000 111ii

253! 1111111

-

5,000 0000011

4000 000001O

3,000 0000001

2,000,000,000

1,000,000,000,000

000 0000000 C

- 12 -

Table 2

Y (K) P (K) N1 (K)

YlOy9Y8 Y7 -.YYO it * ..

*. T

255 001 00000001

254 001 00000000

253,000 11111101

252,000! 11111100

* l

000 00000101

4,000 00,000 100

3,000 00000011

2,000 00000010

1,000 00000001

o 000 l 1

  A signal value N1 (K) reaches its maximum digital value

  mum from Y (K) = 254, and cannot be increased for Y (K) = 255. At the signal value Y (K) = 256, the most significant bit group P (K) changes from the value binary 000 to 001, so that, in accordance with the training law explained above, the maximum bar height of

  Nl (K) max = 127 is again established. For the three values of si-

  gnal Y (K) = 254, 255 and 256, the bar height is therefore equal to 127. The monotonous progression of the function is therefore interrupted on

  two positions, as shown in Figure 7c.

  Additional non-linearity can be eliminated by adding

  as a bit, representing the 128th pitch, the length of

- 13 -

  word of the D / A converter 18. In the field of validity of the bit group P (K), the D / A converter 18 then outputs the value 100000002. If the value Ni (K) = 11111112 and if Y0 = 1, this most significant current source is activated once again, in the partial right impulse N2 (K).

  This has a drawback, namely that, in order not to represent

  feel that a quantification step missing, the precision of the conversion

  weaver N / A must be increased by factor 2 (one additional bit).

  To remedy this drawback, the basis of the digital system is therefore modified in the circuit arrangement according to the invention which, from 2S + 1, becomes 2s + 1-2, s being the word length of the converter D / AT. In the present embodiment, o s = 7, the base of the digital system is reduced from 256 to 254. This is illustrated by the

  table 2. The transfer from P (K) = O to P (K) = 1 is carried out at Y (K) = 254.

  Again, N2 (K) = N1 (K) if YO = 0, and

N2 (K) = N1 (K) + 1 if Yo = 1.

  So, if Y (K) = 253, then N1 (K) = 126 and N2 (K) = 127. If

  Y (K) = 254, then N1 (K) = N2 (K) = 0, but P (K) = 1, an integer pair

  bars are set to the maximum value 127. For Y (K) = 255, a new external pair of bars appears because N1 (K) = 0, and N2 (K) = 1. The surface of the pulse packet 22 therefore increases by

continuously.

  However, the total representable number of steps Y (K) max is reduced from 16 x 128 = 2048 to 16 x 127 = 2032. The dynamic domain BF is therefore reduced by approximately 8 0 / oo. However, this is practically negligible. The basic conversion is also stored in the

  ROM 14 in the form of a correspondence table.

  Another benefit of converting signal values

  in pulse packets is that this prevents the appearance of

  Rition of undesirable voltage spikes in the D / A converter 18. These phenomena are generally caused by differences in

- 14 -

  delay in the current switches of the D / A converter, in par-

  particular if these switch alternately, passing through

  example of the numeric value 1000000 at 0111111. This causes the ap-

  appearance of transient currents which result in unwanted spikes - also known as "glitches" - in the

  analog signal and therefore adversely affect the signal-to-noise ratio of the whole

* ble of the circuit arrangement.

  Part of the current sources of the D / A converter is

  switching on at point A of the pulse packet 22 (FIG. 6, par-

  right), and the other current sources are switched on

  cooked at point B. At point C, only part of the current sources are switched off and at point D the other current sources are switched off. Alternate switching on and off can only be done at a very high LF input level, if two successive pulse packets follow each other without interruption. However, this case is statistically very rare. In addition, unwanted noise

  thus caused is then masked by the high noise level.

  Figure 8 shows a second form of output pulses. Unlike the pulse packets 22 of FIG. 6, in each of the pulse packets 22a, a single outer bar increases in height when the amplitude increases continuously,

  this bar 23a modulated by the amplitude being alternately conti-

  at the right and left sides of the pulse pack. Despite this

  asymmetry, the centers of the pulse packets 22a remain sensitive-

  equidistant. The time error is greater than with the form of pulse output of FIGS. 5 and 6, but it remains small compared to the period T of the cycle BF. The maximum time error is

1 1

Atmax 2-f 2P + 1U-fC

  o 2P is the maximum number of pulses per packet of pulses.

- 15 -

  We obtain: AtMa, fNF TNF 2P + Ufc At an audio frequency of fNF = 1/4 * fc = 8 kHz, Atmax_

TNFmin 2P + 3-.

  If we choose an oversampling factor = 8 and a counting length p = 3 as for the pulse packets of figure 8, the maximum time error compared to the LF period is only 0.2 / oo. With respect to this time error, the factor of

  distortion is small and therefore negligible. The advantage of this form-

  me pulse output compared to that of Figures 5 and 6 r5si-

  in that, for the same factor U and the same word length p, the number of partial curves (see FIG. 7b) doubles. The level of

  the linearity error, with respect to the maximum output, is therefore

halved, that is to say

A, = to

  2P On the other hand, for an identical linearity requirement, the

  oversampling factor U can be doubled without being n4-

  stop doubling the frequency of output pulse r8p8ttiton fl. As explained previously, this reduces the word length r of the sequence of values Y (K) to 10 bits for example, and the resolution s of the D / A converter to 7 bits. The p + r address domain of ROM

14 is reduced by 2 bits.

  To save the additional bit, in the conver-

  weaver N / A, to represent the 28Sme subsurface of a bar, the base of the digital system can again be converted using a

  table of correspondences in memory 14 or of a PLA device.

- 16 -

  Since, in this case, we have individual bars mounted one behind the other, and not pairs of bars,

  the base can be reduced from 2s to 2S-l.

  Figure 9 shows a third form of pulse packet output 22b. The pulses are symmetrical with respect to a reference voltage of 1/2 * Umax for example. Depending on the sign of the amplitude of the LF signal, the pulses, relative to the voltage of

  reference, are positive or negative. Figure 9a shows the passa-

  ge by zero of a low amplitude BF wave. It can be seen that there is no time error at low LF input levels. The mistake

  time only occurs for high amplitudes at which it

  the is neutralized by the known masking effect. Zero crossing

  of a large amplitude LF wave is represented in FIG. 9b.

  The particular advantage in this case is that at low amplitudes, the harmonic content produced by the frequency

  sampling is also low. The relationship between the harmoni-

  ques and the amplitude of the LF signal is therefore substantially constant. The analog low-pass filter 20 chosen may therefore have a lower degree compared to the first forms of pulse output. The

  training law applicable to the third form of pulse output

  sion is also stored in the form of a table of correspon-

dances in ROM 14.

  With a 7-bit D / A converter, for example, the center line 1/2 Usax corresponds, for example, to the digital value 10000002. After the LF wave has passed through zero, the digital value

  is slightly lower, for example 0111111. However, as in-

  previously stated, this transition results in an undesirable transient voltage spike because, in this case, all the sources

  of the D / A converter switch at the same time.

  Spurious pulses of this type can be avoided with the arrangement of FIG. 10. In this arrangement, the coding circuit 12 comprises a ROM 24, two outputs of which are connected to a

  gate circuit 27 by lines 25 and, respectively 26. The va-

  their absolute data output from memory 24 is transmitted to gate circuit 27 via line 25, and their sign

- 17 -

  is transmitted via line 26. The exits from the circuit

  door 26 are connected to a first D / A converter 29 by line 28, and to a second D / A converter 32 by a line 30. The resolution of each of these D / A converters 29, 31 is equal to the half that of the D / A converter 18 of FIG. 1. The outputs of the two D / A converters 29, 31 are added in a totalization circuit 32, and the sum is transmitted to the low-pass filter 20

  whose outputs provide the LF signal.

  If the sign is positive, the gate circuit 27 transmits the absolute value to the first D / A converter 29 via line 28, and the highest absolute value 1111112, in the form of a fixed value, to the input of the second D / A converter 31

  via line 30. If the sign is negative, the cir-

  door cooked reverses the absolute value bit by bit, i.e. it forms the binary complement and transmits it to the second D / A converter 31, while all the bits transmitted by line 28 to the first

  D / A converter 29 receive the logical value 0.

  To save the additional bit, in this example, to represent the 26% me subsurface, the base of the digital system in the embodiment of Figure 10 can also be changed from 26 = 64 to 26 -1 = 63, this modification being preferably carried out using a correspondence table

stored in ROM 24.

- 18 -

Claims (10)

  1. Circuit arrangement for converting values   digital signal to an analog signal, including a   digital-analog generator and a low-pass filter mounted downstream,   as described, upstream of the digital converter-   analog (18), a coding circuit (12) in which the digital signal values [Y (K)] are transformed into pulse packets   (22) composed of several successive impulses without interruption   tion and which have a repetition frequency equal to a multiple of the repetition frequency (f0) of the signal values, in that   the pulse packets (22) have a shape which is substantially similar   metric with respect to equidistant midlines, in that a pulse located on either side of the midline of the packet of pulses (22) has an amplitude [N1 (K), N2 (K)] less than or equal to a maximum value (Nmax), while all the other pulses in the pulse packet (22) have the maximum value (Nmax), and in that the integral with respect to time   on a pulse packet (22) corresponds to the signal value   meric [Y (K)] at the input of the coding circuit (12).   2. circuit arrangement according to claim 1, characterized in that the coding circuit (12) comprises a memory   read-only memory (14) and a counter (16) which addresses the read-only memory (14).   3. Circuit arrangement according to claim 1, characterized in that the pulses are formed by the coding circuit (12) alternately on each side of the center line (ML) of the pulse packet (22).   4. Circuit arrangement according to claim 3, ca-   characterized in that the pulse packets (22) are composed of im-   pulses (23) in the form of bars arranged in pairs with respect to a midline.   5. A circuit arrangement according to claim 1, comprising an interpolation filter (3), in which the digital signal values received at a first repetition frequency (fc) - 19 - 2582883 - 19 -   are transformed into repetition frequency signal values   augmented (f0), a quantization circuit (6), in which the name   bre of parallel bits constituting the different signal values [S (K)] is reduced, an error filter (10), in which the quantization error values [F (K)] are formed from the diff - between the input and output signal values of the   quantification (6) and reintroduced into the input of the quantization circuit   tification (6), a digital-analog converter (18), in the-   which the signal values supplied by the quantization circuit (6) are converted into an analog signal, and a low pass filter (20) which suppresses the sampling frequency components in the analog signal, characterized in that between leaving the circuit   (6) and the input of the digital-analog converter   that (18) there is provided a coding circuit in which the output signal values of the quantization circuit (6) are transformed into pulse packets (22) of increased repetition frequency (fo), in that said packets pulses (22) are symmetrical with respect to moments following the frequency of repetition   increased (fo), and in that the integral with respect to the time of the am-   plitudes of each of the pulse packets (22) corresponds to the am-   plitudes of digital signal values [Y (K)] at repetition frequency increased tition.   6. Circuit arrangement according to claim 2, characterized in that the counter is operated at a frequency (f!), Which is a factor of 2P greater than the repetition frequency (fo) of the output signal values the quantization circuit (6), the number p being equal to the number of outputs of the counter (16), and   in that the counter (16) is reset to zero at the repetition frequency   tion (fc) of the input signal values.   7. circuit arrangement according to claim 1, characterized in that the coding circuit (12) comprises two outputs   connected by a door circuit (27) to the inputs of a first converter   digital-to-analog weaver (29) and a second digital converter   rique-analog (31), and in that the outputs of said converts-   digital-analog sisters (29, 32) are connected to a - 20 - totalization (32).   8. Circuit arrangement according to claim 7, characterized in that the signs of the output signal values   [W (U)] and the absolute values of the output signal of the co-   dage (12) are transmitted to the door circuit (27) via a first line (25) and, respectively, a second line (26), in that, if the sign is positive, the absolute value is transmitted to the first digital-analog converter (29) and the   highest possible absolute value (11111112) at the second conversion   digital-analog weaver (31), and in that, if the sign is born-   gative, the absolute value is inverted bit by bit and sent to the   as digital-analog converter (31), while the first   digital to analog converter (29) receives only zero bits.   9. Method for converting a digital signal, in particular an audio signal, into an analog signal, using a   circuit arrangement according to any of the claims   above, including the following phases: the frequency   of repetition of the input signal values is increased by inter-   polation, the word length of the interpolated signal values, whose repetition frequency is increased, is reduced, an error signal is derived from the difference between the interp signal values   whose repetition frequency is increased, and the values of si-   generally comprising a reduced number of bits and having the same repetition frequency, the band of the error signal is limited by a digital filter and the error signal is added to the signal values whose repetition frequency is increased, the values signal, whose repetition frequency is increased, are converted into a   analog signal, clock frequency components are sup-   awarded by analog post-filtration, characterized in that the   signal bits having a reduced number of bits and whose repetition frequency is increased are converted into pulse packets   which have an identical repetition frequency and which are symmetrical   triques with respect to moments following the frequency of re-   petition increased, and in that the integrals with respect to time of the amplitudes of the different packets of pulses correspond to   amplitudes of the digital input signal values.   10. Method according to claim 9, characterized in that the repetition frequency of the digital signal values is   increased by an oversampling factor from 2 to 8.