DE3304028A1 - Method for increasing the precision of a digital-analog converter - Google Patents

Abstract

Method and arrangement for controlling a digital-analog converter, where the analog output signals are generated with a greater resolution and precision than would normally be possible with the number of control inputs of the digital-analog converter. M bit information elements are fed to this converter, whereas the converter is designed for N bit information elements only. The bits in excess of the number N serve to increase by one the signals repeatedly fed to the input of the converter in a specific time period depending on the value of these additional bit information elements. The ratio of the number of modified input information elements to the original total number of information elements provides the precision in the evaluation and conversion of M bit information elements. <IMAGE>

Description

Process to increase the accuracy of a digital

Analog converter.

The invention relates to a method for increasing the accuracy a digital-to-analog converter with a predetermined number of inputs for a Recording of a corresponding number of bit information and with an analog Exit.

There are digital-to-analog converters and analog-to-digital converters of a modern type essentially made up of electronic components in integrated circuits are included. A digital-to-analog converter usually has 8 or 10 or 12 or 14 or 16 inputs to which digital binary information is fed and which then generate a single analog output signal. The greater the number of digital Inputs, the greater the resolution and accuracy of the digital-to-analog converter. The maximum limit of accuracy is determined by the resolution due to the digital information that is fed to the input. E-n digital-to-analog converter is usually used from output circuitry of a digital arrangement that must emit an analog signal in real-time behavior. For example, must a voltage-dependent oscillator via the analog output of this converter Servo motor or an analog display means or the like can be controlled. Often The corresponding digital circuit must also be capable of digital information to generate the more bit information received than actually fed to the input will. In such cases, the most significant bits are assigned to the digital-analog Converter which then increases the resolution and accuracy of the analog output but is also limited.

The object of the present invention is a method and to enable an arrangement for controlling a digital-to-analog converter, which allows a higher resolution and accuracy to be achieved than actually the number of control inputs of the digital-to-analog converter would normally allow.

This is achieved in that a digital identifier consisting of more than N identification bits are divided into a first digital partial identification from N-bit values of the first-mentioned digital identifier in a second digital partial identifier from the remaining, less significant bits of the aforementioned identifier and where a Value unit (one bit e.g. 's1 ") added to the first digital partial identifier mentioned is to generate a new first digital part identifier and continues to be a third digital partial identifier repeats the digital input of the digital-to-analog converter is supplied at certain time intervals, this third partial identifier either the first digital partial identifier or the new first digital partial identifier, i.e. the partial identifier increased by one, where the ratio of the number of times per unit of time that the third partial identifier is assigned to the digital input if they are equal is supplied with the new first digital identifier, for the total number of times per Time unit at which the third digital identifier is sent to the digital input is approximately equal to the value of the second digital identifier.

The fact that for the evaluation of an input formation If this evaluation is presented several times, there is the possibility of corresponding Change of the originally entered information depending on the value these minor bits in a simple manner provide additional information for the To determine the accuracy of the output information.

According to a further embodiment of the invention is an arrangement for Feeding a digital identifier to a digital-to-analog converter with a digital one Input and prescribed number of N-bit values provided with an analog output, in which a low-pass filter connected to the analog output is provided.

Implementation is simple by means of this arrangement of the method according to the invention possible.

The following is an exemplary embodiment of FIG Invention described.

The FIG 1 shows a conventional arrangement that is used to control a Digital-to-analog converter is used.

FIG. 2 shows a binary number which is identified with 20 bits.

3 shows timing diagrams A to F to explain how a digital Signal is repeatedly fed to a digital-to-analog converter according to the invention.

The arrangement shown in FIG. 4 corresponds to the digital-to-analog converter according to the invention.

FIG. 5 shows in detail the control unit 22 of the digital-to-analog converter according to FIG 4.

6 shows a modified embodiment of the invention Arrangement according to FIG 4.

FIG. 7 shows a 24-bit binary number which is the input of the arrangement 6 can be supplied according to FIG.

FIG. 8 shows a table with words represented in bits, which be recorded in a memory of the arrangement according to FIG.

FIG. 9 shows a regeneration memory that is used for input of the words according to Table 8 is used.

In FIG 1 it is indicated how a digital-to-analog converter DAC from a signal memory LA receives a 16-bit parallel input. The digital-to-analog converter converts the number of bits into an analog signal and transmits this via output 14 away. The digital-to-analog converter shown is a so-called? 6-bit converter, The signal memory LA stores at least 16 bits and carries these signals continuously the 16 output lines 17 to. These 16 bits identify those in the signal memory recorded identifier. The signal memory LA changes its state accordingly the signals7 its 16 input lines 18> upon receipt of a corresponding one Trigger pulse over the line 20, offer.

If a new digital identifier over the parallel lines 17 to the Digital-to-analog converter DAC is fed, the analog signal at the output changes 14 of a predetermined level, that of a predetermined digital identifier X die so far was offered by the digital-to-analog converter, corresponded, in a new level, to the now corresponds to the new digital identifier offered. The period in which the analog signal is converted from one level to another level, in particular the period required for the analog signal to change from a minimum level to a maximum level is referred to as the "settling time" of the digital-to-analog converter. In known digital-to-analog converters, these setting times range between a minimum of about 1 msec.

(ice) to a maximum of nearly 50 microseconds (s). The setting time a digital to analog converter is much less when the digital input is only changes by a low-value identifier bit. In the arrangement according to the present Invention can Digital-to-analog converter with any setting times be used. For the insertion in the arrangement but for the purpose of setting this setting time must be known in advance.

FIG. 2 shows an identifier consisting of 20 bits (namely the code number 00000000010110101011), which consists of two partial identifiers, namely the first Partial ID MSB with 16 most important bits and a second partial ID LSB four minor bits. If the first identifier consists of 20 bits to convert to analog Form would be offered to the digital-to-analog converter according to FIG 1, so could there only the 16 bits of the first partial identifier are sent to the digital-to-analog converter. The additional four bits of the second partial identifier would be lost. At best the 16 bits of the first partial identifier could be rounded up if the value of the second part identifier exceeds 1/2. In the example shown, if the first Partial identifier 0000000001011010 is rounded up to 0000000001011 011.

In the present invention there is provided a method and an arrangement used, which allows the retention of a 20-bit resolution of the overall identifier, when fed to a digital-to-analog converter with fewer than 20 input lines will.

It is assumed that a 20-bit identifier has been calculated and it is necessary to convert this 20-bit identifier into an analog value, It is also assumed that a 20-bit digital-to-analog converter is either not used Is available or is too expensive for the specific use. In such a Case, a digital-to-analog converter with less less than 20 inputs, for example with 60 inputs. This is to be controlled in such a way that on Output the same result and accuracy is achieved by a 2-bit digital-to-analog converter could be achieved. The control function required for this is explained with reference to FIG.

It is assumed that a 16-bit digital-to-analog converter is available and the supplied signals represent a 16-bit identifier which repeats are fed to the 16-bit input lines of the digital-to-analog converter. According to The example shown in FIG. 3 uses this identifier, the so-called digital-to-analog converter Input identifier ", sent to the digital-to-analog converter and then every four milliseconds renewed (ms). We refer to this four millisecond time as the "pulse frame period". Accordingly, during a "superordinate pulse frame" period of 64 milliseconds a 16-bit input identifier is offered 16 times. This pulse frame period of four milliseconds and this superordinate pulse frame period of 64 milliseconds are with their Assumptions of 4 and 64 are just an example.

It can of course be nearly ten times that of a frame period The setting time of the digital-to-analog converter used can be reduced. The parent Pulse frame period should be a certain multiple of the pulse frame period and preferably in relation to the number of binary bits in the second partial identifier LSB stand.

Contains the value of the identifier supplied to the digital-to-analog converter either N most significant bit values MSB corresponds to the original identifier or the N-bit identifier increased by one (MSB + 1). The ratio of 1. the number of times per unit of time that the ID of the digital-to-analog converter entered corresponds to the identifier MSB + 1, to 2. the total number of times per unit of time, which the input digital-to-analog conversion identification has been supplied essentially gives the value of the third partial identifier LSB, which contains the least significant bits in the Represent overall identifier. This means, with time units of 4 milliseconds per pulse frame and of 64 milliseconds per higher-level pulse frame, as in the Line A in FIG. 3 is shown, the digital-to-analog converter identification is only the A fraction of the time from 1/16 corresponds to the value MSB + 1 if the second partial identifier 0001 is as indicated on line B. If the second part identifier corresponds to LSB 0010 the digital-to-analog converter input identifier for the time portion of 2/16 is the same MSB + 1 as indicated on line C.

If the second partial identifier corresponds to 1000, this is the digital-to-analog converter input identifier only 8/16 or 1/2 fractions of the time equals MSB + 1 as indicated in line D. If the second sub-identifier corresponds to 1110, this is the digital-to-analog converter input identifier only 14/16 or 7/8 fractions of the time equals MSB + 1, as indicated in line E.

When the second sub-identifier is 1111, it is the digital-to-analog converter input identifier 15/16 fractions of the time equals MSB + 1, as shown in line F.

From the above it can be seen that the portion of the 16-bit identifier is fed to the digital-to-analog converter, the identifier of the most important bits MSB is increased by the fraction of 1 as determined by the value of the Identifier the least significant bit is marked LSB. Provided that the setting time of the digital-to-analog converter is sufficiently short for the To add changes to the various entered identifiers, these analog outputs are used on average, the resolution corresponds to the original 20-bit identifier. According to a further embodiment of the invention, the analog output is smoothed and aligned by means of a low-pass filter.

Based on FIGS 4 and 5 is an embodiment of the invention Arrangement for carrying out the method described above explained. These Arrangement is extremely fast, with the individual pulse frame and the parent Only claim the pulse frame for extremely short times. 4 shows a digital-to-analog converter with = E input lines, denoted by 17, which come from the signal memory LA. This latch is over 16 input lines, labeled 18 and over a control line 20 is connected to a controller CU. The control unit CU receives Signals that correspond to a 20-bit identifier via twenty input lines, the are denoted by 24 and receives a clock signal via an input line 26 from the clock generator TG. The analog output signal of the digital-to-analog converter DAC is fed to the low-pass filter 30 and thus its output 32 via the line 14.

Details of the control unit CU are shown in FIG. The control contains a 20-bit memory 34 for receiving and storing the digital identifier, which are fed to the input lines 24.

A partial identifier MSB, which consists of the 16 most significant bits of the entire stored identifier in memory 34 are formed, are about Lines 38 are fed to a half adder 36. It will either be a 1 or a "0" is added to the partial identifier MSB, depending on the signal that is sent to a other input 40 is fed to the half adder and the result (either the Partial ID MSB or the partial ID MSB + 1) is transmitted via the 16 output lines 18 passed on.

A partial identifier LSB is made up of the four least significant bits of the Overall identifier which is temporarily stored in the 20-bit memory 34 is formed. These Partial identifier LSB becomes a 256-bit memory RoM46 via four address lines 44 forwarded. Another 4-bit identifier is generated by a 16-stage counter 48 and also fed to the memory RoM46 via four address lines 50. Of the The counter receives clock pulses at half the clock speed from the clock generator TG a flip-flop 52 and an input line 54. The inverse flip-flop state is used as the start signal and fed to the signal memory LA via line 20.

The 256-bit storage locations in the RoM46 memory are eight Addressed bit signals which are fed to the input lines 44 and 50. Of the The contents of the RoM46 memory are used for "1" and "O" values in the half adder 36 in the reference frequencies which are necessary for the second partial identifier LSB, which appear on lines 44, are to be marked with a mean value. In other words, the 16-bit pattern is as shown in lines B to F in FIG is selected using the 4-bit address appearing on lines 44. The memory ROM45 is dependent on the 4-bit address, which is on the lines 50 appears to be controlled via these 16 bits.

The low-pass filter 30 is used to generate the average analog output value on line 14 according to the repetition frequency of the higher-level pulse frame.

The period of the pulse frame can be relatively short: in the Order of magnitude of microseconds (s).

As described above is the pulse frame period of the circuit but preferably at least 10 times the setting time of the digital-to-analog converter DAC, so that with a setting time of this converter in the order of 1 to 50 ps the pulse frame period is on the order of 10 to 500 it is. For one superordinate pulse frame with 16 pulse frames, the superframe period is in the order of magnitude from 160 to 8,000 fs or 0.16 to 8 ms. This thus becomes the pulse frame rate on the order of 2 KHz to 100 KHz and the frequency of the higher-level pulse frame are on the order of 125 Hz to 6.25 KHz.

The cut-off frequency of the low-pass filter is preferably close to half the frequency of the higher-level pulse frame. SO is for example if the frequency of the higher-level pulse frame is 3 KHz, the switch-off frequency be close to 1.5 KHz. In general, the low-pass filter should be an appropriate one Switch-off delay at the frequency of the higher-level frame or that above Frequency to avoid oscillation components of the analog signal and the Run through average DC vegetation.

6 shows a second exemplary embodiment of the invention. at This embodiment is controlled by a programmed microcomputer MCU is formed that has both the 16-bit output signals in parallel above the lines 18 and the start signal on the line 20 is generated. The rest of the arrangement is identical to the arrangement according to FIG.

The microcomputer MCU can be programmed so that the number of required patterns (superordinate pulse frames) are repeated every 800 ps; this means a frequency for the higher-level pulse frame of about 1.25 KHz. This is a useful speed for an 8051 microcomputer, which can easily be done with a 50 ps pulse frame period program or with a program which can be slightly below 50 µs and with an interruption of 50 ps starts. In this case a digital-to-analog converter is required with a response time of 5 fs and a low-pass filter with a cut-off frequency of about 625 Hz should be used.

In general, the faster the digital-to-analog converter (e.g. the shorter the setting time) and the higher the repetition frequency of the bit pattern which is fed to the input of the digital-to-analog converter, the higher is the resolution of the system and the easier it is for the output signals of the To filter the digital-to-analog converter. The low-pass filter can be a simple RC filter or an LC filter or an on-switching capacitance filter or any other be active filter. There is also the possibility of installing the filter in the digital-to-analog converter to be integrated, especially if the response time of this converter has a filter effect at certain repetition frequencies. It is also possible to use the To do without filters if the arrangement itself has its own filter function. If, for example, the digital-to-analog converter DCA is used, a mechanical one is used Controlling sequence control can do this Control itself a flywheel effect have, i.e.

the analog input signal can be delayed.

The function of the microcomputer MCU eLn FIG 6 is now based on the 7-10 described.

FIG. 7 shows a 24-bit identifier, which can be used as a variable via lines 58 are fed to the microcomputer MCU. The two most significant bits of this identifier, byte 1 and byte 2 form the 16-bit partial identifier MSB? which the signal memory LAT via lines 18 and thus via lines 17 to the digital-to-analog converter DAC 'is supplied. At certain time intervals, a "1" becomes this identifier respectively.

added to this word before storing this word on the signal LAT is forwarded.

The least significant byte, byte 0, is used as a memory which contains the data for modulating the 16-bit partial identifier MSB.

The four most significant bits of byte 0 are rounded up first and then shifted four places, as indicated in FIG. 7, by a 4-bit address (Index, reference address) for a 16 x 16 modulation data table, which is present in memory. A modulation data table for a 16-bit parent The pulse frame is shown in FIG. One of the 16 lines or spaces (0 to F in hexadecimal) are addressed and the 16 bits available at this point are stored in a shift register SR, as shown in FIG. 9, is read in. The content of this register SR will then shifted to the left and returned to the same line in the data table. During this cycle, the left most significant bit ("O" or "i) becomes the right most significant bit Place of the memory given and also in a holding memory 62 for addition to Part identifier MSB, which corresponds to a 16-bit word, is stored.

Finally, the functional sequence of the micro is described with reference to FIG. Dasi -komprocessors MC lrd started repeatedly by means of an interrupt pulse, which all 50 are fed to the corresponding interrupt input of the microcomputer will. The program provides the 24 bit, mutable input, which is the input lines 58 are fed safely. Then the number 8 becomes in hexadecimal form Byte 0 added to round up the four most important bits. When the four least significant bits have a value less than 8, the four most significant bits become Bits stay the same. If the four least significant bits have a value 8 or greater the four most significant bits will be increased by one.

If the four most significant bits are all before the rounding up step would be, these bits would all be wandered to 0 and they would be accompanied are from an output signal. In this situation a 1 becomes immediately the first partial identifier added to the 16-bit word formed by byte 1 and byte 2.

Normally, when there is no output signal, the bit values are of byte 0 shifted four places by an index number or a note identifier form. This identifier is used for a word from the modulation data table to choose which one is in memory. As explained above, the Table word, which is addressed, shifted one bit position to the left and then saved again in the table. If the left most significant bit in the Table word was a 1t before moving and the transfer command was set was, will a 1 to the 16-bit MSB word, formed by byte 1 and byte 2 are added. If no carry command has been set, this will be 16-bit MSB word (byte 1 and byte 2) directly via lines 18 to the signal memory LAT and thus give 10 to digital = analog fitJnsetzer.

If a "1" corresponds to the 16-bit MSB word, formed by byte 1 and byte 2 has been added, the result is first for overflow checked.

In an unusual case, if the 16 bits were all 1, would adding a "1" will set all bits to "0" and generate an overflow. if when this happens, all bits of this word are reset to "1"; for example, the maximum value that can be fed to the digital-to-analog converter.

After the 16-bit result on the output lines 18 of the microcomputer MCU have been fed, the program is ended and waits for the next one Interruption.

The embodiments of the invention described above show a method and arrangement around a 20-bit identifier with the aid of a 16-bit digital-to-analog converter to evaluate. The arrangement according to the invention is based on the specified accordingly Bit numbers not bound.

6 claims 9 figures Blank page

Claims (6)

Claims 1. A method for increasing the accuracy of a digital-to-analog converter with a predetermined number (N) of inputs for receiving a corresponding one Number of bit information and with an analog output, d u r c h g e k e n n z e i c h -n e t that a digital identifier consists of more than N identifier bits is divided into a first digital partial identifier (MSB) from N bit values of the first mentioned digital identifier and in a second digital partial identifier (LSB) from the remaining, least significant bits of the aforementioned identifier and where a unit of value (a bit e.g.;? 1n) is added to said first digital partial identifier by one generate new first digital partial identifier (MSB + 1) and continue to generate a third digital partial identifier repeats the digital input of the digital-to-analog converter is supplied at certain time intervals, this third partial identifier either the first digital partial identifier or the new first digital partial identifier, i.e. the partial identifier increased by one, where the ratio of the number of times per unit of time that the third partial identifier is assigned to the digital input if they are equal is supplied with the new first digital identifier, for the total number of times per Time unit at which the third digital identifier is sent to the digital input is approximately equal to the value of the second digital identifier. 2. Arrangement for supplying a digital identifier to a digital-to-analog converter with a digital input and a prescribed number of N-it values and with an analog output, d u r c h g e ke n n n z e i c h n e t that first means for identifying a digital identifier with more than N Bit values, second means, dependent on the first means, for storing a first digital part identifier consisting of N most significant bit values of the first digital identifier and third storage means dependent on the first means a second digital partial identifier consisting of the remaining, low-value ones Bit values of the first-mentioned digital identifier, as well as fourth means for adding a Unit (of a bit value 1) for the first digital part identifier for the purpose of generating a new partial identifier (MSB + 1) and finally fifth means for repeated feed a representation of the third digital partial identifier for the digital input of the digital-to-analog converter at certain intervals, the third digital identifier being either equal to the first digital partial identifier or equal to the new first digital partial identifier, which is increased by one, where the ratio of the number of times per unit of time, to which this third digital partial identifier is fed to the digital input, if it is equal to the first digital identifier changed, for the total number of times per unit of time at which this third digital partial identifier is assigned to the digital input is fed and this is essentially equal to the value of the second digital Partial identification is provided. 3. Arrangement according to claim 2, d a d u r c h g e k e n n z e i c h n e t that the unit of time corresponds to N times the normal interval. 4. Arrangement according to claim 3, d a d u r c h g e -k en n z e i c h n e t that one with the analog Output connected low-pass filter is provided. 5. Arrangement according to claim 4, d a d u r c h g e -k e n n z e i c h n e t that the cut-off frequency of the low-pass filter is approximately 1/2 of the repetition frequency the unit of time. 6. Arrangement according to claim 2, d a d u r c h g e -k e n n z e i c h n e t that the setting time of the digital-to-analog converter is significantly less than is the repetition frequency of said normal intervals.