FR2574238A1 - Phase-shifting device for digital transmission systems - Google Patents

Abstract

The present invention relates to the phasing of digital transmission systems and more particularly its application to the switching of radio wave channels. The invention consists essentially in writing the information arising from the back-up channel into a memory in time with a write clock signal Hi derived from the clock signal of the back-up channel and in reading this information in time with the read clock signal Hi<'> the phase of which is locked and shifted incrementally with respect to the write phase. Application to all transmission equipment.

Description

The present invention relates to the phasing of digital transmission systems and more particularly to its application to switching for microwave links.

In fact, in microwave transmission systems, one channel. backup must be able to replace an entire switching section for an unavailable channel. The usual reasons for such switching orders are fading on a service channel, maintenance or faults. A switching order is issued thanks to the order flights, for example following the result provided by an appraiser. quality. It is imperative that this backup channel transmitting data and clock information identical to those of the faulty channel is in the same phase state as the backed-up channel, otherwise the equipment located in sval would lose their synchronization as a result of the fault. loss or addition of information.

In this equipment for microwave links, it is not uncommon for the phase shift between two channels to correspond to a time greater than one clock period.

It is very difficult to predict the phase difference of the clock signals, on the one hand, and of the data, on the other hand, of each channel, the backup channel having to be equally operational for n channels almost instantaneously. . THE various digital trains have offsets that can reach several clock periods due to differences in the transmission mix, aging of equipment, temperature variations, etc.

It is therefore necessary to prepare the digital trains to be switched in order to adapt them in phase before switching them.

On the other hand, the phase adaptation of the trains must be combined with the permissible gauges by the equipment located downstream, the junctions for example. To this end, test devices aiming to prepare digital trains of data have already been described aiming to provide a request for phasing of digital trains. Thus, the applicant's patent 2 505582 describes digital train test systems formed, for example, of data correlators and phase discriminators. These test systems provide a signal representative of the phase shift at the input of ur. phase shifter.

A phase shifter system has already been described in the prior art. Thus, I patent 2,505,582 of the applicant describes a system with a variable phase shifter. It essentially consists in arranging a large number of delay lines, each line allowing an elementary phase shift representing a fraction of the clock period of the digital trains.

Such systems perform discontinuous phase jumps compatible with high rate transmissions, for example 140 Obits, but they introduce difficulties in achieving large delays at lower rates.

The i..nxention relates to a phase shifting device suitable for all types of equipment as well on cables as optical fibers, microwave links or others, as soon as it is a phase correction between two transmission media .

In particular, the invention aims to compensate for a phase difference between two digital signals or between two clocks.

The device of the invention consists essentially in writing the data D in a buffer memory 2 at the rate
x me of a write clock H deduced from the clock H 'in x cident, - to be kept in memory 2 for 2p periods of lthcr- log H', p being a natural number, a. extract these data from memory 2 at the rate of a clock Hi deduced from that supplied by an oscillator controlled by a. error voltage, said error voltage resulting from the superposition of the phase difference between the writing Ci and the reading e obtained by a phase discriminator and.
s phase difference e between the same transmitted data,
e for example, by two different transmission media, said phase difference ff being expressed as a voltage at the output of a digital to analog converter addressed by a counter, said counter being incremented by the digital offset signal supplied by known test equipment in themselves.

According to one characteristic of the invention, the counter 5 has m positions, m abutting as a function of the dimension 2p of the memory 2 and of the phase jump d
The phase shift device of the invention confers great flexibility of operation.

Other advantages and characteristics will become apparent on reading the following description illustrated by the drawings.

FIG. 1 represents a general view of the phase-shifting device, according to the invention, in its application to the switching of digital trains for radio-relay systems.

FIG. 2 is a timing diagram regulating the writing and reading in the memory.

With reference to FIG. 1, the information coming from the spare channel is received by an equalizer system 1 which regenerates the incoming signal and applies the data, for example binary, D 'to the input of a buffer memory 2. Likewise,
x the clock signal H 'from the emergency signal is applied
x at the input of a write counter 3 which regulates the writing of data D> in this memory 2.

x
It is appropriate to give the system of the invention a phase variation range from 0 to 2p binary elements corresponding to urL variable time t offset between the incoming and outgoing data of the buffer memory 2. The write counter 3 provides a write clock signal Hi triggered by the rising edges of clock signal B 'of the
x spare channel called channel x, this clock signal H. having a period of 2p elements and allowing the recording in buffer memory 2 of 11 binary elements i of the incoming stream D '.

x
Thus, each binary element is kept in the buffer memory 2 for 2p periods and can be available at the output of this memory with a delay with respect to its appropriately chosen writing time and between 0 and 2p periods. Referring to the timing diagram of FIG. 2, the writing of the bit BE has been shown during a clock period H. for which 2p is equal to 8. In the general case, p is a natural integer.

To read this memory 2, the read clock Hi must be phase-locked to the write clock H. in order to
ii not to lose information. On the other hand, to ensure the phase coincidence of the data transmitted on the channel to be backed up and on the backup channel, it must be possible to modify the phase difference between the write and read clocks.

To this end, an OR gate 4 receives a phase shift signal G from one of the n channels capable of being backed up by channel x, only one being in the request state.

These shift pulses are well known from the prior art; they are provided either by a phase descriptor device, or by a correlator, or by a combination of the two as in the patent 2,505,582 of the applicant.

This shift signal G increments a counter 5 which provides, at the output, a binary number between 0 and m, m being suitably chosen. This binary number is applied to the input of a digital to analog converter 6 which supplies an offset voltage g to the input of a circuit 7
e addition. This circuit 7 also receives a voltage coming from a phase discriminator 8 which results from the comparison of the phase of the write clock H. with the phase supplied by a voltage-controlled oscillator 9. The addition circuit 7 outputs a resulting voltage which is filtered by means of ur. low-pass filter 10 then applied to the input of oscillator 9 in order to control it in voltage.

At the output of this oscillator 9, a read signal HL is obtained applied to the read counter 11 of the memory 2.

The read clock Hi of the counter 11 deduced from the clock HL then makes it possible to read the data stored in the memory 2. In fact, as represented in the timing diagram of FIG. 2, the clock signal H ′ is formed of three signals making it possible to cover the eight possible states of the clock signal HL. The counter 11 is essentially a counter by 2, by 4 and by 8, making it possible to restore in reading the phase g of reading in the memory.
s turne is then t = 8 - o + as can be seen on
sie the chronogram between D 'and D
xx
In practice, it is advantageous to choose, on the one hand, the size of the buffer memory 2, on the other hand, the number m of positions of the counter 5 as a function of the necessary phase jump step and therefore to adapt it. at online digital speed. Thus, for a memory of 2p binary elements and wishing a phase jump of 1 / d binary elements, d
d being a natural number, it is necessary to choose a counter 5 having 2 pd = m positions. The binary number supplied by counter 5 is instantly applied to converter 6 and converted into voltage. This offset voltage makes it possible to obtain 2pd phase positions incrementally and cyclically. The; Rapidly triggered phase jumps are furthermore lisd sés by virtue of the phase loop of the invention.

In practice, we choose to adjust the phase of
s the read clock so that the error voltage obtained at the output of the addition circuit 7 is zero when the phase shift is at the center of the variable range. it then suffices to adapt the quantities p and d in an appropriate manner according to the a.ractérìstiques of the intended application.

Claims (2)

1 - Phase shifter device for a digital transmission system comprising means for receiving data D 'at the rate of a clock H', means for transmitting these data at the rate of a reading clock H ', said clock Hi having the same frequency that the clock H's is positive characterized by the fact that the data D 'are ins x written in a buffer memory 2 at the rate of a write clock H deduced from the incident clock H ', are kept x in memory for 2p periods of the clock H ', p being a x natural number, and are extracted from memory 2 at the rate of a clock Hi deduced from that supplied by an oscillator controlled by an error voltage, said voltage d: '- error resulting from the superposition of the phase difference between 11 writing 0 and reading Q obtained by a disorimi 1 phase s nator, and of the phase difference O between the e my data transmitted for example by two dlfférent transmission media, said phase difference O being ex e award-winning in voltage at the output of a digital-to-analog converter addressed by a counter, said counter being incremented by the digital offset signal supplied by test equipment known per se. 2 - Device according to claim 1 characterized in that the counter 5 has m positions9 m being fono ti.on of .la dimension 2p of the memory 2 and of the phase jump 1 / d.